IOb-SoC by IObundle

IOb-SoC

SoC template comprising a RISC-V processor (iob-rv32), an SRAM memory subsystem, a UART (iob-uart), and optional caches and AXI4 connection to external DDR.

Clone the repository

git clone git@github.com:IObundle/iob-soc.git

Ssh access is mandatory so that submodules can be updated.

Update submodules

git submodule update --init --recursive

Edit the system configuration file: /hardware/system.mk

To configure IOb-SoC the following parameters are available:

FIRM_ADDR_W: log2 size of user program and data space, from 1st instruction at address 0 to the stack end at address 2FIRM_ADDR_W-1

SRAM_ADDR_W: log2 size of SRAM, addresses from 0 to 2SRAM_ADDR_W-1

USE_DDR: assign default to 1 if DDR access is needed or to 0 otherwise. Instruction and data L1 caches will be placed in the design, connected to an L2 cache, which in turn connects to an external DDR controller. This parameter can also be passed when invoking the makefile.

RUN_DDR: assign default to 1 if the program runs from the DDR memory and 0 otherwise. This parameter is ignored if USE_DDR=0. If USE_DDR=1 and RUN_DDR=1, the SRAM memory can be accessed when the address MSB is 1. If USE_DDR=1 and RUN_DDR=0, the DDR is used to store data only; it can be accessed when the address MSB is 1. This parameter can also be passed when invoking the makefile.

DDR_ADDR_W: log2 size of DDR, addresses from 0 to 2DDR_ADDR_W-1

CACHE_ADDR_W: log2 size of addressable memory; it should be greater than FIRM_ADDR_W to allow to allow accessing DDR data outside the program scope.

INIT_MEM: assign default to 1 to load a program received by the UART and boot from it, or to 0 otherwise. This parameter can also be passed when invoking the makefile.

BOOTROM_ADDR_W: log2 size of the boot ROM, which should be sufficient to hold the bootloader program and data.

PERIPHERALS: peripheral list; must match respective submodule name so that all hardware and software of the peripheral is automatically included when compiling the system.

SIM_LIST: list of simulators to use in automatic testing. Simulators can be run remotely, in which case parameters SIM_SERVER and SIM_USER should be given.

SIM_SERVER: remote machine where the simulator runs.

SIM_USER: user name for SIM_SERVER.

SIMULATOR: default simulator. Leave SIM_SERVER and SIM_USER blank if simulator runs locally.

BOARD_LIST: list of boards to use in automatic testing. FPGA compilers, loaders and our "console" program can be run remotely, in which case parameters COMPILE_SERVER, COMPILE_USER, COMPILE_OBJ, BOARD_SERVER and BOARD_USER should be given.

LOCAL_BOARD_LIST: list of boards attached to the local machine.

LOCAL_COMPILER_LIST: list of FPGA compilers installed in the local machine.

COMPILE_SERVER: remote machine where the FPGA compiler is installed.

COMPILE_USER: user name for COMPILE_SERVER.

COMPILE_OBJ: name of the FPGA configuration file to build.

BOARD_SERVER: remote machine where the hardware board is attached.

COMPILE_USER: user name for BOARD_SERVER.

REMOTE_ROOT_DIR: directory in the remote machine to copy the current directory

ASIC_NODE: directory in the asic directory containing a compilation environment for the ASIC technology node

DOC_TYPE: directory in the document directory containing the Latex files producing the desired type of document

Simulation

To simulate:

make sim

To visualise simulation waveforms

make sim-waves

clean simulation files:

make sim-clean

FPGA

To compile the FPGA:

make fpga

To configure the FPGA:

make fpga-load

To clean FPGA files:

make fpga-clean

or to clean and delete 3rd party IP:

make fpga-clean-ip

Running the hardware

make run-hw

ASIC

To compile and ASIC:

make asic

To clean ASIC files:

make asic-clean

Software

To compile the firmware:

make  firmware

To compile the bootloader:

make bootloader

Documentation

To compile the chosen document type:

make document

To clean document files:

make clean-doc

Testing

To run a simulation and FPGA test:

make test

To run a simulation test only:

make test-sim

To run a FPGA test only:

make test-fpga

Cleaning

Besides the specific cleanup actions give so far, to clean software and documentation type

make clean

Instructions for Installing the RISC-V GNU Compiler Toolchain

Get sources

git clone https://github.com/riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain
git submodule update --init --recursive
git checkout <stable tag>
git submodule update --init --recursive

Prerequisites

For Ubuntu OS and its variants:

sudo apt install autoconf automake autotools-dev curl python3 python2 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev

To check your python version, use:

python --version

If this doesn't return Python 2.*, navigate to your /usr/bin folder and soft-link python2 to python using:

ln -s python2 /usr/bin/python

For CentOS and its variants:

sudo yum install autoconf automake python3 python2 libmpc-devel mpfr-devel gmp-devel gawk  bison flex texinfo patchutils gcc gcc-c++ zlib-devel expat-devel

Installation

sudo ./configure --prefix=/path/to/riscv --enable-multilib
sudo make
export PATH=$PATH:/path/to/riscv/bin

The export PATH command can be added to the bottom of your ~/.bashrc

Compilation

path/to/riscv/riscv64-unknown-elf-gcc -march=rv32im -mabi=ilp32 <C sources> -o <exec>
MIT License

Copyright (c) 2020 Jose T. de Sousa

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

Project Meta

  • Registered on LibreCores 1 month ago
  • Project started 1 year ago
  • Last commit 1 month ago

Commits

{"labels":[2019,2020],"series":[[581,407]]}

Commits per year

Contributors

{"labels":[2019,2020],"series":[[8,12]]}

Unique contributors per year

Releases

V0.1 is is the only release.

  • V0.1
    Jun 8, 2020 a39dcbb

Languages

{"labels":["Others","make","Verilog-SystemVerilog","Bourne Shell","Tcl\/Tk","Python","C","TeX","C\/C++ Header","Assembly"],"series":[1,25,11,7,6,4,3,2,2,2]}

Share of languages used

Data Sheet
https://github.com/IObundle/iob-soc
Last activity 1 month ago
V0.1 released 3 months ago
Primary language: make
988 commits by 16 contributors
Jose T. de Sousa João Vieira Rodrigues de Almeida Roque P_Miranda pedrompt97 Joao D Lopes
0,30,20,2,4,22,44,56,70,26,2,0,8,12,4,0,0,10,33,27,10,12,21,10,19,23,0,9,2,17,20,24,10,18,10,15,17,20,17,8,3,13,7,6,0,0,0,0,0,0

activity over the last year

LibreCores data updated 1 month ago