chacha by JoachimS
Verilog 2001 implementation of the ChaCha stream cipher.
The core is completed and has been implemented and used in several FPGA designs. The core is for example used as the CSPRNG/DRBG part of the random number generator (RNG) in the Cryptech HSM.
This core implements the ChaCha stream cipher (pdf) By Daniel J. Bernstein (DJB).
This core implements ChaCha with support for 128 and 256 bit keys. The number of rounds can be set from two to 32 rounds in steps of two. The default number of rounds is eight.
The core contains an internal 64-bit block counter that is automatically updated for each data block.
There is a reference model in a separate repository used to generate and document test vectors. There is also a functional model in this repo under src/model/python.
Branch for VHDL interoperability
There is a branch vhdl_interop that changes the port name "next" in chacha_core.v. Next is a reserved word in VHDL. If you are instantiating the core in a mixed language environment use this branch. This branch will not be merged into master, but will track changes to the master branch.
The core has four separate quarterround modules, which means that one round takes one cycle. The overhead latency cost when using the top level wrapper is three, which means that with eight rounds the total latency is 11 cycles. For ChaCha20 the latency is 23 cycles.
Implementation results using the Altera Quartus Prime 15.1 design tool.
Cyclone IV E
- 4748 LEs
- 1940 registers
- 55 MHz
Cyclone V GX
- 1939 ALMs for logic
- 1940 registers
- 60 MHz
Implementation results using Xilinx ISE 14.7.
- 3843 slice LUTs
- 1049 slices
- 1994 registers
- 83 MHz
- 3837 slice LUTs
- 1076 slices
- 1949 registers
- 100 MHz
Copyright (c) 2013, Joachim Strömbergson All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.