This implementation uses the AES block cipher with support for 128 and 256 bit keys. The ICV generated is 128 bit.
The core has been implemented and verified againt test vectors from IETF and NIST using testbench for testcases with zero, single and multiple block messages. Padding has been verified. The CMAC ICV generation works with 128 or 256 bit keys.
The Core has been implemented in hardware (Altera and Xilinx FPGAs).
The core accepts a key and a message divided into zero, one or more 128 bit blocks. After processing the core provides a result, the Integrity Check Vector (ICV) for the message. The ICV can be communicated to a recipient. By recalculating the ICV for the received message and comparing to the received ICV, the recipient can verify the message integrity and that it is from a sender that share the secret key with the recipient.
Performance wise, the cost of processing a message requires one initial AES operation (for internal subkey generation) and then one AES operation for each message block.
The core is used by first writing the key into the key registers and then asserting the init control signal. When the core signals ready the cmac has been initialized. Note that valid will be deasserted by the core, signalling that the ICV result is no longer valid.
The message can then be processed as a sequence of 128 bit blocks. For each block the next control signal shall be asserted. Note that ready signal must be set by the core for the core to accept new blocks.
Note that the core expects information about number of bits in the final message block [1..128]. The core performs padding and tweak based on this information. The final block and the lenght shall be written to the core and then the finalize signal shall be asserted. The core will process the final block and then raise ready and valid signalling that the ICV result is ready and valid.
Note that the core does not provide verification of a given ICV. The caller is expected to perform this comparison after generating the ICV for a received message.
Altera Cyclone V
- Device: 5CGXFC7C7F23C8
- Logic utilization (ALMs): 2285
- Registers: 3171
- Clock speed: 91 MHz
- Device: xc7a200t-3fbg484
- Slices: 2721
- Registers: 2996
- Clock speed: 91 MHz
- Device: xc6slx45-3fgg484
- Slices: 2385
- Registers: 3002
- Clock speed: 100 MHz
BSD 2-Clause License Copyright (c) 2016, Joachim Strömbergson All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.