sha512 by JoachimS

sha512

Verilog implementation of the SHA-512 hash function. This implementation complies with the functionality in NIST FIPS 180-4. The supports the SHA-512 variants SHA-512/224, SHA-512/256, SHA-384 and SHA-512.

Status

The core is completed and is considered mature. The core has been used in more than one FPGA design.

Implementation details

The core uses a sliding window with 16 64-bit registers for the W memory. The top level wrapper contains flag control registers for init and next that automatically resets. This means that the flags must be set for every block to be processed.

FPGA-results

Xilinx FPGAs

Implementation results using ISE 14.7.

Artix-7

  • xc7a200t-3fbg484
  • 4869 Slice LUTs
  • 1575 Slices
  • 3918 regs
  • 96 MHz

Spartan-6

  • xc6slx45-3csg324
  • 4333 LUTs
  • 1300 Slices
  • 3853 regs
  • 57 MHz

Altera FPGAs

Altera Cyclone V GX

  • 2923 ALMs
  • 3609 Registers
  • 80 MHz max clock frequency
Copyright (c) 2014, Joachim Strömbergson
All rights reserved.

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright notice, this
  list of conditions and the following disclaimer.

* Redistributions in binary form must reproduce the above copyright notice, this
  list of conditions and the following disclaimer in the documentation and/or
  other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Project Meta

  • Registered on LibreCores 2 years ago
  • Project started 6 years ago
  • Last commit 6 months ago

Commits

{"labels":[2014,2016,2018,2020,2015,2017,2019],"series":[[89,15,17,1,0,0,0]]}

Commits per year

Contributors

{"labels":[2014,2016,2018,2020,2015,2017,2019],"series":[[1,1,3,1,0,0,0]]}

Unique contributors per year

Releases

Data not available

Languages

{"labels":["Others","Verilog-SystemVerilog","Python","Markdown","make"],"series":[0,7,1,1,1]}

Share of languages used

Data Sheet
https://github.com/secworks/sha512
Last activity 6 months ago
Primary language: Verilog-SystemVerilog
122 commits by 4 contributors
Joachim Strömbergson Olof Kindgren Joachim Strömbergson Joachim Strömbergson
0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

activity over the last year

LibreCores data updated 30 days ago