sha512 by JoachimS

sha512

Verilog implementation of the SHA-512 hash function. This implementation complies with the functionality in NIST FIPS 180-4. The supports the SHA-512 variants SHA-512/224, SHA-512/256, SHA-384 and SHA-512.

Implementation details

The core uses a sliding window with 16 64-bit registers for the W memory. The top level wrapper contains flag control registers for init and next that automatically resets. This means that the flags must be set for every block to be processed.

FPGA-results

Xilinx FPGAs

Implementation results using ISE 14.7.

Artix-7

  • xc7a200t-3fbg484
  • 4869 Slice LUTs
  • 1575 Slices
  • 3918 regs
  • 96 MHz

Spartan-6

  • xc6slx45-3csg324
  • 4333 LUTs
  • 1300 Slices
  • 3853 regs
  • 57 MHz

Altera FPGAs

Altera Cyclone V GX

  • 2923 ALMs
  • 3609 Registers
  • 80 MHz max clock frequency

Status

(2016-08-10)

Added results for Xilinx Artix-7.

(2014-11-07)

Added results for Xilinx Spartan-6.

(2014-04-05)

RTL for the core and top is completed Testbenches for core and top completed. All single block and dual block test cases works. Results after building the complete design for Altera Cyclone V GX:

  • 2919 ALMs
  • 3609 Registers
  • 77 MHz max clock frequency

(2014-03-24)

Core works for the SHA-512 mode case. Added top level wrapper and built the design for Altera Cyclone V GX:

  • 2923 ALMs
  • 3609 Registers
  • 80 MHz max clock frequency

(2014-02-23)

Initial version. Based on the SHA-256 core. Nothing really to see yet.

Copyright (c) 2014, Joachim Strömbergson
All rights reserved.

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright notice, this
  list of conditions and the following disclaimer.

* Redistributions in binary form must reproduce the above copyright notice, this
  list of conditions and the following disclaimer in the documentation and/or
  other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Project Meta

  • Registered 11 months ago
  • Started 4 years ago
  • Last commit 2 years ago

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{"labels":[2014,2016,2015,2017,2018],"series":[["89","15",null,null,null]]}

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{"labels":[2014,2016,2015,2017,2018],"series":[["1","1",null,null,null]]}

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{"labels":["Others","Verilog-SystemVerilog","Python","Markdown","make"],"series":[0,7,1,1,1]}

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Data Sheet
https://github.com/secworks/sha512
Last updated 2 years ago
Language: Verilog-SystemVerilog
104 commits by 1 contributor
Joachim Strömbergson

Activity in last 1 year

Updated 11 months ago