spi2wb
Drive a Wishbone master bus with an SPI bus.
Protocol
The SPI configuration is following :
- CPOL = 0
- CPHA = 1
- CS = active low
An spi2wb frame is composed as following :
8 bits mode
- Write frame:
MOSI : 1AAAAAAA DDDDDDDD
MISO : ZZZZZZZZ ZZZZZZZZ
- Read frame
MOSI : 0AAAAAAA ZZZZZZZZ
MISO : ZZZZZZZZ DDDDDDDD
And with following :
- 1/0: write/read bit
- AAAAAAA: 7 bits address
- DDDDDDD: 8 bits data
- ZZZZZZZ: Don't care signal
16 bits mode
- Write frame:
MOSI : 1AAAAAAA DDDDDDDDDDDDDDDD
MISO : ZZZZZZZZ ZZZZZZZZZZZZZZZZ
- Read frame
MOSI : 0AAAAAAA ZZZZZZZZZZZZZZZZ
MISO : ZZZZZZZZ DDDDDDDDDDDDDDDD
And with following :
- 1/0: write/read bit
- AAAAAAA: 7 bits address
- DDDDDDDDDDDDDD: 16 bits data
- ZZZZZZZZZZZZZZ: Don't care signal
Install instructions
This component use Chisel3 as HDL and Cocotb for testbench framework. There is a hack with cocotbify that require a git submodule. Then to clone it don't forget the recursive option :
$ git clone --recurse-submodules https://github.com/Martoni/spi2wb.git
Simulation instructions
iotesters
A minimal code has been written in src/test/scala to test the component in scala. To launch it simply use make:
$ make test
But the actual testbench is written with Python Cocotb module.
Cocotb
To simulate the module go to cocotb/ directory:
- For 8 bits datasize do:
$ cd cocotb
$ DATAZISE=8 make
- For 16 bits datasize do:
$ cd cocotb
$ DATAZISE=16 make
To see waveform use gtkwave with following command :
$ gtkwave TopSpi2Wb.vcd
Test hardware
Generate verilog
To generate verilog synthesizable component do :
$ make
This will generate a verilog top components named TopSpi2Wb.v
. This component include a blinker to unsure that the bitstream is well downloaded and fpga started.
Testing with busPirate
The design has been tested with a busPirate. A python script is available in hwtest/ directory to test the component with buspirate :
- For 8 bits read/write:
$ python3 test_bus_pirate.py -d8
Write byte 0xCA @ 0x02
Write byte 0xFE @ 0x10
Write byte 0x55 @ 0x00
Write byte 0x12 @ 0xFF
Read byte 0xCA @ 0x02
Read byte 0xFE @ 0x10
Read byte 0x55 @ 0x00
Read byte 0x12 @ 0xFF
- For 16 bits read/write:
$ python3 test_bus_pirate.py -d16
Write byte 0xCAFE @ 0x02
Write byte 0x5958 @ 0x01
Write byte 0x5599 @ 0x00
Write byte 0xBAAF @ 0x10
Write byte 0x1234 @ 0x12
Read byte 0xCAFE @ 0x02
Read byte 0x5958 @ 0x01
Read byte 0x5599 @ 0x00
Read byte 0xBAAF @ 0x10
Read byte 0x1234 @ 0x12
https://github.com/Martoni/spi2wb.git
Issue Tracker
Last activity 1 year ago
v1.3 released 1 year ago
Primary language: Scala
1 open pull request
1 fork
2 watchers
4 stars
39 commits by 2 contributors
activity over the last year
LibreCores data updated 4 months ago