WbMdio by Martoni

Drive MDIO phy interface with a Chisel component

MDIO

Drive MDIO phy interface with a Chisel component. Test it with ksz8081rnb phy.

Wishbone interface

Wishbone slave is a simple 16bits data interface with 4 registers.

16bits addr register name
0x0 status
0x1 control
0x2 readData
0x3 writeData

status

bit 15 .. 1 0
name void busy

with:

  • busy: set if frame is sent

control

bit 15 ... 7..5 4..0
name R void aphy areg

with:

  • R: read bit, must be set to emit read frame
  • aphy: phy address number
  • areg: register number

readData

bit 15 .. 0
name readData

writeData

bit 15 .. 0
name writeData

Typical use

Send write data frame

To send data frame on the mdio bus follow this step :

  • monitor the busy bit in status register, if the bit is low go to following step.
  • Write phy address and reg address in control register
  • Write data in writeData register. The wishbone write will trigger the data mdio write frame.
  • monitor the busy bit, once busy bit is low, write data frame has been sent.

Send read data frame

  • monitor the busy bit in status register, if the bit is low go to following step.
  • Write phy address, reg address and read bit 'R'. Writing the 'R' bit will trigger the read mdio frame
  • monitor the busy bit, once busy bit is low, read data frame is terminated.
  • read readData register to get the data read.

tests

To launch test use the makefile with commands:

$ make testall

Project Meta

  • Registered 14 days ago
  • Started 29 days ago
  • Last commit 14 days ago

Commits

{"labels":[2019],"series":[[21]]}

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Contributors

{"labels":[2019],"series":[[2]]}

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Releases

1.0-rc1 is is the only release.

  • 1.0-rc1
    Oct 1, 2019 d44cae5 prerelease

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{"labels":["Others","Scala","Markdown","make"],"series":[0,4,2,1]}

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Data Sheet
Project Web Site
https://github.com/Martoni/MDIO.git
Issue Tracker
Last updated 14 days ago
1.0-rc1 released 16 days ago
Language: Scala
21 commits by 2 contributors
Fabien Marteau Martoni
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Updated 14 days ago