Steel Core by Rafael Calçada

3-stage single-issue RISC-V softcore (RV32IZicsr)

Key features:

  • RV32IZicsr implementation
  • Small and easy to use
  • 3 pipeline stages
  • Single-issue
  • M-mode support
  • Targeted for use in FPGAs
  • Full documentation
  • Passed all RV32IZicsr tests from RISC-V test and compliance suites
  • 0.46 CoreMarks / MHz

Licence

Steel is distributed under the MIT License. See the LICENCE.md file.

Documentation

Steel documentation (https://rafaelcalcada.github.io/steel-core/) provides information on:

  • Steel configuration
  • Integration with other devices
  • Implemented extensions and CSRs
  • Supported exceptions and interrupts
  • Trap handling
  • Implementation details
  • Timing diagrams for instruction fetch, data fetch, data writing and interrupt request processes
  • Input and output signals

Using Steel in your project

To use Steel in your project you must import all files from rtl directory to it. Then instantiate Steel using the following template:

steel_top #(

    .BOOT_ADDRESS()     // You must provide a 32-bit value. If omitted the core will use
                        // its default value, 32'h00000000.
    ) core (
    
    // Optional inputs must be hardwired to zero if not used.
    
    .CLK(),             // Clock source (required, input, 1-bit)
    .RESET(),           // Reset (required, input, synchronous, active high, 1-bit)
    .REAL_TIME(),       // Value read from a real time counter (optional, input, 64-bit)
    .I_ADDR(),          // Instruction address (output, 32-bit)
    .INSTR(),           // Instruction data (required, input, 32-bit)
    .D_ADDR(),          // Data address (output, 32-bit)
    .DATA_OUT(),        // Data to be written (output, 32-bit)
    .WR_REQ(),          // Write enable (output, 1-bit)
    .WR_MASK(),         // Write mask (output, 4-bit). Also known as "write strobe"
    .DATA_IN(),         // Data read from memory (required, input, 32-bit)
    .E_IRQ(),           // External interrupt request (optional, active-high, input, 1-bit)
    .T_IRQ(),           // Timer interrupt request (optional, active-high, input, 1-bit)
    .S_IRQ()            // Software interrupt request (optional, active-high, input, 1-bit)
    
);

Steel must be connected to a word-addressed memory with 1 clock cycle read/write latency, which means that the memory should take 1 clock cycle to complete both read and write operations. The signals used to fetch instructions and to read/write data were designed to facilitate the integration with FPGA Block RAMs and memory arrays. Read the documentation to learn how integrate the core to these devices.

Running the project in Vivado

The vivado directory has a project created in Vivado for an Artix-7 FPGA. To run it, simply open it in Vivado. To run it on another device, change the project settings.

About the author

The author is a computer engineering student at UFRGS (graduates at the end of 2020) and developed Steel Core for his undergraduate thesis.

Contact: rafaelcalcada@gmail.com / rafaelcalcada@hotmail.com

Acknowledgements

My colleague Francisco Knebel deserves special thanks for his collaboration with this work.

MIT License

Copyright (c) 2020 Rafael de Oliveira Calçada

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

Project Meta

  • Registered on LibreCores 1 month ago
  • Project started 4 months ago
  • Last commit 1 month ago

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