RV12 RISC-V Processor by RoaLogic

The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market.

Product Brief

The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of the Roa Logic’s 32/64bit CPU family based on the industry standard RISC-V instruction set

The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses. It features an optimizing 6-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.

Optional features include Branch Prediction, Instruction Cache, Data Cache, and Debug Unit. Parameterised and configurable features include the instruction and data interfaces, the branch-prediction-unit configuration, and the cache size, associativity, and replacement algorithms. Providing the user with trade offs between performance, power, and area to optimize the core for the application

RV12 RISC-V Architecture

Documentation

Features

  • Royalty Free Industry standard instruction set (www.riscv.org)
  • Parameterized 32/64bit data
  • Fast, precise interrupts
  • Custom instructions enable integration of proprietary hardware accelerators
  • Single cycle execution
  • Optimizing folded 6-stage pipeline
  • Memory Protection Support
  • Optional/Parameterized branch-prediction-unit
  • Optional/Parameterized caches

Compatibility

The RV12 is compatible with the following RISC-V Foundation specifications:

Interfaces

  • AHB3 Lite

Parameters

The following parameters control the feature set of a specific implementation of the RV12:

Parameter Type Default Description
JEDEC_BANK Integer 0x0A JEDEC Bank
JEDEC_MANUFACTURER_ID Integer 0x6E JEDEC Manufacturer ID
XLEN Integer 32 Datapath width
PLEN Integer XLEN Physical Memory Address Size
PMP_CNT Integer 16 Number of Physical Memory Protection Entries
PMA_CNT Integer 16 Number of Physical Menory Attribute Entries
HAS_USER Integer 0 User Mode Enable
HAS_SUPER Integer 0 Supervisor Mode Enable
HAS_HYPER Integer 0 Hypervisor Mode Enable
HAS_RVM Integer 0 “M” Extension Enable
HAS_RVA Integer 0 “A” Extension Enable
HAS_RVC Integer 0 “C” Extension Enable
HAS_BPU Integer 1 Branch Prediction Unit Control Enable
IS_RV32E Integer 0 RV32E Base Integer Instruction Set Enable
MULT_LATENCY Integer 0 Hardware Multiplier Latency (if “M” Extension enabled)
ICACHE_SIZE Integer 16 Instruction Cache size in Kbytes
ICACHE_BLOCK_SIZE Integer 32 Instruction Cache block length in bytes
ICACHE_WAYS Integer 2 Instruction Cache associativity
ICACHE_REPLACE_ALG Integer 0 Instruction Cache replacement algorithm 0: Random 1: FIFO 2: LRU
DCACHE_SIZE Integer 16 Data Cache size in Kbytes
DCACHE_BLOCK_SIZE Integer 32 Data Cache block length in bytes
DCACHE_WAYS Integer 2 Data Cache associativity
DCACHE_REPLACE_ALG Integer 0 Data Cache replacement algorithm 0: Random 1: FIFO 2: LRU
HARTID Integer 0 Hart Identifier
PC_INIT Address h200 Program Counter Initialisation Vector
MNMIVEC_DEFAULT Address PC_INIT-‘h004 Machine Mode Non-Maskable Interrupt vector address
MTVEC_DEFAULT Address PC_INIT-‘h040 Machine Mode Interrupt vector address
HTVEC_DEFAULT Address PC_INIT-‘h080 Hypervisor Mode Interrupt vector address
STVEC_DEFAULT Address PC_INIT-‘h0C0 Supervisor Mode Interrupt vector address
UTVEC_DEFAULT Address PC_INIT-‘h100 User Mode Interrupt vector address
BP_LOCAL_BITS Integer 10 Number of local predictor bits
BP_GLOBAL_BITS Integer 2 Number of global predictor bits
BREAKPOINTS Integer 3 Number of hardware breakpoints
TECHNOLOGY String GENERIC Target Silicon Technology

License

Released under the RoaLogic Non-Commercial License

Dependencies

Requires the Roa Logic Memories IPs and AHB3Lite Package. These are included as submodules.

After cloning the RV12 git repository, perform a git submodule init to download the submodules.


title: Non-Commercial License Agreement

Non-Commercial License Agreement

PLEASE CAREFULLY REVIEW THE FOLLOWING TERMS AND CONDITIONS BEFORE DOWNLOADING AND USING THE LICENSED MATERIALS. THIS LICENSE AGREEMENT (“AGREEMENT”) IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A SINGLE INDIVIDUAL, OR A SINGLE LEGAL ENTITY)(“YOU”) AND ROA LOGIC BV (“ROA LOGIC”) COVERING THE PRODUCTS OR SERVICES YOU PURCHASE FROM ROA LOGIC.

By downloading and/or using or installing products from Roa Logic you automatically agree to and are bound by the terms and conditions of this agreement.

PLEASE NOTE THAT THIS AGREEMENT IS INTENDED FOR NON-COMMERCIAL USE OF THE PRODUCT. IF YOU INTENT TO USE ROA LOGIC PRODUCTS FOR COMMERCIAL PURPOSES, THEN PLEASE CONTACT info@roalogic.com TO ARRANGE AN AGREEMENT WITH US BASED ON OUR COMMERCIAL LICENSE TERMS

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“Physical Implementation” means any implementation in programmable or non-programmable technologies including, but not limited to Field Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices (CPLDs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs)

“Silicon Device(s)” means any customer Physical Implementation containing a unique part number.

“You” the opposite contract party as referred to in article 6:231, subsection c, of the Dutch Civil Code, being the party to whom an offer is made by Roa Logic, or with whom an agreement is concluded by Roa Logic, or to whom the Product is supplied.

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  1. Copyright license
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  1. Use the Product in your design to create, simulate, implement, manufacture, and use a Silicon Device provided you don’t do so to make a profit
  2. Distribute the Product, provided the original disclaimer and copyright notice are retained and this Agreement is part of the distribution.

Specifically you are allowed to:

  1. Use the Product in your design to create, simulate, implement, manufacture, and use a Silicon Device provided you don’t do so to make a profit
  2. Distribute the Product, provided the original disclaimer and copyright notice are retained and this Agreement is part of the distribution.

3. OWNERSHIP

The Product, its documentation, and any associated material is owned by Roa Logic and is protected by copyright and other intellectual property right laws.

Any modification or addition to the Product, documentation, and any associated materials or derivatives thereof, that You intentionally submit to Roa Logic for inclusion in the Product will become part of the Product and thus owned and copyrighted by Roa Logic.

By submitting any material for inclusion you wave any ownership, copyright, and patent rights and claims for the use of the submitted material in the Product. “Submitting” means any form of electronic, verbal, or written communication sent to Roa Logic or its representatives, including, but not limited to, email, mailing lists, source repositories, and issue tracking systems for the purpose of discussing and improving the Product.

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5. DISCLAIMER OF WARRANTY

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7. EXPORT RESTRICTIONS

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  1. exported directly, or indirectly, in violation of export laws;
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8. APPLICABLE LAW AND CHOICE OF FORUM

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Conversion: If any clause or sentence of this agreement is held by a court of law to be illegal or unenforceable, the remaining provisions of the agreement remain in effect. The failure of Roa Logic to enforce any of the provisions in the agreement does not constitute a waiver of Roa Logic’s rights to enforce any provision of the agreement in the future.

Project Meta

  • Registered 1 year ago
  • Started 2 years ago
  • Last commit 1 year ago

Commits

{"labels":[2017,2018,2019],"series":[["15",null,null]]}

Commits per year

Contributors

{"labels":[2017,2018,2019],"series":[["1",null,null]]}

Unique contributors per year

Releases

v1.3 is is the latest of 7 releases.

  • v1.3
    Sep 11, 2018 f901b14
  • v1.3-rc2
    May 2, 2018 e4ad82f prerelease
  • v1.3-rc1
    Feb 5, 2018 b53c8e1 prerelease
  • v1.2
    Nov 24, 2017 3370095
  • v1.1
    Nov 1, 2017 07e662e
  • v1.1-rc2
    Nov 1, 2017 a243961 prerelease
  • v1.1-rc1
    Nov 1, 2017 d21c913 prerelease

Languages

{"labels":["Others","Verilog-SystemVerilog","make"],"series":[1,32,2]}

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Data Sheet
https://github.com/RoaLogic/RV12
Non-Commercial
Last updated 1 year ago
v1.3 released 7 months ago
Language: Verilog-SystemVerilog
15 commits by 1 contributor
rherveille

Activity in last 1 year

Updated 3 months ago