RV12 RISC-V Processor by RoaLogic
RISC-V CPU Core
- User Mode Specifications 2.1
- Privilege Mode Specifications 1.9.1
- Single issue, single thread
- RV32I or RV64I core (parameterized)
- Optional Multiplier and Divider Units (RVM extensions)
- Optional Branch Predict Unit
- Optional Instruction Cache
- Optional Data Cache
Released under the RoaLogic Non-Commerical license.
The release contains regression tests for the supported modules, based on the official riscv-tests.
Requires the RoaLogic Memories IPs and AHB3Lite Package. These are included as submodules. After cloning the RV12 git repository do a 'git submodule init' to download the submodules.
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