Open Source VHDL Group

Website / Wiki => http://www.vhdl.net/
Gitter => https://gitter.im/vhdl/Lobby
ReadTheDocs => https://vhdl-corelib.readthedocs.io
Travis-CI => https://travis-ci.org/VHDL/CoreLib

Project Meta

Registered on LibreCores 3 years ago
Project started 4 years ago
Last commit 4 years ago

Commits

{"labels":[2016,2017,2018,2019,2020,2021],"series":[[5,0,0,0,0,0]]}

Commits per year

Contributors

{"labels":[2016,2017,2018,2019,2020,2021],"series":[[1,0,0,0,0,0]]}

Unique contributors per year

Releases

Data not available

Languages

{"labels":["Others","Markdown"],"series":[0,1]}

Share of languages used

Data Sheet

https://github.com/VHDL/CoreLib
Last activity 4 years ago
Primary language: Markdown
2 open issues
3 forks
13 watchers
8 stars
5 commits by 1 contributor

activity over the last year

LibreCores data updated 7 months ago