dblclockfft by ZipCPU

A C++ generator of Verilog FFT cores that produce and consume two samples per clock

A Generic Piplined FFT Core Generator

This generic pipelined FFT project contains all of the software necessary to create the IP to generate an arbitrary sized FFT. The FFT has been modified for operation in one of the following modes:

  • Two samples in per clock and, after some delay, two samples out per clock. This uses 6 multiplies per FFT stage in the butterflies. This was the purpose of the original dblclkfft. (Why double clock? I don't know. Double-sample FFT might've been a better name.)

  • One sample in per clock, with the i_ce line being high for every incoming sample--up to one sample per clock. There's also options to run with at least one clock between samples, or even two clocks between samples (or more). This mode uses 3, 2, or 1 multiplies per FFT stage respectively.

  • Eventually, I want to support a real FFT mode which will accept real samples input, and alternately produce real and imaginary samples output--or the converse for the inverse FFT.

The FFT generated by this project is very configurable. By simple adjustment of a command line parameter, the FFT created will either be a forward FFT or an inverse FFT. The number of bits processed, kept, and maintained by this FFT are also configurable. Even the number of bits used for the twiddle factors, or whether or not to bit reverse the outputs, are all configurable parts to this FFT core.

These features make this open source pipelined FFT module very different and unique among the other open HDL cores you may find.

For those who wish to get started right away, please download the package, change into the sw directory and run make. There is no need to run a configure script, fftgen is completely portable C++. Then, once built, go ahead and run fftgen without any arguments. This will cause fftgen to print a usage statement to the screen. Review the usage statement, and run fftgen a second time with the arguments you need.

Current State

This particular version of the FFT core now passes all my tests. It has yet to meet hardware to be finally verified.

  • The FFT test bench doesn't yet have a threshold that adjusts with input parameters to determine success or failure (yet).

  • I haven't started on the real-only version of this FFT.

While my previously stated goal ws to continue working with this core until it has a real-FFT capability before releasing it back into the master branch, I'm actually so excited that I got it to this point that I'm going to move it from dev to master earlier, and come back to get the real only version.

Commercial Applications

Should you find the LGPLv3 license insufficient for your needs, other licenses can be purchased from Gisselquist Technology, LLC.

Likewise, please contact us should you wish to fund the further development of this core.

Project Meta

  • Registered on LibreCores 5 years ago
  • Project started 5 years ago
  • Last commit 2 years ago



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Last activity 2 years ago
Primary language: C++
1 star
92 commits by 3 contributors
ZipCPU Me C-Elegans

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LibreCores data updated 1 year ago