wb2axip by ZipCPU

A pipelined wishbone to AXI bridge
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WB2AXIP: A Pipelind Wishbone B4 to AXI4 bridge

Built out of necessity, this core is designed to provide a conversion from a wishbone bus to an AXI bus. Primarily, the core is designed to connect a wishbone bus, either 32- or 128-bits wide, to a 128-bit wide AXI bus, which is the natural width of a DDR3 transaction (with 16-bit lanes). Hence, if the Memory Interface Generator DDR3 controller is running at a 4:1 clock rate, memory clocks to AXI system clocks, then it should be possible to accomplish one transaction clock at a sustained or pipelined rate. This bus translator is designed to be able to handle one transaction per clock (pipelined), although (due to Xilinx's MIG design) the delay may be up to 27 clocks. (Ouch!)

Since the initial build of the core, I've added the WB to AXI lite bridge. This is also a pipelined bridge, and like the original one it is also formally verified.

AXI to Wishbone conversion

As of 20181228, the project now contains an AXI4 lite read channel to wishbone interface, and also an AXI4 lite write channel to wishbone interface.
A third core, the AXI-lite to WB core combines these two together using a Wishbone arbiter. All four of these designs have been formally verified, and should be reliable to use.

As of 20190101, this AXI-lite to WB bridge has been FPGA proven.

The full AXI4 protocol, however, is rather complicated--especially when compared to WB. As a result, while there is a full-fledged AXI4 to Wishbone bridge within this project, this bridge is still not ready for prime time. It is designed to synchronize the write channels, turning AXI read/write requests into pipeline wishbone requests, maintaining the AXI ID fields, handle burst transactions, etc. As designed, it ignores the AXI xSIZE, xLOCK, xCACHE, xPROT, and xQOS fields, while supporting xBURST types of FIXED (2'b00) and INCR (2'b01) but not WRAP (2'b10) or reserved (2'b11). The design supports bridging between busses of different widths. The only problem is ... this full AXI4 to WB converter doesn't work (yet). I know this because it doesn't yet pass formal verification.

Formal Verification

Currently, the project contains formal specifications for Avalon, Wishbone, and AXI busses.

Commercial Applications

Should you find the GPLv3 license insufficient for your needs, other licenses can be purchased from Gisselquist Technology, LLc.

Thanks

I'd like to thank @wallento for his initial work on a Wishbone to AXI converter, and his encouragement to improve upon it. While this isn't a fork of his work, the pipelined wishbone to AXI bridge took its initial motivation from his work.

Project Meta

  • Registered 2 years ago
  • Started 2 years ago
  • Last commit 2 years ago

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{"labels":[2016,2017,2018,2019],"series":[["9",null,null,null]]}

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https://github.com/ZipCPU/wb2axip
GPLv3
Last updated 2 years ago
Language: Verilog-SystemVerilog
1 watcher
3 stars
9 commits by 2 contributors
Me Dan Gisselquist

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Updated 5 months ago