wbicapetwo by ZipCPU

Wishbone to ICAPE interface bridge
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Wishbone to ICAPE2 interface conversion

This core maps the configuration registers of a 7-series (or Spartan--6) Xilinx part onto register addresses on a wishbone bus interface via the ICAPE2 access port to those parts. The big thing this captures is the timing and handshaking required to read and write registers from the configuration interface.

As an example of what can be done, writing a 32'h00f to local address 5'h4 sends the IPROG command to the FPGA, causing it to immediately reconfigure itself.

As another example, the warm boot start address is located in register 5'h10. Writing to this address, followed by issuing the IPROG command just mentioned will cause the FPGA to configure from that warm boot start address.

For more details on the configuration interface, the registers in question, their meanings and what they do, please see the respective User's Guide.

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  • Registered 2 years ago
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  • Last commit 2 years ago

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https://github.com/ZipCPU/wbicapetwo
GPLv3
Last updated 1 year ago
Language: Verilog-SystemVerilog
1 star
2 commits by 1 contributor
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Updated 1 year ago