wbscope by ZipCPU

A wishbone controlled scope for FPGAs
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A Wishbone Controlled Scope for FPGA's

This is a generic/library routine for providing a bus accessed 'scope' or (perhaps more appropriately) a bus accessed logic analyzer for use internal to an FPGA. The general operation is such that this 'scope' can record and report on any 32 bit value transiting through the FPGA that you have connected to the scope. Once started and reset, the scope records a copy of the input data every time the clock ticks with the circuit enabled. That is, it records these values up until the trigger. Once the trigger goes high, the scope will record for bw_holdoff more counts before stopping. Values may then be read from the buffer, oldest to most recent. After reading, the scope may then be reset for another run.

In general, therefore, operation happens in this fashion:

  1. A reset is issued.
  2. Recording starts, in a circular buffer, and continues until
  3. The trigger line is asserted. The scope registers the asserted trigger by setting the o_triggered output flag.
  4. A counter then ticks until the last value is written. The scope registers that it has stopped recording by setting the o_stopped output flag.
  5. The scope recording is then paused until the next reset.
  6. While stopped, the CPU can read the data from the scope

    • oldest to most recent
    • one value per bus clock
  7. Writes to the data register reset the address to the beginning of the buffer


The Wishbone scope was featured on zipcpu.com as a conclusion to the discussion of the example debugging bus. That example discussed how to hook up the scope to your logic, as well as how to employ the scope software to create a VCD file that could then be viewed in GTKWave. The scope was also mentioned as a means of capturing traces of button bounces, with the short discussion of how to set it up for that task here.

Commercial Applications

Should you find the GPLv3 license insufficient for your needs, other licenses can be purchased from Gisselquist Technology, LLC.

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  • Registered 2 years ago
  • Started 2 years ago
  • Last commit 1 year ago



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Last updated 1 year ago
Language: Verilog-SystemVerilog
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Updated 1 year ago