zipcpu by ZipCPU
The Zip CPU
The Zip CPU is a small, light-weight, RISC CPU. Specific design goals include:
- 32-bit. All registers, addresses, and instructions are 32-bits in length. While the byte-size itself was at one time 32-bits, the CPU now handles 8-bit bytes like all other CPUs
- A RISC CPU. Instructions nominally complete in one cycle each, with exceptions for multiplies, divides, memory accesses, and (eventually) floating point instructions.
- A load/store architecture. Only load and store instructions may access memory.
- Wishbone compliant. All memory and peripherals are accessed across a single wishbone bus.
- A Von-Neumann architecture, meaning that both instructions and data share a common bus.
- A pipelined architecture, having stages for prefetch, decode, read-operand(s), a combined stage containing the ALU, memory, divide, and floating point units, and then the final write-back stage.
- A two mode machine: supervisor and user, with each mode having a different access level.
- Completely open source, licensed under the GPL.
Unique features and characteristics
- Only 29 instructions are currently implemented. Six additional instructions have been reserved for a floating point unit, but such a unit has yet to be implemented.
- (Almost) all instructions can be executed conditionally. Exceptions include load immediate, the debug break instruction, the bus lock and simulation instructions, and the no-operation instruction. The assembler will quietly turn a conditional load immediate into a two-instruction equivalent.
- Simplfied wishbone bus. While the ZipCPU conforms to the Wishbone B4 standard, some simplifications have been made. All tgx lines have been removed, although the select lines have been kept. All accesses are (or can be) pipelined. Finally, the ZipCPU project (and its daughter projects/peripherals) assumes that the strobe line is zero whenever the cycle is zero. This simplifies peripheral processing.
- The CPU makes heavy use of pipelined wishbone processing wherever and whenever it can. Hence, loading two vaues in a row may cost only one clock more than just loading the one value.
- The CPU has no interrupt vectors, but rather two register sets. On any interrupt, the CPU just switches from the user register set to the supervisor register set. This simplifies interrupt handling, since the CPU automatically saves, preserves, and restores the supervisor's context between enabling interrupts and receiving the next interrupt. An interrupt peripheral handles the combining of multiple interrupts into a single interrupt line.
If you'd like to get started with the ZipCPU, you might wish to know that this repository contains the CPU, its documentation, and the toolchain. The CPU implementation found here, though, is just that: a CPU. This implementation requires a bus with peripherals hanging off of it, things such as RAM, flash (ROM), serial port, etc. This is just where I keep the CPU apart from any necessary peripherals.
So, if you want to try out the CPU, feel free to download and build this
git-clone with a depth of 1--there's a lot of stuff in the
git repo that you don't necessarily need). You'll need it for the binutils,
GCC, and newlib support provided by it.
Once you've built these tools, then I'd suggest you look into the ZBasic repository. That repository places the CPU in an environment with block RAM, QSPI flash, and SD-card (SPI protocol) access. From that repository, you can either tweak the distro (main.v, regdefs.h, board.h, board.ld) to add the peripherals you want to use the CPU with, or you can use autofpga to adjust your RAM size, add or remove peripherals and so forth while maintaining (creating, really) all of these files for you.
Even more than that, the ZBasic distribution has complete Verilator support so that you can build your design, and simulate it, from power on reset through bootloader through ... well, however far you'd like to simulate and your disk has space for.
If you aren't interested in simulating the CPU, there is an assembly level debugger that you can use to stop and step the CPU, as well as an integrated wishbone scope that you can use to get traces from within the design while it is running.
If you'd like to use the ZipCPU, and don't know where to begin, feel free to find me on IRC as ZipCPU. I tend to inhabit the #openarty channel of the Freenode IRC server. If you get stuck, I've been known to help folks out there as well.
I've recently blogged about the ZipCPU at zipcpu.com! Articles you might find valuable include:
- An overview of the ZipCPU's ISA
- How-to build the tool-chain, and test the CPU
- Formal properties of a WB bus
- Formally proving the prefetch
I'm also working on formally verifying the entire CPU. My goal will be to prove, via yosys-smtbmc, that the ZipCPU will never enter into an invalid state. I've been successful so far proving the various components of the ZipCPU. What remains is the CPU itself.
Not yet integrated
An MMU has been written for the ZipCPU, and even integrated into it, but it has not yet been tested. Using formal methods, I've now proved that this component works. A test bench also exists to exercise it.
A data cache has been written for the ZipCPU, but has yet to be fully optimized.
The ZipOS would greatly speed up and improve the bare bones newlib library--primarily by providing "O/S" level interrupt support when using the library. This integration has not (yet) been accomplished.
On the other hand, if the MMU is available, I might rather just create a Linux distribution.
If the GPLv3 license is insufficient for your needs, other licenses (for all but the tool-chain) can be purchased from Gisselquist Technology, LLC.