verilog-i2c by alexforencich
Verilog I2C interface
For more information and updates: http://alexforencich.com/wiki/en/verilog/i2c/start
GitHub repository: https://github.com/alexforencich/verilog-i2c
Introduction
I2C interface components. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.
Documentation
i2c_init module
Template module for peripheral initialization via I2C. For use when one or more peripheral devices (i.e. PLL chips, jitter attenuators, clock muxes, etc.) need to be initialized on power-up without the use of a general-purpose processor.
i2c_master module
I2C master module with AXI stream interfaces to control logic.
i2c_master_axil module
I2C master module with 32-bit AXI lite slave interface.
i2c_master_wbs_8 module
I2C master module with 8-bit Wishbone slave interface.
i2c_master_wbs_16 module
I2C master module with 16-bit Wishbone slave interface.
i2c_slave module
I2C slave module with AXI stream interfaces to control logic.
i2c_slave_axil_master module
I2C slave module with parametrizable AXI lite master interface.
i2c_slave_wbm module
I2C slave module with parametrizable Wishbone master interface.
Source Files
axis_fifo.v : AXI stream FIFO
i2c_init.v : Template I2C bus init state machine module
i2c_master.v : I2C master module
i2c_master_axil.v : I2C master module (32-bit AXI lite slave)
i2c_master_wbs_8.v : I2C master module (8-bit Wishbone slave)
i2c_master_wbs_16.v : I2C master module (16-bit Wishbone slave)
i2c_slave.v : I2C slave module
i2c_slave_axil_master.v : I2C slave module (parametrizable AXI lite master)
i2c_slave_wbm.v : I2C slave module (parametrizable Wishbone master)
Testing
Running the included testbenches requires MyHDL and Icarus Verilog. Make sure that myhdl.vpi is installed properly for cosimulation to work correctly. The testbenches can be run with a Python test runner like nose or py.test, or the individual test scripts can be run with python directly.
Testbench Files
tb/axil.py : MyHDL AXI4 lite master and memory BFM
tb/axis_ep.py : MyHDL AXI Stream endpoints
tb/i2c.py : MyHDL I2C master and slave models
tb/wb.py : MyHDL Wishbone master model and RAM model
Copyright (c) 2015-2017 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
https://github.com/alexforencich/verilog-i2c.git
MIT
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