svlint by dalance

SystemVerilog linter

svlint

SystemVerilog linter

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svlint

Installation

Download binary

Download from release page, and extract to the directory in PATH.

Cargo

You can install by cargo.

cargo install procs

Usage

Option

svlint 0.1.0

USAGE:
    svlint [FLAGS] [OPTIONS] <files>...

FLAGS:
        --example    Prints config example
    -h, --help       Prints help information
    -s, --silent     Suppresses message
    -1               Prints results by single line
    -V, --version    Prints version information
    -v, --verbose    Prints verbose message

OPTIONS:
    -c, --config <config>          Config file [default: .svlint.toml]
    -d, --define <defines>...      Define
    -f, --filelist <filelist>      File list
    -i, --include <includes>...    Include path

ARGS:
    <files>...    Source file

Rules

Name Description
enum_with_type enum must have data type
for_with_begin multiline 'for' statement must have 'begin'
function_with_automatic 'function' must be 'automatic'
generate_for_with_label 'generate for' must have label
generate_if_with_label 'generate if' must have label
generate_keyword 'generate'/'endgenerate' must be omitted
genvar_declaration genvar must be declared in loop
if_with_begin multiline 'if' statement must have 'begin'
inout_with_tri 'inout' must have 'tri'
input_with_var 'input' must have 'var'
legacy_always 'always_comb'/'always_ff'/'always_latch' must be used
loop_variable_declaration loop variable must be declared in loop
output_with_var 'output' must have 'var'
parameter_in_package 'parameter' must be replaced to 'localparam' in package
priority_keyword 'priority' is forbidden
tab_charactor tab charactor is forbidden
unique0_keyword 'unique0' is forbidden
unique_keyword 'unique' is forbidden
wire_reg 'wire'/'reg' must be replaced to 'logic'/'tri'

Configuration

Configuration file is searched to the upper directory until /. So you can put configuration file (.svlint.toml) on the repository root like .gitignore.

The example of configuration file is below:

[option]
exclude_paths = ["ip/.*"]

[rules]
inout_with_tri = false
input_with_var = false
output_with_var = false

The complete example can be generated by svlint --example

[option] section

exclude_paths is a list of regular expression. If a file path is matched with the list, the file is skipped to check.

[rules] section

By default, all rules are enabled. If you want to disable some rules, false can be specified.

MIT License

Copyright (c) 2019 

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

Project Meta

  • Registered 21 days ago
  • Started 30 days ago
  • Last commit 22 days ago

Commits

{"labels":[2019],"series":[[14]]}

Commits per year

Contributors

{"labels":[2019],"series":[[1]]}

Unique contributors per year

Releases

v0.1.0 is is the only release.

  • v0.1.0
    Oct 29, 2019 0a2dc52

Languages

{"labels":["Others","Verilog-SystemVerilog","Rust","YAML"],"series":[3,38,24,5]}

Share of languages used

Data Sheet
Project Web Site
https://github.com/dalance/svlint.git
Issue Tracker
Last updated 22 days ago
v0.1.0 released 22 days ago
Language: Verilog-SystemVerilog
14 commits by 1 contributor
dalance
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,10,0,0,0,0

Activity in last 1 year

Updated 21 days ago