MIPI CSI-2 Receiver by daveshah1

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

MIPI CSI-2 IP Cores

The vhdl_rx folder contains a tried-and-tested high performance CSI-2 receiver core in VHDL. This can handle 4k video at over 30fps (most likely 60fps with a suitable camera module). This has been tested with the OV13850 camera module with a Xilinx Kintex-7 FPGA. It is currently limited to a 4-lane and 10bpp without modification, other parameters such as timing can be modified at compile time. Also in this folder are an example project and some miscellaneous VHDL support IP such as an AXI-4 framebuffer controller.

The verilog_cores contains work-in-progress CSI-2 transmit and receive cores in Verilog. These are designed to be more flexible and run on a variety of platforms. The first target will be 640x480 video using a Raspberry Pi camera with an iCE40 FPGA.

All cores are licensed under the MIT License, see LICENSE for details.

MIT License

Copyright (c) 2016-2018 David Shah <dave@ds0.me>

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

Project Meta

  • Registered 11 months ago
  • Started 2 years ago
  • Last commit 1 year ago

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{"labels":[2016,2017,2018,2019],"series":[["4","2",null,null]]}

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https://github.com/daveshah1/CSI2Rx.git
MIT
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Last updated 1 month ago
Language: Verilog-SystemVerilog
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6 commits by 1 contributor
David Shah

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Updated 1 month ago