ri5cy by drossi

Build Status

OpenHW Group CORE-V CV32E40P RISC-V IP

CV32E40P is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements the RV32IM[F]C instruction set architecture, and the Xpulp custom extensions for achieving higher code density, performance, and energy efficiency [1], [2]. It started its life as a fork of the OR10N CPU core that is based on the OpenRISC ISA. Then, under the name of RI5CY, it became a RISC-V core (2016), and it has been maintained by the PULP platform team until February 2020, when it has been contributed to OpenHW Group.

Please be aware that a portion of the RTL that comprises the CV32E40P's floating-point unit is maintained in the PULP Platform FPNEW project. To download the fpnew repository, please type:

make deps

Documentation

The CV32E40P user manual can be found in this repository.

Verification

The verification environment for the CV32E40P is not in this Repository. There is a small, simple testbench here which is useful for experimentation only and should not be used to validate any changes to the RTL prior to pushing to the master branch of this repo.

The verification environment for this core as well as other cores in the OpenHW Group CORE-V family is at the core-v-verif repository on GitHub.

The Makefiles supported in the core-v-verif project automatically clone the appropriate version of the cv32e40p and fpnew RTL sources from their respective repositories.

Physical Design

Coming soon!

Contributing

We highly appreciate community contributions. We are currently using the lowRISC contribution guide. To ease our work of reviewing your contributions, please:

  • Create your own fork to commit your changes and then open a Pull Request.
  • Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
  • Write meaningful commit messages. For more information, please check out the the Ibex contribution guide.
  • If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.

When contributing SystemVerilog source code, please try to be consistent and adhere to the lowRISC Verilog coding style guide.

To get started, please check out the "Good First Issue" list.

Issues and Troubleshooting

If you find any problems or issues with CV32E40P or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.

References

  1. Gautschi, Michael, et al. "Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices." in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 10, pp. 2700-2713, Oct. 2017

  2. Schiavone, Pasquale Davide, et al. "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications." 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017)

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Project Meta

  • Registered on LibreCores 1 year ago
  • Project started 5 years ago
  • Last commit 1 month ago

Commits

{"labels":[2015,2016,2017,2018,2019,2020],"series":[[281,154,161,137,309,117]]}

Commits per year

Contributors

{"labels":[2015,2016,2017,2018,2019,2020],"series":[[4,15,16,25,19,15]]}

Unique contributors per year

Releases

marsellus_v1.1.0 is is the latest of 41 releases.

  • marsellus_v1.1.0
    Jan 30, 2020 eb2d483
  • marsellus_1.0.1
    Dec 23, 2019 9dd31b1
  • marsellus_1.0.0
    Dec 15, 2019 4e27cb0
  • pulpissimo-v3.4.0
    Nov 18, 2019 be1fdf5
  • vega_v1.3.4
    Oct 28, 2019 98e8152
  • vega_v1.3.3
    Sep 9, 2019 56f4bac
  • vega_v1.3.2
    Sep 4, 2019 4954549
  • pulpissimo-v3.3.1
    Aug 26, 2019 0e5c1e6
  • pulpissimo-v3.3.0
    Jul 5, 2019 1543a5d
  • pulpissimo-v3.2.0
    Jul 3, 2019 21ce7a7
  • pulpissimo-v3.1.0
    Jun 24, 2019 b24b102
  • vega_v1.3.1
    May 24, 2019 47d182b
  • pulpissimo-v3.0.0
    Apr 16, 2019 6cb61e8
  • vega_v1.3.0
    Apr 11, 2019 f8c342d
  • pulpissimo-v2.0.1
    Mar 20, 2019 19037e5
  • vega_v1.2.0
    Feb 21, 2019 bd7c324
  • vega_v1.1.3
    Jan 11, 2019 28bb51d
  • vega_v1.1.2
    Jan 7, 2019 d7d25e4
  • pulpissimo-v2.0.0
    Dec 20, 2018 e47d6ef
  • vega_v1.1.1
    Nov 26, 2018 cd0e43f
  • vega_v1.1.0
    Nov 25, 2018 303773e
  • vega_v1.0.10
    Nov 20, 2018 457c751
  • vega_v1.0.9
    Nov 17, 2018 4535bd1
  • vega_v1.0.8
    Nov 17, 2018 432cfbb
  • vega_v1.0.7
    Nov 6, 2018 24b0153
  • vega_v1.0.6
    Nov 4, 2018 91d41d3
  • vega_v1.0.5
    Nov 3, 2018 f2cae69
  • vega_v1.0.4
    Nov 2, 2018 607f222
  • vega_v1.0.3
    Oct 27, 2018 a6d28a5
  • vega_v1.0.2
    Oct 26, 2018 08863f1
  • vega_v1.0.1
    Oct 21, 2018 f46115d
  • v1.0.1
    Oct 1, 2018 6148cf5
  • vega_v1.0.0
    Sep 23, 2018 3bf4ad0
  • trace_debugger_dev_v1.0.0
    Sep 22, 2018 3d74b64
  • v1.0.0
    Sep 12, 2018 825bcd9
  • pulpissimo-v1.0.1
    Jun 19, 2018 b842d0c
  • pulpissimo-v1.0
    Jan 29, 2018 f0180d6
  • pulpissimo-v1.0.0
    Jan 22, 2018 12e1cda
  • pulpinov1.0.0
    Dec 4, 2017 6c928ad
  • pulpino-v1.0.0
    Dec 4, 2017 6c928ad
  • Pulpino_v2.1
    May 19, 2016 ccdf02e

Languages

{"labels":["Others","Assembly","Verilog-SystemVerilog","C"],"series":[169,279,63,15]}

Share of languages used

Data Sheet
https://github.com/pulp-platform/riscv.git
Last activity 1 month ago
marsellus_v1.1.0 released 5 months ago
Primary language: Assembly
1159 commits by 60 contributors
Andreas Traber bluew Sven Stucki Pasquale Davide Schiavone Pasquale Davide Schiavone
0,7,2,2,7,4,8,21,6,16,12,2,5,1,13,3,2,7,8,2,0,0,3,5,6,16,4,5,7,3,13,10,18,15,2,8,1,0,1,0,0,0,0,0,0,0,0

activity over the last year

LibreCores data updated 1 month ago