ri5cy by drossi

RI5CY: RISC-V Core

RI5CY is a small 4-stage RISC-V core. It started its life as a fork of the OR10N CPU core that is based on the OpenRISC ISA.

RI5CY fully implements the RV32IMC instruction set and many custom instruction set extensions that improve its performance for signal processing applications.

The core was developed as part of the PULP platform for energy-efficient computing and is currently used as the processing core for PULP and PULPino.

Documentation

A datasheet that explains the most important features of the core can be found in the doc folder.

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Project Meta

  • Registered 2 months ago
  • Started 3 years ago
  • Last commit 3 months ago

Commits

{"labels":[2015,2016,2017,2018],"series":[["281","154","161","45"]]}

Commits per year

Contributors

{"labels":[2015,2016,2017,2018],"series":[["4","15","16","14"]]}

Unique contributors per year

Releases

vega_v1.0.0 is is the latest of 9 releases.

  • vega_v1.0.0
    Sep 23, 2018 3bf4ad0
  • trace_debugger_dev_v1.0.0
    Sep 22, 2018 3d74b64
  • v1.0.0
    Sep 12, 2018 825bcd9
  • pulpissimo-v1.0.1
    Jun 19, 2018 b842d0c
  • pulpissimo-v1.0
    Jan 29, 2018 f0180d6
  • pulpissimo-v1.0.0
    Jan 22, 2018 12e1cda
  • pulpinov1.0.0
    Dec 4, 2017 6c928ad
  • pulpino-v1.0.0
    Dec 4, 2017 6c928ad
  • Pulpino_v2.1
    May 19, 2016 ccdf02e

Languages

{"labels":["Others","Verilog-SystemVerilog","YAML","Markdown","Bourne Shell"],"series":[3,40,3,2,2]}

Share of languages used

Data Sheet
https://github.com/pulp-platform/riscv.git
Last updated 3 months ago
vega_v1.0.0 released 2 months ago
Language: Verilog-SystemVerilog
641 commits by 34 contributors
Andreas Traber Sven Stucki Pasquale Davide Schiavone Gautschi Pasquale Davide Schiavone
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,4,0,0,2,1,1,0,1,2,2,2,0,1,0,0,0,2,0,4,0,1,1,0,2,1,5,10,6,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0

Activity in last 1 year

Updated 2 months ago