Fedar F1
Fedar F1 is a 5-Stage Pipelined (Fetch|Decode|Execute|Memory|Writeback) RV64IM RISC-V Core written fully in Verilog.
How to compile?
- Open a terminal in
testbench
folder. - Run:
run_tests.sh
.
- The script automatically compile and create files under the
testbench/output/
folder. - And will create
.vcd
files under thetestbench/vcd
folder.
- Done!
Compilation requires iverilog
verilog compiler.
You can install iverilog on Debian based distros (like Pardus GNU/Linux or Ubuntu) with this command:
sudo apt install iverilog
If you don't want to compile it again, precompiled
.vcd
files are available under thetestbench/vcd
.
How to open .vcd files?
- Use GTKWave.
You can install GTKWave on Debian based distros (like Pardus GNU/Linux or Ubuntu) with this command:
sudo apt install gtkwave
Then double click the files or open with terminal command: gtkwave file.vcd
.
MIT License Copyright (c) 2021 Emin Fedar Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Data Sheet
Project Web Site
https://github.com/eminfedar/fedar-f1-rv64im.git
MIT
Issue Tracker
Last activity 1 year ago
v1.0 released 1 year ago
Primary language: Verilog-SystemVerilog
4 forks
5 watchers
83 stars
23 commits by 1 contributor
https://github.com/eminfedar/fedar-f1-rv64im.git
MIT
Issue Tracker
Last activity 1 year ago
v1.0 released 1 year ago
Primary language: Verilog-SystemVerilog
4 forks
5 watchers
83 stars
23 commits by 1 contributor
activity over the last year
LibreCores data updated 1 year ago