Fedar F1 - RV64IM by eminfedar

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

Fedar F1

LibreCores

Fedar F1 is a 5-Stage Pipelined (Fetch|Decode|Execute|Memory|Writeback) RV64IM RISC-V Core written fully in Verilog.

Simulated GTKWave output of the CPU

How to compile?

  1. Open a terminal in testbench folder.
  2. Run: run_tests.sh.
  • The script automatically compile and create files under the testbench/output/ folder.
  • And will create .vcd files under the testbench/vcd folder.
  1. Done!

Compilation requires iverilog verilog compiler.

You can install iverilog on Debian based distros (like Pardus GNU/Linux or Ubuntu) with this command:

sudo apt install iverilog

If you don't want to compile it again, precompiled .vcd files are available under the testbench/vcd.

How to open .vcd files?

You can install GTKWave on Debian based distros (like Pardus GNU/Linux or Ubuntu) with this command:

sudo apt install gtkwave

Then double click the files or open with terminal command: gtkwave file.vcd.

MIT License

Copyright (c) 2021 Emin Fedar

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

Project Meta

  • Registered on LibreCores 7 months ago
  • Project started 8 months ago
  • Last commit 7 months ago

Commits

{"labels":[2021,2022],"series":[[23,0]]}

Commits per year

Contributors

{"labels":[2021,2022],"series":[[1,0]]}

Unique contributors per year

Releases

v1.0 is is the only release.

  • v1.0
    May 23, 2021 5fe431f

Languages

{"labels":["Others","Verilog-SystemVerilog","Coq","Bourne Shell","Markdown","Assembly"],"series":[0,12,2,2,1,1]}

Share of languages used

Data Sheet
Project Web Site
https://github.com/eminfedar/fedar-f1-rv64im.git
MIT
Issue Tracker
Last activity 7 months ago
v1.0 released 7 months ago
Primary language: Verilog-SystemVerilog
4 forks
5 watchers
83 stars
23 commits by 1 contributor
Emin Fedar
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,10,9,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

activity over the last year

LibreCores data updated 7 months ago