litedram by enjoy-digital
__ _ __ ___ ___ ___ __ ___ / / (_) /____ / _ \/ _ \/ _ | / |/ / / /__/ / __/ -_) // / , _/ __ |/ /|_/ / /____/_/\__/\__/____/_/|_/_/ |_/_/ /_/ Copyright 2015-2020 / EnjoyDigital A small footprint and configurable DRAM core powered by Migen & LiteX
LiteDRAM provides a small footprint and configurable DRAM core.
LiteDRAM is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
Using Migen to describe the HDL allows the core to be highly and easily configurable.
LiteDRAM can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core.
- Generic SDRAM PHY (vendor agnostic, tested on Xilinx, Altera, Lattice)
- Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
- Spartan7/Artix7/Kintex7/Virtex7 DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
- Kintex/Virtex Ultrascale (Plus) DDR3/DDR4 PHY (1:4 frequency ratio)
- ECP5 DDR3 PHY (1:2 frequency ratio)
- Fully pipelined, high performance.
- Configurable commands depth on bankmachines.
- Periodic refresh/ZQ short calibration (up to 8 postponed refreshes).
- Configurable crossbar (simply use crossbar.get_port() to add a new port!)
- Ports arbitration transparent to the user.
- Native, AXI-MM or Wishbone user interface.
- DMA reader/writer.
- ECC (Error-correcting code)
[> FPGA Proven
LiteDRAM is already used in commercial and open-source designs:
- HDMI2USB: http://hdmi2usb.tv/home/
- NeTV2: https://www.crowdsupply.com/alphamax/netv2
- USBSniffer: http://blog.lambdaconcept.com/doku.php?id=products:usb_sniffer
- and others commercial designs...
[> Possible improvements
- add Avalon-ST interface.
- add support for Altera devices.
- add more documentation
- ... See below Support and consulting :)
If you want to support these features, please contact us at florent [AT] enjoy-digital.fr.
[> Getting started
- Install Python 3.6+ and FPGA vendor's development tools.
- Install LiteX and the cores by following the LiteX's wiki installation guide.
- You can find examples of integration of the core with LiteX in LiteX-Boards and in the examples directory.
Unit tests are available in ./test/. To run all the unit tests:
$ ./setup.py test
Tests can also be run individually:
$ python3 -m unittest test.test_name
LiteDRAM is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use LiteDRAM for closed-source proprietary designs. Even though we do not require you to do so, those things are awesome, so please do them if possible:
- tell us that you are using LiteDRAM
- cite LiteDRAM in publications related to research it has helped
- send us feedback and suggestions for improvements
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LiteDRAM.
[> Support and consulting
We love open-source hardware and like sharing our designs with others.
LiteDRAM is developed and maintained by EnjoyDigital.
If you would like to know more about LiteDRAM or if you are already a happy user and would like to extend it for your needs, EnjoyDigital can provide standard commercial support as well as consulting services.
So feel free to contact us, we'd love to work with you! (and eventually shorten the list of the possible improvements :)
E-mail: florent [AT] enjoy-digital.fr
Unless otherwise noted, LiteDRAM is Copyright 2012-2018 / EnjoyDigital Initial development is based on MiSoC's LASMICON / Copyright 2007-2016 / M-Labs Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Other authors retain ownership of their contributions. If a submission can reasonably be considered independently copyrightable, it's yours and we encourage you to claim it with appropriate copyright notices. This submission then falls under the "otherwise noted" category. All submissions are strongly encouraged to use the two-clause BSD license reproduced above.