litesata by enjoy-digital

Small footprint and configurable SATA core
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                                  Copyright 2014-2020 / EnjoyDigital
                                     Copyright 2014-2015 / HKU

                              A small footprint and configurable SATA core
                                      powered by Migen & LiteX

License

[> Intro

LiteSATA provides a small footprint and configurable SATA core.

LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

Using Migen to describe the HDL allows the core to be highly and easily configurable.

LiteSATA can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core.

[> Features

PHY:

  • OOB, COMWAKE, COMINIT
  • ALIGN inserter/remover and bytes alignment on K28.5
  • 8B/10B encoding/decoding in transceiver
  • Errors detection and reporting
  • 32 bits interface
  • 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)

Core:

  • Link:
    • CONT inserter/remover
    • Scrambling/Descrambling of data
    • CRC inserter/checker
    • HOLD insertion/detection
    • Errors detection and reporting
  • Transport/Command:
    • Easy to use user interfaces (Can be used with or without CPU)
    • 48 bits sector addressing
    • 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
    • Errors detection and reporting

Frontend:

  • Configurable crossbar (simply declare your crossbar and use crossbar.get_port() to add a new port!)
  • Ports arbitration transparent to the user
  • Synthetizable BIST
  • Striping module to segment data on multiple HDDs and increase write/read speed and capacity. (RAID0 equivalent)
  • Mirroring module for data redundancy and increase read speeds. (RAID1 equivalent)

[> FPGA Proven

LiteSATA is already used in commercial and open-source designs:

  • High End 50Mpixels CMOS Camera using CFAST & SD cards.
  • Low latency database research.

[> Possible improvements

  • add standardized interfaces (AXI, Avalon-ST)
  • add NCQ support
  • add AES hardware encryption
  • add on-the-flow compression/decompression
  • add support for Altera PHYs.
  • add support for Lattice PHYs.
  • add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are supported)
  • add Zynq Linux drivers.
  • ... See below Support and consulting :)

If you want to support these features, please contact us at florent [AT] enjoy-digital.fr.

[> Getting started

  1. Install Python 3.6+ and FPGA vendor's development tools.
  2. Install LiteX and the cores by following the LiteX's wiki installation guide.
  3. You can find examples of integration of the core with LiteX in LiteX-Boards and in the examples directory.

[> Tests

Unit tests are available in ./test/. To run all the unit tests:

$ ./setup.py test

Tests can also be run individually:

$ python3 -m unittest test.test_name

[> License

LiteSATA is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use LiteSATA for closed-source proprietary designs. Even though we do not require you to do so, those things are awesome, so please do them if possible:

  • tell us that you are using LiteSATA
  • cite LiteSATA in publications related to research it has helped
  • send us feedback and suggestions for improvements
  • send us bug reports when something goes wrong
  • send us the modifications and improvements you have done to LiteSATA.

[> Support and consulting

We love open-source hardware and like sharing our designs with others.

LiteSATA is developed and maintained by EnjoyDigital.

If you would like to know more about LiteSATA or if you are already a happy user and would like to extend it for your needs, EnjoyDigital can provide standard commercial support as well as consulting services.

So feel free to contact us, we'd love to work with you! (and eventually shorten the list of the possible improvements :)

[> Contact

E-mail: florent [AT] enjoy-digital.fr

Unless otherwise noted, LiteSATA is Copyright 2014-2020 / EnjoyDigital
Unless otherwise noted, LiteSATA is Copyright 2014-2015 / HKU

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this
   list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
   this list of conditions and the following disclaimer in the documentation
   and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


Other authors retain ownership of their contributions. If a submission can
reasonably be considered independently copyrightable, it's yours and we
encourage you to claim it with appropriate copyright notices. This submission
then falls under the "otherwise noted" category. All submissions are strongly
encouraged to use the two-clause BSD license reproduced above.

Project Meta

  • Registered on LibreCores 3 years ago
  • Project started 5 years ago
  • Last commit 1 month ago

Commits

{"labels":[2015,2016,2017,2018,2019,2020],"series":[[85,56,15,16,40,7]]}

Commits per year

Contributors

{"labels":[2015,2016,2017,2018,2019,2020],"series":[[2,2,3,3,1,1]]}

Unique contributors per year

Releases

2020.08 is is the latest of 2 releases.

  • 2020.08
    Aug 7, 2020 65d02a6
  • 2020.04
    Apr 11, 2020 2e5c5b1

Languages

{"labels":["Others","Python"],"series":[23,42]}

Share of languages used

Data Sheet
https://github.com/enjoy-digital/litesata
Last activity 1 month ago
2020.08 released 1 month ago
Primary language: Python
3 forks
7 watchers
10 stars
219 commits by 5 contributors
Florent Kermarrec Olof Kindgren Felix Held Tim 'mithro' Ansell Johan Klockars
0,14,1,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,0,0,1,0,0,0,0,0

activity over the last year

LibreCores data updated 30 days ago