Wishbone by fossi-foundation
The Wishbone SoC Interconnect Architecture
Wishbone is an interconnect for Systems-on-Chip. It's been placed in the public domain and is (as far as we know) free from patents and royalties. Wishbone is widely used in free and open source designs, but it can also be used in commercial designs without limitations.
Specification Documents
Today, the most used versions of Wishbone are revision B.3, and to a lesser extend, revision B.4. Revision B.4 most notably adds support for pipelining more efficient access to high-latency peripherals like DRAM.
Note: Version B.4 adds new features which are not as widely accepted as the functionality of the previous versions. A future version of the specification will try to reach wider agreement in this regard.
Superseeded Specifications
The following specification documents have been replaced by newer versions and should not be used for new designs any more.
Application Notes
- Combining Wishbone interface signals by Richard Herveille
- Review of Three SoC Buses by Rudolf Usselmann
Contributing and Maintainership
The primary author and maintainer of the Wishbone specification is Richard Herveille. The specification is now maintained by a group of people under the umbrella of the FOSSi Foundation. Please join the discussion@lists.librecores.org mailing list (subscribe) if you have questions or want to contribute to the specification process.
Notice is hereby given that this document is not copyrighted, and has been placed into the public domain. It may be freely copied and distributed by any means. The name ‘WISHBONE’ and the ‘WISHBONE COMPATIBLE’ rubber stamp logo are hereby placed into the public domain (within the scope of System-on-Chip design, System-on-Chip fabrication and related areas of commercial use). The WISHBONE logo may be freely used under the compatibility conditions stated elsewhere in this document. This specification may be used for the design and production of System-on-Chip (SoC) components without royalties or other financial obligations to OpenCores. The author(s) of this specification are not aware that the information contained herein, nor of products designed to the specification, cause infringement on the patent, copyright, trademark or trade secret rights of others. However, there is a possibility that such infringement may exist without their knowledge. The user of this document assumes all responsibility for determining if products designed to this specification infringe on the intellectual property rights of others.
https://github.com/fossi-foundation/wishbone
CC0 (public domain)
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