SDLIB by hutch31

srdy-drdy library

Srdy-Drdy Library

The Srdy-Drdy library is an interface standard for connecting RTL blocks together in an FPGA and ASIC with a unidirectional interface that provides bidirectional flow control. The library is also a set of components which are compliant to the interface definition and provide a variety of functions from basic timing closure to buffering and arbitration between blocks.

Project Meta

  • Registered on LibreCores 3 years ago
  • Project started 9 years ago
  • Last commit 12 days ago



Commits per year



Unique contributors per year


Data not available



Share of languages used

Data Sheet
Project Web Site
Public Domain
Issue Tracker
Last activity 12 days ago
Primary language: Verilog-SystemVerilog
1 fork
5 watchers
4 stars
147 commits by 16 contributors
Guy Hutchison Guy Hutchison Frank Wang Frank Wang Gerald Schmidt

activity over the last year

LibreCores data updated 12 days ago