SDLIB by hutch31

srdy-drdy library

Srdy-Drdy Library

The Srdy-Drdy library is an interface standard for connecting RTL blocks together in an FPGA and ASIC with a unidirectional interface that provides bidirectional flow control. The library is also a set of components which are compliant to the interface definition and provide a variety of functions from basic timing closure to buffering and arbitration between blocks.

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  • Registered on LibreCores 3 years ago
  • Project started 9 years ago
  • Last commit 1 year ago



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Last activity 1 year ago
Primary language: Verilog-SystemVerilog
1 fork
5 watchers
4 stars
146 commits by 16 contributors
Guy Hutchison Guy Hutchison Frank Wang Frank Wang Gerald Schmidt

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LibreCores data updated 7 months ago