SDLIB by hutch31

srdy-drdy library

Srdy-Drdy Library

The Srdy-Drdy library is an interface standard for connecting RTL blocks together in an FPGA and ASIC with a unidirectional interface that provides bidirectional flow control. The library is also a set of components which are compliant to the interface definition and provide a variety of functions from basic timing closure to buffering and arbitration between blocks.

Project Meta

  • Registered on LibreCores 3 years ago
  • Project started 9 years ago
  • Last commit 12 days ago

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{"labels":[2012,2013,2014,2016,2017,2019,2020,2021,2015,2018],"series":[[46,30,11,27,19,2,11,1,0,0]]}

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{"labels":[2012,2013,2014,2016,2017,2019,2020,2021,2015,2018],"series":[[2,6,3,5,6,2,2,1,0,0]]}

Unique contributors per year

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{"labels":["Others","Verilog-SystemVerilog","reStructuredText","Python"],"series":[13,116,8,6]}

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Project Web Site
https://github.com/hutch31/sdlib.git
Public Domain
Issue Tracker
Last activity 12 days ago
Primary language: Verilog-SystemVerilog
1 fork
5 watchers
4 stars
147 commits by 16 contributors
Guy Hutchison Guy Hutchison Frank Wang Frank Wang Gerald Schmidt
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0

activity over the last year

LibreCores data updated 12 days ago