SDLIB by hutch31

srdy-drdy library

Srdy-Drdy Library

The Srdy-Drdy library is an interface standard for connecting RTL blocks together in an FPGA and ASIC with a unidirectional interface that provides bidirectional flow control. The library is also a set of components which are compliant to the interface definition and provide a variety of functions from basic timing closure to buffering and arbitration between blocks.

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  • Registered 11 months ago
  • Started 6 years ago
  • Last commit 1 year ago

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{"labels":[2012,2013,2014,2016,2017,2015,2018],"series":[["46","30","11","27","19",null,null]]}

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{"labels":[2012,2013,2014,2016,2017,2015,2018],"series":[["2","6","3","5","6",null,null]]}

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{"labels":["Others","Verilog-SystemVerilog","Python","C++"],"series":[6,116,8,6]}

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https://github.com/hutch31/sdlib.git
Public Domain
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Last updated 1 year ago
Language: Verilog-SystemVerilog
1 fork
5 watchers
4 stars
133 commits by 14 contributors
Guy Hutchison Guy Hutchison Frank Wang Frank Wang Gerald Schmidt

Activity in last 1 year

Updated 4 months ago