TV80 is a Z80-compatible synthesizable Verilog core.
The TV80 core aims to be an area-efficient core which closely mimics the original operation and cycle timing of the Zilog Z80. The core has been used by the author/porter in multiple silicon tape-outs as a utility processor or programmable state machine.
The top level wrapper is the tv80s, which presents a synchronous interface where all signals transition on the positive edge of the clock.
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Data Sheet
Project Web Site
https://github.com/hutch31/tv80.git
MIT
Issue Tracker
Last activity 9 months ago
Primary language: Verilog-SystemVerilog
1 open issue
2 forks
2 watchers
5 stars
21 commits by 4 contributors
https://github.com/hutch31/tv80.git
MIT
Issue Tracker
Last activity 9 months ago
Primary language: Verilog-SystemVerilog
1 open issue
2 forks
2 watchers
5 stars
21 commits by 4 contributors
0,0,0,0,0,0,0,0,1,0,0,1,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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LibreCores data updated 4 months ago