The Generic Logic Interfacing Project (GLIP) by imphil

Simple FIFO-based, transport-agnostic device - host communication

GLIP - The Generic Logic Interfacing Project

GLIP, the "Generic Logic Interfacing Project", is a solution for transferring data through FIFOs between a host, usually a PC, and a target, usually a hardware component such as an FPGA or a microcontroller. The actual data transport can happen through various interfaces, such as USB 2.0, JTAG or TCP. GLIP encapsulates all low-level details of the data transfers and provides on the host side an easy to use C library, and on the target side ready to use interfaces (e.g. in Verilog) to quickly setup a working communication.

For more information, see http://glip.io.

Most of GLIP is licensed under the MIT license, which essentially allows you to
use GLIP in commercial as well as non-commercial open and closed source 
projects. Note that some backends might require components which are published
under a different license. Check the individual backends for details.

The MIT License
===============

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.

Project Meta

  • Registered 2 years ago
  • Started 4 years ago
  • Last commit 1 year ago

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{"labels":[2014,2015,2016,2017,2018],"series":[["14","12","84","52",null]]}

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{"labels":["Others","Verilog-SystemVerilog","Markdown","make","C\/C++ Header","C","Tcl\/Tk","C++"],"series":[4,48,35,13,12,11,7,4]}

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Data Sheet
Project Web Site
https://github.com/TUM-LIS/glip
MIT
Issue Tracker
Last updated 1 year ago
Language: Verilog-SystemVerilog
13 open issues
1 open pull request
8 forks
7 watchers
11 stars
162 commits by 9 contributors
Philipp Wagner Stefan Wallentowitz Max Koenen Philipp Wagner Stefan Rösch

Activity in last 1 year

Updated 1 year ago