UART for FPGA by jakubcabal
Simple UART for FPGA
Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA.
Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!
The UART controller was simulated and tested in hardware.
Inputs and outputs ports:
-- CLOCK AND RESET CLK : in std_logic; -- system clock RST : in std_logic; -- high active synchronous reset -- UART INTERFACE UART_TXD : out std_logic; -- serial transmit data UART_RXD : in std_logic; -- serial receive data -- USER DATA INPUT INTERFACE DIN : in std_logic_vector(7 downto 0); -- input data to be transmitted over UART DIN_VLD : in std_logic; -- when DIN_VLD = 1, input data (DIN) are valid DIN_RDY : out std_logic -- when DIN_RDY = 1, transmitter is ready and valid input data will be accepted for transmiting -- USER DATA OUTPUT INTERFACE DOUT : out std_logic_vector(7 downto 0); -- output data received via UART DOUT_VLD : out std_logic; -- when DOUT_VLD = 1, output data (DOUT) are valid (is assert only for one clock cycle) FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
CLK_FREQ : integer := 50e6; -- system clock frequency in Hz BAUD_RATE : integer := 115200; -- baud rate value PARITY_BIT : string := "none"; -- type of parity: "none", "even", "odd", "mark", "space" USE_DEBOUNCER : boolean := True -- enable/disable debouncer
Table of resource usage summary:
|Use debouncer||Parity type||LE (LUT+FF)||LUT||FF||M9k||Fmax|
Implementation was performed using Quartus Prime Lite Edition 18.1.0 for Intel Cyclone 10 FPGA (10CL025YU256C8G). Setting of some generics: BAUD_RATE = 115200, CLK_FREQ = 50e6.
A basic simulation is prepared in the repository. You can use the prepared TCL script to run simulation in ModelSim.
vsim -do sim/sim.tcl
UART loopback example:
The UART loopback example design is for testing data transfer between FPGA and PC. I use it on my FPGA board CYC1000 with Intel Cyclone 10 FPGA (10CL025YU256C8G) and FTDI USB to UART Bridge.
This UART controller is available under the MIT license (MIT). Please read LICENSE file.
The MIT License (MIT) Copyright (c) 2015 Jakub Cabal Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.