IOb-MEM by jjts

IOb-mem

Test all memory modules

From the top directory, type make.

Test a specific memory module

Go to the memory folder and type make.

Simulate a specific memory module

In the memory folder, type make sim.

Parameter configuration

For specific memory modules, there are parameters that can be configured.

RAM: RAM=1 to use RAM; RAM=0 otherwise (default).

R: R=1 for READ_DATA > WRITE_DATA; R=0 otherwise (default).

MIT License

Copyright (c) 2020 Jose T. de Sousa

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

Project Meta

  • Registered on LibreCores 1 month ago
  • Project started 5 months ago
  • Last commit 1 month ago

Commits

{"labels":[2020],"series":[[93]]}

Commits per year

Contributors

{"labels":[2020],"series":[[9]]}

Unique contributors per year

Releases

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Languages

{"labels":["Others","Verilog-SystemVerilog","make"],"series":[3,24,15]}

Share of languages used

Data Sheet
https://github.com/IObundle/iob-mem
Last activity 1 month ago
Primary language: Verilog-SystemVerilog
93 commits by 9 contributors
André Merendeira Jose de Sousa Jose Sarmento P_Miranda Pedro Rodrigues
0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,7,8,10,4,9,12,6,1,3,2,3,1,1,3,0,0,0,13,8,0,0,0,0,0,0,0

activity over the last year

LibreCores data updated 1 month ago