OpenRAM
An open-source static random access memory (SRAM) compiler.
What is OpenRAM?
OpenRAM is an award winning open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.
Documentation
Please take a look at our presentation We have created a detailed presentation that serves as our documentation. This is the most up-to-date information, so please let us know if you see things that need to be fixed.
Basic Setup
Dependencies
The OpenRAM compiler has very few dependencies:
- Ngspice 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) or Xyce 7.2 (or later)
- Python 3.5 or higher
- Various Python packages (pip install -r requirements.txt)
- Git
If you want to perform DRC and LVS, you will need either:
You must set two environment variables:
- OPENRAM_HOME should point to the compiler source directory.
- OPENERAM_TECH should point to one or more root technology directories (colon separated).
Environment
For example add this to your .bashrc:
export OPENRAM_HOME="$HOME/openram/compiler"
export OPENRAM_TECH="$HOME/openram/technology"
You may also wish to add OPENRAM_HOME to your PYTHONPATH:
export PYTHONPATH="$PYTHONPATH:$OPENRAM_HOME"
We include the tech files necessary for SCMOS SCN4M_SUBM. The SCMOS spice models, however, are generic and should be replaced with foundry models. If you are using FreePDK45, you should also have that set up and have the environment variable point to the PDK. For example add this to your .bashrc:
export FREEPDK45="/bsoe/software/design-kits/FreePDK45"
You may get the entire FreePDK45 PDK here. If you are using SCMOS, you should install Magic and Netgen. We have included the most recent SCN4M_SUBM design rules from Qflow.
Basic Usage
Once you have defined the environment, you can run OpenRAM from the command line using a single configuration file written in Python.
For example, create a file called myconfig.py specifying the following parameters for your memory:
# Data word size
word_size = 2
# Number of words in the memory
num_words = 16
# Technology to use in $OPENRAM_TECH
tech_name = "scn4m_subm"
# You can use the technology nominal corner only
nominal_corner_only = True
# Or you can specify particular corners
# Process corners to characterize
# process_corners = ["SS", "TT", "FF"]
# Voltage corners to characterize
# supply_voltages = [ 3.0, 3.3, 3.5 ]
# Temperature corners to characterize
# temperatures = [ 0, 25 100]
# Output directory for the results
output_path = "temp"
# Output file base name
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
# Disable analytical models for full characterization (WARNING: slow!)
# analytical_delay = False
You can then run OpenRAM by executing:
python3 $OPENRAM_HOME/openram.py myconfig
You can see all of the options for the configuration file in $OPENRAM_HOME/options.py
Unit Tests
Regression testing performs a number of tests for all modules in OpenRAM. From the unit test directory ($OPENRAM_HOME/tests), use the following command to run all regression tests:
python3 regress.py
To run a specific test:
python3 {unit test}.py
The unit tests take the same arguments as openram.py itself.
To increase the verbosity of the test, add one (or more) -v options:
python3 tests/00_code_format_check_test.py -v -t freepdk45
To specify a particular technology use "-t " such as "-t freepdk45". The default for a unit test is scn4m_subm. The default for openram.py is specified in the configuration file.
Porting to a New Technology
If you want to support a new technology, you will need to create:
- a setup script for each technology you want to use
- a technology directory for each technology with the base cells
We provide two technology examples for SCMOS and FreePDK45. Each specific technology (e.g., FreePDK45) should be a subdirectory (e.g., $OPENRAM_TECH/freepdk45) and include certain folders and files:
- gds_lib folder with all the .gds (premade) library cells:
- dff.gds
- sense_amp.gds
- write_driver.gds
- cell_1rw.gds
- replica_cell_1rw.gds
- dummy_cell_1rw.gds
- sp_lib folder with all the .sp (premade) library netlists for the above cells.
- layers.map
- A valid tech Python module (tech directory with __init__.py and tech.py) with:
- References in tech.py to spice models
- DRC/LVS rules needed for dynamic cells and routing
- Layer information
- Spice and supply information
- etc.
Get Involved
- Report bugs by submitting Github issues.
- Develop new features (see how to contribute)
- Submit code/fixes using a Github pull request
- Follow our project.
- Read and cite our ICCAD paper
Further Help
- Additional hints
- Documentation
- OpenRAM Slack Workspace
- OpenRAM Users Group (subscribe here)
- OpenRAM Developers Group (subscribe here)
License
OpenRAM is licensed under the BSD 3-clause License.
Contributors & Acknowledgment
- Matthew Guthaus from VLSIDA created the OpenRAM project and is the lead architect.
- James Stine from VLSIARCH co-founded the project.
- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera
If I forgot to add you, please let me know!
BSD 3-Clause License Copyright (c) 2019, Regents of the University of California and The Board of Regents for the Oklahoma Agricultural and Mechanical College (acting for and on behalf of Oklahoma State University) All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
https://github.com/VLSIDA/OpenRAM.git
Issue Tracker
Last activity 4 days ago
v1.1.19 released 7 months ago
Primary language: Python
15 open issues
4 open pull requests
120 forks
49 watchers
386 stars
3699 commits by 62 contributors
activity over the last year
LibreCores data updated 2 days ago