no2usb by no2fpga
Nitro USB core
This fpga core implements a USB Full-Speed SIU using only normal FPGA CMOS IOs.
The main design goals are:
- Small and efficient (originaly targetting ice40)
- Flexible, even at runtime (dynamic EP config)
- Constant size no matter how many EPs are use
- Single clock-domain (currently 48M but soon extended to any 12M multiple starting at 36M).
The current code in this repo targets the iCE40 only and uses some direct
SB_RAM_4K instances. A more generic version will be added soon,
it has already been run on ECP5 for the Hack-a-day badge 2019 supercon but
the small tweaks haven't been added here yet.
See LICENSE.md for the licenses of the various components in this repository
In general in this repository:
The HDL core itself is licensed under the terms of the "CERN Open Hardware Licence Version 2 - Permissive" license.
The custom USB stack is licensed under the terms of the GNU Lesser General Public License v3.0 or later.
Except for the parts that are re-used in the tiny-usb stack driver, those are licensed under the terms of the MIT license.
The tiny-usb stack driver is licensed under the terms of the MIT license.
The various small utilities / scripts are licensed under the terms of the MIT license.
Refer to the header of each file to see which license it is under.
doc/ subdirectory for the full text of those licenses.