opengfx430 by olivier-girard

The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.

Table of content:
gfx_structure.png
Copyright (c) 2014, olgirard
All rights reserved.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright notice, this
  list of conditions and the following disclaimer.

* Redistributions in binary form must reproduce the above copyright notice,
  this list of conditions and the following disclaimer in the documentation
  and/or other materials provided with the distribution.

* Neither the name of openmsp430 nor the names of its
  contributors may be used to endorse or promote products derived from
  this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Project Meta

  • Registered 2 years ago
  • Started 2 years ago
  • Last commit 2 years ago

Commits

{"labels":[2016,2017,2018],"series":[["41",null,null]]}

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{"labels":[2016,2017,2018],"series":[["1",null,null]]}

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{"labels":["Others","Verilog-SystemVerilog","Markdown","Coq","HTML"],"series":[0,14,8,2,1]}

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Data Sheet
https://github.com/olgirard/opengfx430
Last updated 2 years ago
Language: Verilog-SystemVerilog
41 commits by 1 contributor
Olivier Girard

Activity in last 1 year

Updated 1 year ago