FuseSoC by olofk

a package manager and a set of build tools for FPGA/ASIC development

FuseSoC

CI status https://img.shields.io/pypi/dm/fusesoc.svg?label=PyPI%20downloads

Introduction

FuseSoC is an award-winning package manager and a set of build tools for HDL (Hardware Description Language) code.

Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions.

FuseSoC makes it easier to

  • reuse existing cores
  • create compile-time or run-time configurations
  • run regression tests against multiple simulators
  • Port designs to new targets
  • let other projects use your code
  • set up continuous integration

FuseSoC is non-intrusive Most existing designs doesn't need any changes to work with FuseSoC. Any FuseSoC-specific patches can be applied on the fly during implementation or simulation

FuseSoC is modular It can be used as an end-to-end flow, to create initial project files for an EDA tool or integrate with your custom workflow

FuseSoC is extendable Latest release support simulating with GHDL, Icarus Verilog, Isim, ModelSim, Verilator and Xsim. It also supports building FPGA images with Altera Quartus, project IceStorm, Xilinx ISE and Xilinx Vivado. Support for a new EDA tool requires ~100 new lines of code and new tools are added continuously

FuseSoC is standard-compliant Much effort has gone into leveraging existing standards such as IP-XACT and vendor-specific core formats where applicable.

FuseSoC is resourceful The standard core library currently consisting of over 100 cores including CPUs, peripheral controllers, interconnects, complete SoCs and utility libraries. Other core libraries exist as well and can be added to complement the standard library

FuseSoC is free software It puts however no restrictions on the cores and can be used to manage your company's internal proprietary core collections as well as public open source projects

FuseSoC is battle-proven It has been used to successfully build or simulate projects such as Nyuzi, Pulpino, VScale, various OpenRISC SoCs, picorv32, osvvm and more.

Read more in the online documentation, or get straight into business with the quick start below

Getting started

Install latest stable version:

sudo pip install fusesoc

or install latest development version from git:

git clone https://github.com/olofk/fusesoc
cd fusesoc
sudo pip install -e .

FuseSoC should now be installed and ready to use. Next step is to add some cores to use with FuseSoC. FuseSoC itself doesn't come with any cores but there is a FuseSoC base library with a lot of useful cores. In addition to that, many projects such as OpenTitan, SweRVolf and OpenPiton provide their own core libraries.

If you have one of the supported simulators installed, and want to do a quick check to see that it's working, follow the steps below, or look at the tutorial in the online documentation for a more thorough introduction.

Quick start

Create and enter an empty workspace

mkdir workspace
cd workspace

Install the FuseSoc base library into the workspace

fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores

Get a list of cores found in the workspace

fusesoc core list

If you have any of the supported simulators installed, you can try to run a simulation on one of the cores as well. For example, fusesoc run --target=sim i2c will run a regression test on the core i2c with icarus verilog. If you want to try another simulator instead, add e.g. --tool=modelsim or --tool=xcelium between run and i2c.

fusesoc --help will give you more information on commands and switches.

Did it work? Great! FuseSoC can be used to create FPGA images, perform linting, manage your IP libraries or do formal verification as well. Check out the online documentation and tutorial to learn more about creating your own core files and using existing ones. If it didn't work, please get in touch

Next steps

A good way to get your first hands-on experience with FuseSoC is to contribute to the LED to Believe project. This project aims to used FuseSoC to blink a LED on every available FPGA development board in existence. There are already around 40 different boards supported. If you're board is already supported, great, then you can run your first FuseSoC-based design. If it's not supported, great, you now have the chance to add it to the list of supported boards. Either way, head over to LED to Believe to learn more and see how to go from a blinking LED to running a RISC-V core on an FPGA.

Need help?

The online documentation contains a tutorial as well as information for users and developers of cores, or FuseSoC itself. For some quick communication with the active developers, feel free to join us at the FuseSoC chat. If you have found an issue, or want to know more about currently known problems, check out the issue tracker.

If you are looking for professional paid support, we are happy to provide feature additions, bug fixes, user training, setting up core libraries, migrating existing designs to FuseSoC and other things.

Please contact olof.kindgren@gmail.com for more info

Further reading

BSD 2-Clause License

Copyright FuseSoC contributors
All rights reserved.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright notice, this
  list of conditions and the following disclaimer.

* Redistributions in binary form must reproduce the above copyright notice,
  this list of conditions and the following disclaimer in the documentation
  and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Project Meta

  • Registered on LibreCores 5 years ago
  • Project started 10 years ago
  • Last commit 10 months ago

Commits

{"labels":[2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021],"series":[[1,136,152,151,78,204,206,177,79,91,0]]}

Commits per year

Contributors

{"labels":[2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021],"series":[[1,1,8,9,8,8,11,9,11,12,0]]}

Unique contributors per year

Releases

1.11.0 is is the latest of 23 releases.

  • 1.11.0
    Jun 16, 2020 f525483
  • 1.10
    Mar 4, 2020 ed63efa
  • 1.9.3
    Oct 14, 2019 41c8e5f
  • 1.9.2
    Jun 17, 2019 a2c00f7
  • 1.9.1
    Mar 3, 2019 9be0378
  • 1.9
    Dec 18, 2018 4e44d59
  • 1.8.4
    Aug 18, 2018 ff00eab
  • 1.8.3
    Jul 24, 2018 53d12e9
  • 1.8.2
    Jun 26, 2018 fdab087
  • 1.8.1
    Mar 22, 2018 390fe9a
  • 1.8
    Feb 5, 2018 36c4d4b
  • 1.7
    Aug 12, 2017 d9d870c
  • 1.6.1
    Mar 21, 2017 5dce097
  • 1.6
    Dec 24, 2016 b94fbf4
  • 1.5
    Aug 8, 2016 d70e34a
  • 1.4
    Feb 3, 2016 07aca69
  • 1.3
    Nov 16, 2015 f2ff84d
  • 1.2
    Feb 24, 2015 08d843a
  • 1.1
    Apr 15, 2014 6d16af4
  • 1.0
    Feb 22, 2014 3c17a39
  • orpsoc-3.2
    Feb 14, 2014 23ed82e
  • orpsoc-3.1
    Sep 28, 2013 d4797a4
  • orpsoc-3.0
    Aug 20, 2013 eaa5695

Languages

{"labels":["Others","Python","reStructuredText","Verilog-SystemVerilog","YAML","Bourne Shell"],"series":[6,42,23,5,4,4]}

Share of languages used

Data Sheet
Project Web Site
https://github.com/olofk/fusesoc
GPLv3
Issue Tracker
Last activity 10 months ago
1.11.0 released 1 year ago
Primary language: Python
81 open issues
10 open pull requests
123 forks
59 watchers
578 stars
1275 commits by 49 contributors
Olof Kindgren Olof Kindgren Philipp Wagner Franck Jullien Philipp Wagner
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,9,5,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

activity over the last year

LibreCores data updated 9 months ago