fifo by olofk

Generic FIFO implementation with optional FWFT


A FuseSoC-compatible library of FIFO implementations

RTL code

The following RTL components exist in the library


A generic FIFO implementation


A module to place on the output of any FIFO to turn it into a FWFT FIFO


FIFO with FWFT (First word fall-through)


A generic asynchronous FIFO


A generic Dual Port RAM used as backend in fifo.v


Wrapper with proper reset handling for the FIFOE1 macros found in some Xilinx FPGA families such as Virtex-5, Virtex-6 and all 7-series devices.


Timing constraints file for Quartus with rules for the dual clock FIFO. To use the constraints, include the file in your project and call dual_clock_fifo_false_paths path/to/fifo/instance from your main constraints file for each instance of the dual clock FIFO


All components have FuseSoC support and can be run with multiple simulators and configurations.

To find all compile/run -time options run fusesoc sim fifo --help

To specify which simulator to use, add --sim=<simulator> after the sim argument, where <simulator> can be any FuseSoC-supported event-based verilog simulator (i.e. icarus, isim, modelsim, rivierapro, xsim).

Add the FIFO library to your FuseSoC library path and run

dual clock FIFO testbench

fusesoc sim --testbench=dual_clock_fifo_tb fifo


fusesoc sim --testbench=fwft_fifo_tb fifo


fusesoc sim --testbench=fifo_tb fifo

Xilinx FIFOE1

fusesoc sim xilinx_fifoe1

Note that this testbench requires the $XILINX_VIVADO environment variable to be set and only runs on XSim bundled with Vivado

Project Meta

  • Registered on LibreCores 5 years ago
  • Project started 7 years ago
  • Last commit 1 year ago



Commits per year



Unique contributors per year


v1.3 is is the latest of 5 releases.

  • v1.3
    Nov 28, 2017 b4ff50a
  • v1.2.1
    May 2, 2017 73c1ae8
  • v1.2
    Apr 3, 2017 77f66d0
  • v1.1
    Sep 28, 2016 4f58a15
  • v1.0
    Oct 15, 2014 f5c4d14



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Data Sheet
Last activity 1 year ago
v1.3 released 4 years ago
Primary language: Verilog-SystemVerilog
1 open issue
10 forks
4 watchers
20 stars
35 commits by 2 contributors
Olof Kindgren Stefan Kristiansson

activity over the last year

LibreCores data updated 1 year ago