LED to Believe by olofk
LED to believe
This project aims to provide LED blinking examples for all the FPGA dev boards in the world.
The goal is to provide a quick way to test your new FPGA board and get acquainted with using FuseSoC in your design flow.
Each FPGA board is implemented as a separate FuseSoC target and users are highly encouraged to add support for their any board at their disposal so that we can have a large collection.
How to use
This project is available in the FuseSoC base library, so if you have FuseSoC installed, you likely already have this project as well.
To check if it's available run
fusesoc core list and check for a core called
If it's not there, try to run
fusesoc library update to refresh the core libraries and look again.
If it's still not there, or if you want to modify the project, e.g. to add support for an additional board, you can add LED to believe as a new core library with
fusesoc library add blinky https://github.com/fusesoc/blinky. LED to believe will now be added as a new library and downloaded to
To build for your particular board, run
fusesoc run --target=<board> fusesoc:utils:blinky where
<board> is one of the boards listed in the Board support section below.
fusesoc core show fusesoc:utils:blinky to find all available targets.
There is also a simulation target available to test the core without any hardware. To use this, run
fusesoc run --target=sim fusesoc:utils:blinky.
The simulation target has a number of target-specific configuration parameters that can be set. All target-specific parameters goes on the end of the command line (after the core name).
To list all simulation parameters, run
fusesoc run --target=sim fusesoc:utils:blinky --help.
Example: To run four pulses with a simulated clock frequency of 4MHz and creating a VCD file, run
fusesoc run --target=sim fusesoc:utils:blinky --pulses=4 --clk_freq_hz=4000000 --vcd.
The default simulator to use is Icarus Verilog, but other simulators can be used by setting the
--tool parameter after the
Currently supported simulators for this target are icarus, modelsim and xsim. To use e.g. modelsim run
fusesoc run --target=sim --tool=modelsim fusesoc:utils:blinky.
What to do next
That was fun, wasn't it? And did you know that once you have gotten a LED to blink in this way, you are actually 90% of the way already to run a small SoC with a RISC-V CPU on the same board. Maybe your board is already supported? Or maybe you're up to the challenge of adding support for it. All it takes is to create a 16MHz clock and allocate an output pin to connect a UART. For more info, move on to learn about and run SERV, the world's smallest RISC-V CPU
The following boards are currently supported:
This are two variants for this board:
- 15t has ~10K LUTs. Use
- 35t has ~20K LUTs. Use
Chameleon96 (Arrow 96 CV SoC Board)
EBAZ4205 'Development' Board
This development board featuring
Zynq 7010 was the control card of Ebit E9+
Note: The Zynq PL on this board doesn't have a reference clock without involving the Zynq PS. To workaround this problem, the onboard 33MHz clock oscillator can be physically bridged to the PL clock input pin. To do this, solder a fine wire from R2340 (the clock output of X8) to the PL clock input on the pad for the missing R1372 near X5.
EP2C5T144 Development Board
Nandland Go Board
Microsemi Polarfire Evaluation Kit
MYIR FZ3 - Deep Learning Accelerator Card
QMTECH Wukong Board Artix-7 XC7A100T & XC7A200T
Wukong_v1 for revision 1 ,
Wukong_200t_v2 for revision 2. Those boards can be programmed with openFPGALoader.
SoCKit Development Kit
Note: There is no on-board clock for Zynq PL. Therefore, in this example PL clock is generated and supplied from Zynq PS in the block design. Block design tcl script is generated on Vivado 2020.2. If you have an other version of Vivado installation, you should just create and export the block design bd_ultra96_v2.tcl with fabric clock PL0 is enabled and made external.
ULX3S comes in different sizes. The targets
ulx3s_85 are defined for different FPGA sizes
Zybo Z7-10 & Zybo Z7-20
Zybo Z7 comes with two variants of the Zynq SoC. The targets
zybo_z7-20 are defined for different SoC configurations.
MIT License Copyright (c) 2018 fusesoc Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.