wb_intercon
Wishbone interconnect utilities
Files
- wb_mux.v Wishbone multiplexer
- wb_arbiter.v Wishbone round-robin arbiter
- wb_data_resize.v Converts 32-bit accesses from master to 8-bit slaves
- wb_upsizer.v Converts accesses from a master to a slave with N times wider data path
wb_intercon also implements a FuseSoC generator called wb_intercon_gen. More info and usage can be found by running fusesoc gen show wb_intercon_gen once wb_intercon is added to the FuseSoC library
ISC License Copyright 2019, Olof Kindgren Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
Data Sheet
https://github.com/olofk/wb_intercon
Last activity 3 months ago
v1.2.2 released 1 year ago
Primary language: Verilog-SystemVerilog
3 forks
5 watchers
14 stars
27 commits by 1 contributor
Last activity 3 months ago
v1.2.2 released 1 year ago
Primary language: Verilog-SystemVerilog
3 forks
5 watchers
14 stars
27 commits by 1 contributor
activity over the last year
LibreCores data updated 1 month ago