OpTiMSoC: Open Tiled Manycore System-on-Chip

OpTiMSoC is an award-winning an open-source framework primarily written in Verilog which allows you to build your own manycore System-on-Chip by connecting tiles like processors and memories through a Network-on-Chip. The resulting system can then be simulated on a PC or synthesized for an FPGA. You want to know how a SoC really works by taking a deep look inside? You want to evaluate the benefit of a new hardware accelerator? You want to test algorithms to assign tasks efficiently to different processing cores? OpTiMSoC gets you started!

Getting started

OpTiMSoC comes with an ever growing documentation as well as a lot of sample code that you can use to get started quickly. Depending on the hardware and software you have available, you can start by running a small existing system on an FPGA or simulating it (with Verilator or ModelSim).

Read the Documentation

A sneak peek

OpTiMSoC can boot Linux! Have a look, and read more about it in our blog.

Get involved

OpTiMSoC welcomes your contribution! Our web site has more information how to get in touch and contribute. Or simply file an issue or a pull request here on GitHub.

License

OpTiMSoC is licensed under the permissive MIT license, see COPYING for details.

Unless otherwise defined in a file, the following license applies to
OpTiMSoC:

Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.

Project Meta

Registered on LibreCores 4 years ago
Project started 9 years ago
Last commit 8 months ago

Commits

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Commits per year

Contributors

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Unique contributors per year

Releases

v2018.1 is is the latest of 4 releases.

v2018.1

Dec 20, 2018 89eea53
v2018.1-rc1

Dec 18, 2018 171a620 prerelease
v2016.1

Sep 2, 2016 0c6df64
v2015.1

Dec 29, 2015 e1d562a

Languages

{"labels":["Others","Verilog-SystemVerilog","C\/C++ Header","C","Markdown","C++","make","Python","reStructuredText","Bourne Shell","YAML"],"series":[315,266,117,96,58,52,51,49,44,22,21]}

Share of languages used

Data Sheet

Project Web Site
https://github.com/optimsoc/optimsoc.git
MIT
Issue Tracker
Last activity 5 months ago
v2018.1 released 2 years ago
Primary language: Verilog-SystemVerilog
43 open issues
3 open pull requests
18 forks
21 watchers
46 stars
2526 commits by 16 contributors

0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

activity over the last year

LibreCores data updated 5 months ago

OpTiMSoC by optimsoc