Planet LibreCores

Embench 1.0 Benchmark Suite for IoT Class Devices Released

by FOSSi Foundation on FOSSi Foundation - News & Posts
The Embench group announces the first full release of its free and open source benchmark suite for IoT class devices. The benchmark suite, comprising 19 real programs, has proved popular across industry and academia since the pre-release version 0.5 was made available in February 2020. The project is developed by an open group, with contributors from companies and universities worldwide. The code is available under a free and open source license on GitHub (see ...

SoC Integration Testing: Intro and Challenges

by Matthew Ballance on Bits, Bytes, and Gates
As I mentioned in my end-of-year post, one of my 2020 projects was to develop a design for the Google/eFabless/SkyWater Multi-Project Wafer (MPW) fab run. One thing I looked forward to was applying elements of the Python-based verification flow that I've been developing. Doing so highlighted a gap in my verification toolkit: reusable infrastructure for SoC-level verification.Caravel and the User

Poor Men's SMU, part 3: Diodes are Forever

by Fatsie on Chips4Makers.io
This is third part on my adventures with the AD5522 SMU development board. For history you can look at part 1 and part 2. After getting the SMU working and being able to operate it from Jupyter notebooks on a raspberry Pi I now decided to use the device to measure some diodes/LEDs. I did the measurement and the plotting again in a Python notebook. I also used the notebook to comment on the results. Head over to the html version of the notebook to learn all about the diode and LED ...

Open-Hardware BeagleV, at $149, is the Most Affordable RISC-V Linux Computer Yet

by Gareth Halfacree on FOSSi – AB Open
teaser image BeagleBoard.org and Seeed Studio, in partnership with StarFive, have opened applications for an open-source, highly-affordable, Linux-capable RISC-V single-board computer: the $149 BeagleV. Launching with an initial pilot production batch in late March to early April, the BeagleV is an open-source single-board computer built around a StarFive system-on-chip implementing SiFIve’s U74 RISC-V cores. The two 64-bit application-processor-class RISC-V cores run at 1.5GHz, while accelerators ...

El Correo Libre Issue 34

by Gareth Halfacree on LibreCores - Medium
teaser image Looking Back on 2020, The Year of the Open-Source Chip2020 was quite a year. Even though it played out different for each of us, we were united in that many of our plans didn’t work out. Much has been written about missed chances, but let’s end this year on a positive note and focus on the good things. After all, that’s something the software and hardware development community have always been good at: embracing change. So let’s call 2020 an “agile year” and do a “sprint recap.”A key part ...

Poor Men's SMU, part 2

by Fatsie on Chips4Makers.io
teaser image This is a continuation of my adventure with the AD5522 development board (see part 1 ). I did make progress on setting it up but as always it has taken much more time than wanted to debug the setup. Schrödinger's cat One problem I had to solve was that the setup sometimes seemed to work flawlessly but other times not. Especially when I tried to debug the setup by looking at it though an oscilloscope all seemed to work but it did not seem to work when not looking at it. After some more ...

Let’s Make RISC-V Connected Systems Synonymous with Security

by Jon Jacobsen on Blog – RISC-V International
teaser image This blog was submitted by Silex Insight.   If you are designing systems based on a RISC-V architecture, for example to run highly connected applications, you want to include tight, future-proof security. Both for your customers’ experience and your reputation, you want to avoid a breach of security – leaking private data or even changing the functionality. Therefore, security should be part of the fabric of your system. Luckily, the RISC-V architecture offers a solid ground for security. ...

Poor Men's Source Measurement Unit (SMU)

by Fatsie on Chips4Makers.io
teaser image SMU ? In my previous professional life doing semiconductor process development I used so called source measure units (SMUs) for measuring out transistors. Although I don't remember the exact type number, I guess I had access to a HP 4145A semiconductor parametric analyzer. Nice thing about these units is that these allow 4-quadrant operation, e.g. allow all the 4 combinations of positive or negative voltage with positive or negative current. It allows to force a voltage and measure current ...

Looking back on 2020, the year of the open source chip

by FOSSi Foundation on FOSSi Foundation - News & Posts
Dear Free and Open Source Silicon enthusiasts! 2020 was quite a year. Even though it played out different for each of us, we were united in that many of our plans didn’t work out. Much has been written about missed chances, but let’s end this year on a positive note and focus on the good things. After all, that’s something the software and hardware development community have always been good at: embracing change. So let’s call 2020 an “agile year” and do a “sprint recap.” A key part of ...

2020: Nights and Weekends Projects in Review

by Matthew Ballance on Bits, Bytes, and Gates
2020 in ReviewLast year was my first year-end blog post looking back at the prior year's projects, and I thought I'd continue the (now) tradition this year. 2020 has definitely been a different year for me, and not just because of the COVID19 situation. It's been a year to take a step back and consider directions, next steps, and the tools I'll need to get there. But it's also included some

OpenTitan at One Year

by lowRISC on lowRISC: Collaborative open silicon engineering
Last year, along with our partners, lowRISC announced OpenTitan, the world’s first open source silicon root of trust. The project has progressed rapidly since then. A recent Google Security Blog post detailed key milestones met, our growth in contributors, and revealed news of the first commercial OpenTitan tapeout. OpenTitan’s success demonstrates the value of the lowRISC collaborative engineering model, wherein our full-stack engineering team allows us to serve as an essential ...

RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDA

by Steve Hoover on Blog – RISC-V International
teaser image Last month I had the great pleasure of sharing a blog post about Nicholas Sharkey, an amazing 13 year-old who participated with graduate students and professionals in an online workshop of mine and developed his own pipelined RISC-V CPU core — an amazing feat for an 8th grader!  Well, now, a month later, we just offered the workshop again and… I kinda feared when I posted about Nicholas that folks might get the wrong idea about the workshop. In fact, we had a second 12-year-old in this ...

RISC-V International Annual Awards

by Jeffrey Osier-Mixon on Announcements – RISC-V International
teaser image Each year, RISC-V International recognizes certain members of the community who have gone above and beyond in their dedication and effort with RISC-V. These are the awards for 2020. RISC-V Innovation Founders Awards In recognition of the industry impact initiated by the technical leadership and generous contribution of the founding inventors and innovators of the RISC-V ISA. ...

Stream Computing Joins RISC-V International as a Premium Member

by Kim McMahon on Announcements – RISC-V International
Silicon startup Stream Computing to join the RISC-V Board of Directors and Technical Steering Committee to advance open source AI innovation Zurich – Dec. 8, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced Stream Computing has joined RISC-V International as a Premium Member. A Stream Computing executive will join the RISC-V ...

RISC-V International Reports Another Strong Year of Growth with New Technical Milestones, Educational Programs, RISC-V Adoption and More

by Kim McMahon on Announcements – RISC-V International
RISC-V sees widespread commercial adoption across industries, from embedded to AI, from IoT to HPC and beyond Zurich – Dec. 8, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), highlighted the organization’s incredible year of growth in a keynote today by Calista Redmond, CEO of RISC-V International, at the RISC-V Summit, which is being held ...

What is Processor Core Complexity?

by Roddy Urquhart on Blog – RISC-V International
This blog was originally published on the Codasip blog.   The more complex a processor core, the larger the area and power consumption. But increasing complexity is not a single dimension as processors can be more complex in different ways. In selecting a processor IP core, it is important to choose the right sort of complexity for your project. Some ways of thinking about complexity include: Word length Execution units Privilege/protection Virtual memory Security features Generally, the ...

RISC-V Gets an Early, Minimal Android 10 Port Courtesy of PLCT Lab

by Gareth Halfacree on FOSSi – AB Open
PLCT Lab, a group working on compilers, runtimes, and emulators, has announced a milestone for its effort to port the Android Open Source project to the free and open-source RISC-V instruction set architecture: a successful minimal boot, with step-by-step instructions for trying it out yourself. With increasing interest in using the RISC-V instruction set architecture for mobile-centric devices, a major hurdle is a lack of software support. It’s long been possible to boot mainstream Linux ...

What is Needed to Support an Operating System?

by Roddy Urquhart on Blog – RISC-V International
This blog was originally published on the Codasip blog.   For each embedded product, software developers need to consider whether they need an operating system; and if so, what type of an OS. Operating systems vary considerably, from real-time operating systems with a very small memory footprint to general-purpose OSes such as Linux with a rich set of features. Choosing a proper type of operating system for your product – and consequently working out the required features of the embedded ...

A Comparison of Formal and Simulation for a Simple, Yet Non-Trivial Design - Part 1

by Tudor Timi on Verification Gentleman
teaser image I've talked a lot about constrained random verification on the blog, but now it's time to branch out to formal verification. As a fun first post on the topic, I thought we could do a comparative study. We can take a design and write two verification environments for it, one using formal verification and the other using simulation, based on UVM. Once we're done, it should be very interesting to be able to look at them side-by-side and to do an analysis.I thought long and hard about which one ...

Kactus2 website has moved

by Esko Pekkarinen on Kactus2: News
As part of the recent university merger, our previous website funbase.cs.tut.fi domain will be closed. The website have been moved to a new location at https://research.tuni.fi/system-on-chip/. The source code will continue to be hosted at https://github.com/kactus2/kactus2dev.

OTA: LimeSDR on the Traverse Ten64, LimeRFE Production Update, and More

by Gareth Halfacree on MyriadRF
Traverse Technologies has showcased the flexibility of its Ten64 eight-core Linux-based networking platform for wireless use, demonstrating its compatibility with the LimeSDR USB and GNU Radio. “There has been quite a bit of interest in using Ten64 for software-defined radio (SDR) applications,” the company explains, “so we have put together a simple demo using a LimeSDR to tune into an FM radio station and stream it to the internet.” Built as a Docker container, the project uses GNU Radio ...

Understanding the Performance of Processor IP Cores

by Roddy Urquhart on Blog – RISC-V International
This blog was originally published on the Codasip blog.   Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider performance. The first thing to think about is what aspect of performance you care about. Do you care more about the absolute throughput that you want (performance ...

SiFive Strengthens Foothold in Storage Applications for Data-Centric AI Computing

by James Prior on SiFive
teaser image SiFive RISC-V processors are powering flash drives in production as well as addressing emerging In-Storage Computing (ISC) needs In the current digital age, where data powers increasing levels of decision making, industrial control and automation, efficient data storage, movement, and processing become the focal point of technological innovations in silicon, system, and software. At SiFive, we have been designing and optimizing RISC-V based domain-specific solutions to address the ...

BBC Picks SiFive’s RISC-V-Powered HiFive Inventor for Doctor Who Coding Push

by Gareth Halfacree on FOSSi – AB Open
The BBC has announced a partnership with SiFive to bring RISC-V-powered development to kids around the world with the launch of the BBC Doctor Who HiFive Inventor educational development board and supporting coursework bundle. Announced late last year, the SiFive Learn Inventor is a hand-shaped educational development board inspired by the popular BBC micro:bit but powered by SiFive’s Freedom E310 processor – itself driven by the free and open-source RISC-V instruction set architecture ...

RPC DRAM support in open source DRAM controller

by Antmicro on Blog – RISC-V International
teaser image Original content published October 28, 2020 on the Antmicro blog. The Internet of Things is one of the areas that is hugely benefiting from miniaturization of semiconductor technologies, as more computing power can be encapsulated into increasingly smaller devices. Shrinking in size and requiring less power, various devices – including AI-capable ones – are applied in ways that were not possible a few years ago. One of the new and exciting developments in this space is the emergence of RPC ...

13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core

by Steve Hoover on Blog – RISC-V International
teaser image One of my great pleasures operating my EDA startup, Redwood EDA, is working with enthusiastic college students and open-source developers and seeing how our technology is renewing excitement for logic design. Recently, Kunal Ghosh of VLSI System Design and I conducted our third “Microprocessor for You in Thirty Hours” (MYTH) Workshop, where participants learn about RISC-V and build their own RISC-V CPU cores (something that’s typically done over the course of a semester or two). In addition ...

PicoRio: the Raspberry Pi-like Small-Board Computer for RISC-V

by RISC-V International Open Source Laboratory Tsinghua-Berkeley Shenzhen Institute on Blog – RISC-V International
teaser image By Zhangxi Tan, Lin Zhang, Yi Li, and David Patterson of the RISC-V International Open Source Laboratory Tsinghua-Berkeley Shenzhen Institute RISC-V, the royalty-free open-source alternative to proprietary instruction sets, is growing globally in popularity.  This has led to many free and open-source processor designs, a free and open software stack and an international organization that maintains and promotes the instruction set. However, while key pieces of an open-source ecosystem for ...

Open Source Digital Library in HPC

by John Davis on Blog – RISC-V International
teaser image This post was originally published on the MEEP (MareNostrum Exascale Emulation Platform) website. John Davis, MEEP project coordinator, explains how the European project MEEP will develop an open source digital library for the RISC-V ecosystem in HPC, its hardware and software developments and a performance modeling tool called Coyote. MEEP is a digital laboratory that enables us to build hardware that does not yet exist to test ideas on Hardware. It will be fast enough to enable software ...

El Correo Libre Issue 33

by Gareth Halfacree on LibreCores - Medium
teaser image Matt Guthaus Showcases OpenRAM on SkyWater’s 130nm Process in FOSSi Dial-UpProfessor Matt Guthaus has offered an overview of OpenRAM, an open-source Python framework designed to handle the integration of static RAM (SRAM) into application-specific integrated circuit (ASIC) design, as part of the ongoing FOSSi Dial-Up video series. “I’ve been working on OpenRAM for actually quite a few years now,” Matt explained by way of introduction in the live video presentation, “and it’s turning into a ...

PolarFire SoC and RISC-V

by Antmicro on Blog – RISC-V International
teaser image Hitting the market as the world’s first mass-produced, Linux-capable RISC-V implementation, PolarFire SoC FPGA turned heads among designers of computer systems who work with open processor architectures. This low-power, 4+1 core FPGA family with 23-461K logic elements from Microchip is becoming a major prototyping, research and experimentation platform for RISC-V-based solutions, allowing system designers to leverage its FPGA resources and the ability to run a plethora of Linux-based apps ...

Third Workshop on RISC-V Activities – It’s the ecosystem!

by RISC-V Community News on Blog – RISC-V International
On Thursday October 8, the third Workshop on RISC-V Activities was hosted by edacentrum, due to the pandemic situation as an online workshop. First of all I have to say that with more than 230 registrations the workshop was very well attended. On the other hand, this comes not as a real surprise, since RISC-V is getting a lot of attention lately. Calista Redmond, RISC-V International CEO reported a tremendous 62% growth to now more than 750 RISC-V members across 50 countries – wow! What is ...

Fixing the ESD generator

by Fatsie on Chips4Makers.io
teaser image This is a continuation on my previous blog on first tests on the ESD generator. Problems After some more debugging the voltage multiplier of the ESD Generator has been made to work. Detailed simulation results of the problems can be found in this Jupyter notebook in the created sim folder in the ESD Generator source folder. Summary of the problems: Leakage problem reported on in the previous blog post is mainly caused by the 10MΩ input impedance on the oscilloscope input not the diode ...

OTA: New srsLTE, Lime Suite, LuaRadio, GQRX, SDR#, and More

by Gareth Halfacree on MyriadRF
The open-source srsLTE cellular communications suite has hit version 20.10, bringing new functionality including mobility functions and performance-enhancing PHY changes – and a range of bug-fixes, too. The srsLTE 20.10 release brings with it a new logging framework alongside initial NR PHY layer and stack components. The srsENB package receives Mobility – Intra eNB and S1 – functionality and RRC Re-establishment functionality, too, while the UE PHY layer is non-blocking and PHY ...

The Heart of RISC-V Development is Unmatched

by James Prior on SiFive
teaser image Creating a RISC-V PC Ecosystem for Linux application development Today, SiFive introduces the new HiFive platform for professional RISC-V developers, the HiFive Unmatched! The HiFive Unmatched enables developers to create the RISC-V-based software they need for RISC-V platforms. From real-time operating systems to custom Linux distributions, and the compilers, libraries, and applications that go with product design, developers can use the HiFive Unmatched to natively test and build RISC-V ...

SiFive VIU75 Accelerates Vector Math

by Abhishek Jadhav on FOSSi – AB Open
teaser image At the Linley Fall Conference 2020, SiFive Chief Architect and co-founder Krste Asanovic announced the RISC-V based VIU7 series. In that, the VIU75 CPU core is 64-bit, runs Linux, and supports “RV vector extension”. When it comes to RISC-V based core IP, SiFive has always dominated with new CPU IP with a huge portfolio. The RISC-V core VIU75 comes from the VI7 series and U cores. The VI7 series has a high-performance, 8-stage dual-issue in-order pipeline with an integrated vector unit, ...

RISC-V International Announces Agenda for the Third Annual RISC-V Summit

by Kim McMahon on Announcements – RISC-V International
The leading RISC-V conference will be held virtually this year, featuring keynotes, tutorials, exhibitions, networking opportunities and more WHAT: The RISC-V International Association has announced the online program for the RISC-V Summit 2020. WHEN: Tuesday, Dec. 8 to Thursday, Dec. 10, 2020. WHERE: Register online here. DETAILS: RISC-V International will hold its third annual RISC-V Summit online from Dec. 8-10, 2020. The RISC-V Summit brings together innovators, academics and business ...

A birthday present for lowRISC: We won an OpenUK Award!

by lowRISC on lowRISC: Collaborative open silicon engineering
teaser image On October 20th, lowRISC CIC won in the Open Hardware category at the 2020 OpenUK Awards, describing lowRISC as “the jewel in the crown of the UK’s open silicon companies”. The OpenUK awards promote “UK Leadership in Open Technology”, and are given out by OpenUK, a UK-based not-for-profit company which supports open source collaboration and open technologies within the United Kingdom. On receiving the award, lowRISC CTO, Alex Bradbury, said “We’re incredibly grateful to have been ...

The SiFive 20G1 Update for 7-Series Core IP

by Drew Barbier on SiFive
Faster, More Efficient SiFive 7-Series Core IP Today, we’re announcing the SiFive 20G1 6.0 update, which is focused on improving the 7-Series line of products. Our previous release, SiFive 20G1, was a comprehensive update that spanned from the 7-Series to the 2-Series, including U-, S-, and E-Cores. Similarly, the 20G1 6.0 update improves the performance, features, and functionality of SiFive 7-Series U-, S-, and E-Cores. Ever since the 7-Series introduction in 2018, SiFive has been able to ...

El Correo Libre Issue 32

by Gareth Halfacree on LibreCores - Medium
teaser image Antmicro Integrates Embench for Quick Core-to-Core Performance ComparisonsFree and open source silicon pioneer Antmicro has published a series of benchmark results designed to pit a selection of cores head-to-head in real-world workloads, using the Embench benchmark suite maintained by the FOSSi Foundation. “Embench, maintained by the FOSSi Foundation we proudly participate in, is an open source embedded benchmark test suite which aims to respond to the needs of modern embedded systems,” ...

How we used differential testing to rapidly find and fix missed optimisation opportunities in LLVM's RISC-V backend

by Luís Marques on lowRISC: Collaborative open silicon engineering
At this October 2020 LLVM Developers’ Meeting I presented a poster about how, with a surprisingly simple tool, we were able to rapidly identify, isolate, and fix a range of missed optimisation opportunities in LLVM’s RISC-V backend. The tool works by generating random C programs, compiling each program with both Clang and GCC (targeting RISC-V) and comparing the assembly generated by both compilers. If it estimates that Clang/LLVM generated worse code than GCC then it saves that case ...

First testing of and changes to ESD generator

by Fatsie on Chips4Makers.io
teaser image As reported in a previous blog post I am working on a small circuit to generate high voltages for some ESD testing. I now received the PCBs and the components for on the PCB and even did find some time to do the first testing of the design. As a reminder this is the schematic of the ESD generator: To do the first testing I just populated the transformator, the diode bridge and components C1, C13, D5 and D17. This can be seen in the next picture: It should allow to test if a voltage of ...

SHAKTI Announces Third Silicon Success with the Arduino-Compatible Moushik

by Gareth Halfacree on FOSSi – AB Open
The SHAKTI free and open source silicon project has reached another milestone with the boot up of the Moushik, an Arduino-compatible system-on-chip (SoC) and the group’s third successful silicon tape-out. The SHAKTI project first announced its success in booting Linux on a home-grown RISC-V based processor back in 2018, initially on a chip built by US semiconductor giant Intel on a 22nm process, then on a chip built natively in India on a 180nm node at the ISRO Semiconductor Laboratory in ...

OTA: High School RADAR, GSM Base Station on DragonOS, FM on the ISS, and More

by Gareth Halfacree on MyriadRF
Parkland High School student Victor Cai has presented work on a proof-of-concept short-range RADAR system, built around a LimeSDR Mini, at the GNU Radio Conference 2020 (GRCon20). Victor’s experimental system, presented with supporting paper during the virtual GRCon20 event, combines an off-the-shelf laptop running GNU Radio with a LimeSDR Mini software defined radio, a mixture of commercial and home-made antennas, and a simple experimental setup to prove that often-dismissed ...

The Incredible Opportunity For SiFive

by Patrick Little on SiFive
A note from SiFive President & CEO, Patrick Little I’m honored to join SiFive to lead the brilliant, hard-working team of innovators and engineers who are responsible for creating some of the most impactful architectures in the technology industry. Ten years ago, an inspired team of computer scientists set out to invent a better way for hardware and software to talk to each other, free of legacy overhead and unencumbered by complexity, bringing the RISC-V Instruction Set Architecture to ...

IBM Contributes Open-Source A2O POWER Core, Open-CE to the OpenPOWER Foundation

by Gareth Halfacree on FOSSi – AB Open
The OpenPOWER Foundation has announced two more IBM projects which have been moved to an open-source licence, following on the heels of opening the POWER instruction set architecture (ISA) itself. Announced this week at the OpenPOWER Summit 2020, IBM is contributing a the A2O out-of-order processor core with supporting FPGA environment and a deep-learning-focused project it calls the Open Cognitive Environment (Open-CE), aiming to improve accessibility of existing frameworks. “I’m excited ...

SiFive Announces FU740-Based RISC-V PC, Plans to Grow the RISC-V Ecosystem

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneer SiFive has announced its intention to encourage growth of the RISC-V developer ecosystem with the release of a ready-to-run off-the-shelf RISC-V-powered personal computer built on its FU740 processor – offering a turnkey alternative to the current raft of do-it-yourself options. The free and open-source RISC-V instruction set architecture (ISA) and the ecosystem which surrounds it is gathering momentum on a daily basis. From hobbyists and academics experimenting through to ...

Reverse-engineering the first FPGA chip, the XC2064

by DP on FPGA – Dangerous Prototypes
teaser image Ken has written an article on reverse engineering the first FPGA chip, the XC2064: The FPGA was invented by Ross Freeman1 who co-founded Xilinx2 in 1984 and introduced the first FPGA, the XC2064. 3 This FPGA is much simpler than modern FPGAs—it contains just 64 logic blocks, compared to thousands or millions in modern FPGAs—but it led to the current multi-billion-dollar FPGA industry. Because of its importance, the XC2064 is in the Chip Hall of Fame. I reverse-engineered Xilinx’s ...

GSoC Projects Successfully Completed

by Pirmin Vogel, Sam Elliott, and Greg Chadwick on lowRISC: Collaborative open silicon engineering
Time is ticking and summer is almost over already. With that, also our this years’ Google Summer of Code (GSoC) projects are coming to an end. A lot of open-source coding has been done, pull requests have been made, reviewed and merged. Experiments have been conducted, results were gathered, interpreted and presented. Bugs were found and fixed, and the resulting designs further improved. Both our students and mentors have been working hard and we are pleased to announce that both our two ...

El Correo Libre Issue 31

by Gareth Halfacree on LibreCores - Medium
teaser image FOSSi Dial-Up is a BlockbusterFOSSi Dial-Up has been running for three episodes now and it was a great joy and success. In this edition of ECL I want to quickly recap what has happened so far and where you can binge the previous three episode.In our kick-off Tim Ansell as the project lead of the Skywater open source PDK gave an overview of the project. The PDK is a major missing link in an open source silicon design flow, and this project is a thrilling milestone. If that was not enough for ...

RISC-V Vector Extension Intrinsic Support

by Chris Lattner on SiFive
The RISC-V Vector extension (RVV) enables processor cores based on the RISC-V instruction set architecture to process data arrays, alongside traditional scalar operations to accelerate the computation of single instruction streams on large data sets. The RISC-V International vector working group is composed of experts from industry and academia, to create a standard extension that can be ratified for general adoption among any who choose to adopt RVV. We’re incredibly pleased to announce ...

Randomness is Secure with SiFive Shield HCA

by James Prior on SiFive
Building a secure foundation using the concept of randomness seems, on the surface, counter-intuitive. As an aspect of entropy, randomness enables the generation of cryptographic methods to protect data, chips, and systems. By harnessing the nature of randomness as the basis of a secure system, it is possible to enhance the security of computer systems and protect vital information. In July, SiFive introduced the SiFive Shield hardware cryptographic accelerator (HCA), as part of the ...

Lattice Semiconductor Embraces Open Hardware, Launches “Community Sourced” Portal

by Gareth Halfacree on FOSSi – AB Open
Field-programmable gate array (FPGA) expert Lattice Semiconductor has embraced the ethos of the open hardware community, creating a portal which lists what the company describes as “community sourced” open hardware development boards and reference designs. “In addition to proprietary boards developed by Lattice and other partners there is a broad array of boards developed by the open source community,” Lattice notes on its freshly-launched portal. “In some cases just the designs are ...

OTA: New Lime Suite Release, 16km Barefoot TV Transmissions, and More

by Gareth Halfacree on MyriadRF
Lime Suite v20.07.1 has officially launched, bringing a range of improvements to the LimeSDR-focused software bundle – including a fix for a bug which was causing quick tests of LimeSDR Mini boards to fail. In its latest release, Lime Suite v20.07.1 repairs a recently-discovered bug which would manifest as intermittent failures when running the LimeQuickTest utility on LimeSDR Mini boards. While these failures would appear to suggest that the boards were themselves faulty, the cause was ...

OpenFive's Customizable Silicon-Focused Solutions

by Shafy Eltoukhy on SiFive
teaser image OpenFive is a solution-centric and processor agnostic custom silicon business unit dedicated to building optimized domain-specific SoCs Today, I am excited to announce the launch of OpenFive, a self-contained and autonomous custom silicon business unit of SiFive, Inc. OpenFive is solution-centric and uniquely positioned to design processor agnostic SoCs and deliver high-quality silicon. The demand for domain-specific silicon and workload-focused architecture is driven by several key ...

El Correo Libre Issue 30

by Gareth Halfacree on LibreCores - Medium
teaser image Brian Bailey: Open Source Verification “Leaves the Door Open to New Approaches”Brian Bailey, technology editor for electronic design automation (EDA) at Semiconductor Engineering, has penned a piece looking into exactly what is meant by “open-source verification” — and how it can leave the door open to novel approaches not previously considered by the industry. “Ask different people what open-source verification means and you will get a host of different answers,” Brian explains. “They ...

DIN SPEC 3105, Published Under an Open Licence, “Writes a New Chapter” for Open Hardware

by Gareth Halfacree on FOSSi – AB Open
The German Institute for Standardisation (Deutsches Institut für Normung, DIN) has published a formal specification, DIN SPEC 3105, for open source hardware documentation – and the specification itself is open, and the first to be published under a Creative Commons licence. Released as part of a pilot program which sees DIN working alongside open-source and open-hardware communities, DIN SPEC 3105 details requirements for technical documentation in open-source hardware projects. “The pilot ...

Lime Suite 20.07.1 Released

by Andrew Back on MyriadRF
A new release of the Lime Suite software, which provides drivers, utilities and APIs for the LimeSDR family of boards, has been made. The v20.07.1 release includes a number of improvements to the Lime Suite library, with perhaps the most notable being a configuration change for LimeSDR Mini boards, which addresses issues including intermittent failures when running LimeQuickTest. As such all LimeSDR Mini owners are strongly urged to upgrade. Other improvements include various fixes to the ...

EDeA Project Aims to Make Sharing, Using KiCad “Subcircuits” as Easy as Possible

by Gareth Halfacree on FOSSi – AB Open
KiCad users may soon be able to easily share, download, and assemble subcircuits into open-hardware projects thanks to a new initiative dubbed EdeA. “There is a growing Open Hardware movement, a diverse bunch of people with intimidating skill levels, and they are reimplementing the wheel over and over,” explains pseudonymous co-founder ln of the project. “What if it were easy to share those tricks, to reuse what we already made, tested, so we can build better, cheaper, or achieve more? What ...

RISC-V Global Forum: Technology. Opportunity. Community.

by Kim McMahon on Announcements – RISC-V International
teaser image The schedule for RISC-V Global Forum is live! We have an exciting lineup of keynotes, session presentations, lightning talks, ask the experts, sponsor exhibits, and networking opportunities. Below you can find all the exciting information about how to interact in our Global Forum digital experience. Connected worldwide This event is fully virtual, bringing together a worldwide audience with 18 hours of content that includes three keynote blocks, concurrent sessions, and exhibit ...

OTA: Hijacking Hostile Drones, LiFi Dev Kits, Custom LimeSDR Chassis and More

by Gareth Halfacree on MyriadRF
Vilnius Gediminas Technical University student Ugnius Buržinskis has released a video demonstrating a drone hijacking system, designed to prevent unauthorised uncrewed aerial vehicles (UAVs) from entering a restricted area, powered by a LimeSDR Mini. Using the LimeSDR Mini, housed in a protective casing and connected to an off-the-shelf laptop running software based on the SoapySDR application programming interface (API), the system is designed to wrest control of an unauthorised drone ...

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Last updated 22 January 2021 02:00 UTC