Planet LibreCores

The Rapid Rise of RISC‑V

by Jack Kang on SiFive 14 January 2022 17:00 UTC

SiFive is aiming high with bold new technology for performance-driven applications SiFive transformed in 2021 and grew from leading RISC-V for embedded products into performance-demanding markets, creating real choice in the semiconductor processor IP market. Now, the SiFive portfolio features three distinct, market-focused product families, based on market requirements ranging from high-performance applications, machine learning and artificial intelligence processing, to embedded real-time ...

RISC-V RV32I S-Type | Maven Silicon

by Maven Silicon on Blog – RISC-V International 12 January 2022 14:36 UTC

This video explains the RV32I S-Type instructions.  RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. C-V RV32I S-Type | Maven Silicon The post RISC-V RV32I S-Type | Maven Silicon appeared first on RISC-V International.

El Correo Libre Issue 46

by Gareth Halfacree on LibreCores - Medium 11 January 2022 09:10 UTC

Incredible Hack Implements a CPU in a Modular Analogue SynthBuilding a CPU out of discrete digital logic is a right-of-passage for many in the world of free and open source silicon and open hardware, but engineer Kate F. has gone a step further — building a functional CPU using an analogue modular synth. “I’m using VCV Rack. It’s software simulation for Eurorack modular synthesisers, either in conjunction with, or in place of hardware modules,” Kate explains of the project. “You know the ...

Edalize 0.3.0

by Olof Kindgren on Tales from Beyond the Register Map 07 January 2022 14:30 UTC

 Looks like it's time for a new Edalize release. During this development cycle, most of the work has been done under the hood with creating a new internal architecture and refactoring many of the backends. Most of those efforts will bear fruit longer term, but we can already today see the initial work on the flow API, that has been planned for at least two years. We also welcome a new backend for Lattice Nexus devices and some miscellaneous feature additions and bug fixes. Read on for the ...

Edge AI on Low-Footprint RISC-V | Alexander Stanitzki, Fraunhofer IMS

by RISC-V Community News on Blog – RISC-V International 04 January 2022 15:00 UTC

The integration of AI algorithms on end devices (“Edge AI”, “AI of Things”, TinyML,..)  is conquering the domain of resource constrained microcontrollers and cost-efficient ASIC designs. AI can improve the performance of basic sensors, helps to achieve light-weight object recognition and tracking in optical detectors and can be useful for HMI functions such as handwriting recognition. RISC-V makes it possible to quickly develop new hardware architectures to support these applications even ...

OTA: LimeSDR’s Part in the UK’s Open RAN Plans, an Open-Source ARDF Controller, a “Widowmaker” Radio, and More

by Gareth Halfacree on MyriadRF 31 December 2021 11:00 UTC

The UK government has announced a target of carrying 35 per cent of all cellular traffic over open radio access networks (open RANs) by 2030, alongside the planned retirement of 2G and 3G cellular – and LimeSDR technology has been selected for two key test-bed projects. “The mobile network operators have confirmed that they do not intend to offer 2G and 3G mobile networks past 2033 at the latest,” the Department for Digital, Culture, Media, and Sport (DCMS) said in a statement on the ...

When You Reach The Summit, Keep Climbing

by Andy Frame on SiFive 10 December 2021 20:00 UTC

The RISC-V Summit 2021 highlighted to the world that the future of RISC-V has no limits! 2021 has been an outstanding year for SiFive, and the biggest in its history, starting with the introduction of the AI/ML focused SiFive Intelligence™ and high performance SiFive Performance™ series of processors and culminating with the announcement of the SiFive Performance P650 and latest SiFive 21G3 release as part of the RISC-V Summit 2021. Specifications In parallel, RISC-V International has ...

El Correo Libre Issue 45

by Gareth Halfacree on LibreCores - Medium 14 December 2021 09:42 UTC

Test Bench Environment cocotb Gets Bug-Fix 1.6.1 ReleaseOctober’s release of cocotb 1.6.0, the at-the-time latest version of the popular coroutine-based cosimulation test bench environment for VHDL and Verilog RTL, brought with it a wealth of improvements and new features — and one annoying regression bug, which has now been resolved in version 1.6.1. Released earlier this month, cocotb 1.6.1 has all the same features as 1.6.0 — including the new C-to-Python PYGPI_ENTRY_POINT, the ...

Our New Partnership with Rambus and the DesignShare Economy

by Jack Kang on SiFive 15 October 2018 23:40 UTC

As we continue to expand our product offerings to better serve the rapidly growing RISC-V and SiFive community, we are always looking to work with companies (big and small) who share our vision. On Monday, we proudly announced that we will form a new partnership with Rambus, a leader in the digital security, semiconductor and IP industries, to help us take the next step in democratizing access to custom silicon. Through the partnership, we will be able to offer Rambus’ cryptography ...

All Aboard, Part 4: The RISC-V Code Models

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

The RISC-V ISA was designed to be both simple and modular. In order to achieve these design goals, RISC-V minimizes one of the largest costs in implementing complex ISAs: addressing modes. Addressing modes are expensive both in small designs (due to decode cost) and large designs (due to implicit dependencies). RISC-V only has three addressing modes: PC-relative, via the auipc, jal and br* instructions. Register-offset, via the jalr, addi and all memory instructions. Absolute, via the lui ...

Interrupts on the SiFive E2 Series

by Drew Barbier on SiFive 15 October 2018 23:40 UTC

Last week SiFive launched the new E2 Series RISC-V Core IP. The E2 Series represents SiFive’s smallest, most efficient Core IP Series and is targeted specifically for embedded microcontroller designs. One of the reasons it is great for microcontroller applications is because of its extremely small area footprint, just 0.023mm2 in 28nm for the entire E20 Standard Core! Another reason it's great for the embedded market is its configurability. The E2 Series can be configured even smaller than ...

The DesignShare Ecosystem Expands Its Catalog of IP to include eMemory’s Logic NVM

by Jack Kang on SiFive 15 October 2018 23:40 UTC

It’s been a fantastic few months for us with new initiatives and industry recognitions, and we’re excited to share more great news. Earlier this month, we welcomed eMemory, the IP provider of logic-based, non-volatile memory (Logic NVM), as the latest company to join the DesignShare movement! If you missed our previous blog post, DesignShare is a concept that opens a new range of applications and gives any company, inventor or maker the ability to harness the power of custom silicon. The ...

What’s new in AI & ML from SiFive

by Patrick Little on SiFive 23 April 2021 16:00 UTC

Introducing the SiFive Intelligence X280 This week has been an exciting one for our team at SiFive, with a number of key announcements that are beginning to allow us to publicly share our strategy for the exponentially growing AI/ML market. While we are only scratching the surface of the impact AI/ML will have on our industry and our lives, it’s clear that the workloads, algorithms, and requirements are going to be constantly evolving and improving for the foreseeable future. These changing ...

Dover Microsystems Brings Real-Time Chip Security to SiFive’s DesignShare

by Shafy Eltoukhy on SiFive 15 October 2018 23:40 UTC

Boy have we been busy. Over the last few months, our DesignShare ecosystem has continued to expand, and, this week, we were excited to welcome Dover Microsystems into the program. Through DesignShare, developers now have access to Dover Microsystems’ CoreGuard Silicon IP, which enables processors to defend themselves in real-time from all network-based attacks. CoreGuard prevents illegal instructions from executing before any damage can be done. Its security rules define the difference ...

Intel Capital Investment Boosts Vision for the Future

by Naveed Sherwani on SiFive 15 October 2018 23:40 UTC

We’re very happy to announce that Intel Capital participated in our recent Series C funding round. The investment was revealed at the Intel Capital Global Summit earlier today. Now, you may be thinking, “$50.6 million provides immense potential for SiFive – so now what?” For those of you who aren’t familiar with what SiFive is all about, we aim to leverage the body of software and tools available from the open-source community under the guidance of the RISC-V Foundation with the intention ...

All Aboard, Part 11: RISC-V Hackathon, Presented by SiFive

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

Date: Monday, March 12 – Wednesday, March 14 Time: 10:30am Monday – 1:00pm Wednesday Location: Embedded Linux Conference, Hilton Portland Downtown, Skyline II, Floor 23 UPDATE 2 (3/7/2018) We’ve doubled the cash prize to $2,000 for each challenge! Plus we’ve added a “coolest demo” category, with the same prize package as the other challenges (a HiFive Unleashed board plus the $2,000). You can register for the Hackathon here. UPDATE (3/7/2018) We've seen a lot of interest in the RISC-V ...

Last Week in RISC-V: Sept 7, 2018

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

This is the last version of "Last Week in RISC-V" that I plan on sending to the various mailing lists, as we'll be posting the rest of them on SiFive's Blog. I didn't get any contributions, but I also haven't gotten through my email yet -- sorry if I missed anything that's been sent it, but I'm not too far behind so I should have everything read from this week by the end of next week. Linux 4.19-rc3 On Tuesday I tagged my pull request for Linux 4.19-rc3, which contains what I hope to be ...

The DesignShare Ecosystem Grows with the Addition of UltraSoC’s Embedded Analytics IP

by Jack Kang on SiFive 15 October 2018 23:40 UTC

It’s been a busy summer for us. Our days have been filled with many prospect, customer and partner meetings with teams looking to leverage RISC-V in their roadmap. Last week, we announced the outcome of one of those meetings: UltraSoC, a provider of on-chip monitoring and analytics IP, is the latest company to join the DesignShare movement. If you missed our previous blog post, 'Our New Partnership with Rambus and the DesignShare Economy,' Designshare is a concept that enables an entirely ...

Analog Bits Clocks into the DesignShare Ecosystem

by Jack Kang on SiFive 15 October 2018 23:40 UTC

Our DesignShare family is growing, and we’re thrilled to announce that Analog Bits, the industry’s leading provider of low-power mixed-signal IP solutions, is now a part of the ecosystem. System designers will have access to Analog Bits’ precision clocking macros such as PLLs and SERDES IP available for the SiFive Freedom platforms through DesignShare. Analog Bits has become an important supplier of differentiated IP embedded in SoC devices and has been instrumental in spawning the mobile ...

A Core By Any Other Name...

by Jack Kang on SiFive 15 October 2018 23:40 UTC

With all apologies to Shakespeare, would a core by any other name still hit the sweet spot in the market for those looking for cost-effective custom silicon? Based on feedback from some friendly chaps in the industry, today we are announcing a new naming scheme for our products. We’ve updated our product names to reflect that we build and provide IP for RISC-V cores--and not any other ISA. To ease the transition, we’ve kept part numbers – like the U54-MC unveiled last week at the Linley ...

All Aboard, Part 9: Paging and the MMU in the RISC-V Linux Kernel

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

This entry will cover the RISC-V port of Linux's memory management subsystem. Since the vast majority of the memory management code in Linux is architecture-independent, the vast majority of our memory management code handles interfacing with our MMU, defining our page table format, and interfacing with drivers that have memory allocation constraints. I will refrain from discussing the RISC-V memory model in this blog, both because it isn't yet finished and because it's complicated ...

A Look Back: 7th RISC-V Workshop

by Allen Leibovitch on SiFive 15 October 2018 23:40 UTC

A new year brings new opportunities. Before we dive into 2018, we wanted to take some time to reflect on some of the excitement we experienced over the last couple of months. At the 7th RISC-V Workshop, we had the honor of partnering with some of the industry’s leading companies and announced the following at the workshop: An extended partnership with Microsemi: Microsemi and SiFive formed a strategic partnership to create and market a development board based on SiFive’s RISC-V based ...

Last Week in RISC-V: Sept 28, 2018

by Palmer Dabbelt on SiFive 19 October 2018 20:37 UTC

I spent too much time writing my single entry this week so it's all I have. The issue itself is somewhat complex, so I thought it warranted a deep dive. Relaxing R_RISCV_PCREL_* in the Presence of Addends Jim recently found an issue with our ELF relocation scheme. While technically it's a somewhat wide-ranging ABI bug, the actual set of cases in which the issue will manifest is somewhat restricted -- in other words: while I'm sure the proper long-term fix for this will be quite involved, ...

All Aboard, Part 3: Linker Relaxation in the RISC-V Toolchain

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

Last week's blog entry discussed relocations and how they apply to the RISC-V toolchain. This week we'll be delving a bit deeper into the RISC-V linker to discuss linker relaxation, a concept so important it has greatly shaped the design of the RISC-V ISA. Linker relaxation is a mechanism for optimizing programs at link-time, as opposed to traditional program optimization which happens at compile-time. This blog will follow an example linker relaxation through the toolchain, demonstrate an ...

Last Week in RISC-V: Sept 14, 2018

by Palmer Dabbelt on SiFive 19 October 2018 20:36 UTC

GNU Tools Cauldron Trip Report, Part 2 I was at the GNU tools cauldron last week. I summarized the two BoF sessions in last week's entry. While that was the extent of the RISC-V specific events at the cauldron, I attended the remainder of the cauldron where there were some great sessions. Vector ABI I attended the aarch64 BoF session, where one of the major issues at hand is to implement a system ABI that allows argument passing via SVE registers. This brought up a mirror in RISC-V land: ...

Introducing the U54-MC RISC-V Core IP – The First RISC-V Core with Linux Support

by Jack Kang on SiFive 15 October 2018 23:40 UTC

Since we launched the industry’s first open-source RISC-V SoC back in July of last year, we’ve had the pleasure of pushing the boundaries of the RISC-V ecosystem and have been delighted by the support that SiFive – and RISC-V – has gained from system designers and Makers alike. Today, we are proud to announce we have taken the next step in our journey to deliver custom silicon to everyone who needs it. Introducing the U54-MC RISC-V Core IP, the industry’s first RISC-V based, 64-bit, ...

All Aboard, Part 6: Booting a RISC-V Linux Kernel

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

This post begins a short detour into Linux land, during which we'll be discussing the RISC-V Linux kernel port. SiFive has recently announced the Linux-capable U54-MC RISC-V Core IP, and our Linux port was recently submitted to linux-next, Linux's staging branch, so assuming that everything goes smoothly we should be merged at the end of the next merge window. Along with Linux we should soon have the full suite of core system components upstream, both for embedded systems (via binutils, ...

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part II

by Camille Kokozaki on SiFive 14 May 2019 23:06 UTC

During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded Processors, and E Cores 32-bit Embedded Processors. Embedded intelligence allows mixing of application cores with embedded cores, extensible custom instructions, ...

All Aboard, Part 5: Per-march and per-mabi Library Paths on RISC-V Systems

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

A previous blog described how the -march and -mabi command-line arguments to GCC can be used to control code generation for the sources you compile as a user, but most programs require linking against system libraries in order to function correctly. Since users generally don't want to compile every library along with their program, either because they're too complicated or because they're meant to be shared, a mechanism is needed for linking against the correct set of system libraries to ...

RISC-V Founding Member, Syntacore, Upgrades to Premier Level Membership

by Kim McMahon on Announcements – RISC-V International 07 December 2021 16:51 UTC

ZURICH – Dec. 7, 2021 – RISC-V International, a global open hardware standards organization, today announced that Syntacore, a semiconductor IP company specializing in customizable microprocessor cores and tools based on the RISC-V instruction set, has upgraded to the Premier membership level. At this Premier level, Alexander Redkin, CEO and co-founder at Syntacore, will join the RISC-V Board of Directors. A founding member of RISC-V International, Syntacore focuses solely on the RISC-V ISA ...

RISC-V Celebrates Incredible Year of Growth and Progress, Ratifying Multiple Technical Specifications, Launching New Education Programs, and Accelerating Broad Industry Adoption

by Kim McMahon on Announcements – RISC-V International 06 December 2021 17:00 UTC

With billions of chips in the market, RISC-V has seen widespread commercial adoption across industries and implementations, from embedded automotive to hyperscale AI, from 5G to HPC and beyond. Zurich – Dec. 6, 2021 – RISC-V International, a global open hardware standards organization, is bringing the open hardware community together to network, learn, celebrate, and fuel the open era of microprocessor design at the RISC-V Summit, which is being held virtually and in-person in San Francisco ...

Next generation music AI engine available for RISC-V

by Kim McMahon on Blog – RISC-V International 06 December 2021 16:30 UTC

Vancouver based software studio Cartesian Theatre Corp. and SiFive, Inc., the founder and leader in RISC-V computing, are excited to announce CT’s Helios music recommendation engine’s successful port to the open and free RISC-V instruction set architecture. Helios is an advanced patent-protected AI music recommendation engine that can be used to search commercial music catalogues using music itself as the search key. Applications are wide ranging, such as production studios seeking ...

Ventana Micro Systems Inc. Joins RISC-V International’s Board of Directors

by Kim McMahon on Announcements – RISC-V International 06 December 2021 16:00 UTC

Ventana will continue to contribute and accelerate technical progress and market adoption of RISC-V ZURICH – Dec. 6, 2021 – RISC-V International, a global open hardware standards organization, today announced that Ventana Micro Systems Inc., a company developing high-performance data center class RISC-V processors that was recently named by CRN as one of the 10 hottest semiconductor startups, has upgraded to the Premier membership level. With its upgraded membership, Ventana’s founder and ...

RISC-V International Ratifies 15 New Specifications, Opening Up New Possibilities for RISC-V Designs

by Kim McMahon on Announcements – RISC-V International 02 December 2021 13:00 UTC

New Vector, Scalar Cryptography and Hypervisor specifications will help accelerate the adoption of RISC-V across a variety of market segments.   ZURICH – Dec. 2, 2021 – RISC-V International, a global open hardware standards organization, today announced that RISC-V members have ratified 15 new specifications – representing more than 40 extensions – for the free and open RISC-V instruction set architecture (ISA). Most notably, RISC-V members ratified the Vector, Scalar Cryptography, and ...

Retro-µC 2021 Test Tape-out

by Fatsie on Chips4Makers.io 27 November 2021 23:00 UTC

I found some time to work on the Retro micro-controller again and perform a test tape-out in TSMC 0.35um technology. I was also contacted by Matt Venn for an interview. We agreed to also discuss this tape-out during the interview. This relieved me from the (in my eyes) boring task of writing an extensive blog post on it. The interview is published on Matt Venn's Zero To ASIC Course YouTube channel. Just wanted to do a little additional expectation management. Due to the current chip squeeze ...

OTA: Delivery Updates, LimeSDR on a Phone, a New CubeSat, LoRa Moonbounce and More

by Gareth Halfacree on MyriadRF 26 November 2021 06:27 UTC

Lime Micro products, including the LimeSDR family, are still being impacted by global component shortages and supply chain disruption – but Lime’s Ebrahim Bushehri has detailed how the company is working to overcome the issues. “While we’ve placed our orders and hope the supply chain settles down soon, we’re not betting on it and are actively pursuing other avenues to resuming production,” Ebrahim explains. “For example, there is some hope of synthesizing a PLL in an FPGA and sourcing FPGAs ...

Accelerating the Future of RISC-V

by Rohit Kumar on SiFive 19 November 2021 17:00 UTC

The freedom of RISC-V enables a bright future for SiFive What a time to be in the Semiconductors and CPU industry! As an industry, we are experiencing a perfect storm. With the rise of machine learning, cloud computing, and autonomous driving; the need for advancement in computing has never been greater. This is happening at a time when Moore’s law has considerably slowed and dennard scaling has come to an end. Architectural innovation is required to break out of the current logjam, but the ...

See Western Digital’s SweRV Core family at the 2021 RISC-V Summit

by Ted Marena on Blog – RISC-V International 18 November 2021 20:08 UTC

RISC-V has been a very popular choice for embedded processor designs. Western Digital’s existing SweRV Core family is among the highest performance, area optimized embedded RISC-V Cores available today. The openness of RISC-V enabled the SweRV Core EH2 to offer dual threaded capability. It was the first commercial RISC-V core and it has notched an impressive CoreMarks/Mhz score of 7.8 in dual threaded mode. At the RISC-V Summit on Dec 8, 2021 at 11am Zvonimir Bandic will unveil the new ...

RISC-V is Inevitable

by Jack Kang on SiFive 17 November 2021 18:00 UTC

In just a few short years, RISC-V has become a category of utmost importance in tech; but, things are just getting started. In 2014, the inventors of RISC-V (and founders of SiFive) published a very “modest” goal: for RISC-V to become the standard ISA for all computing devices. Ambitious at the time, but now we can confidently state that RISC-V has made its impact in our industry and is here to stay. RISC-V has become hugely important – strategic to companies and governments alike – and has ...

Goodbye Blogger, Hello Static Site

by Tudor Timi on Verification Gentleman 14 November 2021 17:32 UTC

Announcement The Verification Gentleman Blog will be moving from Blogger.Why?While Blogger was a great platform to start on, especially considering the fact that it's 100% free, I feel that I've outgrown it.The interface is very arcane and it's very difficult to do any kind of customization. For example, setting up syntax highlighting required fiddling with a lot of things to get it working and even then the results aren't all that great. It's very easy to mess up the entire blog and not be ...

A Comparison of Formal and Simulation for a Simple, Yet Non-Trivial Design - Part 1

by Tudor Timi on Verification Gentleman 24 November 2020 23:11 UTC

I've talked a lot about constrained random verification on the blog, but now it's time to branch out to formal verification. As a fun first post on the topic, I thought we could do a comparative study. We can take a design and write two verification environments for it, one using formal verification and the other using simulation, based on UVM. Once we're done, it should be very interesting to be able to look at them side-by-side and to do an analysis.I thought long and hard about which one ...

Favor Composition Over Inheritance - Even for Constraints

by Tudor Timi on Verification Gentleman 29 March 2020 15:02 UTC

Simulation is currently the dominant functional verification technique, with constrained random verification the most widely used methodology. While producing random data is a big part of it, letting the solver blindly generate stimulus isn't going to be very efficient. Constraints are needed to guide the stimulus toward interesting scenarios.A good constrained random test suite contains a mixture of tests with varying degrees of randomness. This is achieved by progressively adding ...

Bigger Is Not Always Better: Builds Are Faster with Smaller Packages

by Tudor Timi on Verification Gentleman 09 February 2020 18:44 UTC

One trend over the past few years is that the projects I've been working on tend to get bigger and more complicated. Bigger projects come with new challenges. Among these are the fact that it's much more difficult to keep the entire project in one's head, the need to synchronize with more developers because team sizes grow, a higher risk of having to re-write code because of poorly understood requirements or because some requirements change, and many more.There's one thing, though, that ...

Testing SVA Properties and Sequences

by Tudor Timi on Verification Gentleman 25 June 2017 21:25 UTC

After a pretty long absence, it’s finally time to complete the series on unit testing interface UVCs. I meant to write this post in October/November 2016. While writing the code, I got bogged down by a simulator bug and tried to find an elegant work around, but failed. I got frustrated and shelved the work for a while. In the meantime I got caught up with technical reading and with taking online courses. I’ve also been pretty busy at work, putting in quite a bit of overtime, which left ...

Testing UVM Drivers, Part 2

by Tudor Timi on Verification Gentleman 15 August 2016 14:30 UTC

In the previous post we looked at how we can emulate sequencer/driver communication using a lightweight stub of uvm_sequencer. Let's also look at some more tips and tricks I've picked up while writing unit tests for drivers. To mix things up a bit, let's look at the AXI protocol. We're not going to implement a full featured driver; instead, we'll focus on the write channels: interface vgm_axi_interface(input bit ACLK, input bit ARESETn); logic [3:0] AWID; logic [31:0] AWADDR; logic [3:0] ...

Testing UVM Drivers

by Tudor Timi on Verification Gentleman 07 August 2016 16:06 UTC

It's that time again when I've started a new project at work. Since we're going to be using some new proprietary interfaces in this chip, this calls for some new UVCs. I wouldn't even consider developing a new UVC without setting up a unit testing environment for it first. Since this is a greenfield project, a lot of the specifications are volatile, meaning that the interface protocol can change at any moment. Having tests in place can help make sure that I don't miss anything. Even if the ...

A Quick Look at SVAUnit

by Tudor Timi on Verification Gentleman 24 July 2016 15:05 UTC

I've been writing more and more SystemVerilog assertions (SVAs) lately. I find that they are the best way to capture temporal requirements, allowing the rest of the (class-based) testbench to stay timing agnostic. Since assertions are a key part of the checking infrastructure we need to make sure that they're bulletproof. This means that we need to test them to make sure that they're doing what we expect them to do.The typical flow when writing an assertion is the following (for me, at ...

The Humble Beginnings of a SystemVerilog Reflection API, Part 3

by Tudor Timi on Verification Gentleman 01 June 2016 20:59 UTC

We've already looked at how to interrogate classes about what variables they have and how to set and get the values of these variables in different instances. Classes are much more than just data containers, though. They also contain methods that can operate on their variables. In this post we'll look at how we can handle tasks and functions inside our reflection API. Before we start, however, let's take a quick look at the two kinds of methods we can declare in SystemVerilog: tasks and ...

The Humble Beginnings of a SystemVerilog Reflection API, Part 2

by Tudor Timi on Verification Gentleman 20 May 2016 20:03 UTC

In the previous post we saw that it's possible to use the Verilog Programming Interface (VPI) to programmatically get information about classes. For example, we can "ask" a class what variables it has. We've wrapped the calls to the C interface in a nice SystemVerilog library by using the Direct Programming Interface (DPI). While being able to mine the code for information about its structure can prove very useful, what this gives use is merely introspection. True reflection requires that ...

The Humble Beginnings of a SystemVerilog Reflection API

by Tudor Timi on Verification Gentleman 10 April 2016 16:34 UTC

Reflection is a mechanism that allows "inspection of classes, interfaces, fields and methods at runtime without knowing the names of the interfaces, fields, methods at compile time. It also allows instantiation of new objects and invocation of methods". In e, using reflection together with define as compute macros allows us to do some really cool stuff. A major complaint about SystemVerilog is that it lacks reflection capabilities. These could be useful for writing super generic code,but ...

An Overview of UVM End-of-Test Mechanisms

by Tudor Timi on Verification Gentleman 25 March 2016 20:35 UTC

A lot traffic coming from Google to the blog is from searches about setting the UVM drain time. That's because one of my first posts was about how to set the drain time prior to going into the run phase. At the time of writing, this was the third most viewed post. End-of-test handling in UVM seems to be a topic a lot of people are interested in. In this post we’re going to look at different ways of implementing it. End-of-test relies on objections. Each component can raise objections during ...

Registering Abstract Classes with the UVM Factory

by Tudor Timi on Verification Gentleman 14 February 2016 17:18 UTC

Every now and again I stumble upon a situation where it's natural to use an abstract class. A typical example is when working with parameterized classes and wanting to swap parameterizations: virtual class some_abstract_component extends uvm_component; pure virtual function void do_stuff(); virtual task run_phase(uvm_phase phase); do_stuff(); endtaskendclassclass some_concrete_param_component #(type T = int) extends some_abstract_component; virtual function void do_stuff(); ...

Fun and Games with CRV: Einstein's Puzzle (Revisited)

by Tudor Timi on Verification Gentleman 09 December 2015 21:02 UTC

Two weeks ago, Aurelian from AMIQ published a post on how to solve the so-called Einstein's puzzle using e. At the end, he challenged us readers to try and improve on his solution. Not being one to shy away, I rolled up my sleeves and got to work.He started out by defining a struct to hold the information about a resident:<'struct resident { nationality : nationality_t; house_color : house_color_t; cigarette : cigarette_t; pet : pet_t; drink : drink_t;};'>He gave up on this idea after ...

Packages, Class Names and UVM

by Tudor Timi on Verification Gentleman 06 December 2015 18:17 UTC

Some time ago I wrote a post that challenged some of the established coding conventions of modern SystemVerilog. In particular, I expressed my displeasure with the fact that all training material from EDA companies, tutorial sites and other learning resources state that packages should always contain a "_pkg" suffix appended to the package name and that all identifiers in the package (class/function/constant names) should contain the package name as a prefix. I attribute this to the ...

Accessing Multiple Registers at Once

by Tudor Timi on Verification Gentleman 22 November 2015 23:32 UTC

As I already mentioned, I gave a talk at DVCon Europe this year on how to implement burst accesses to memories modeled using UVM_REG. The motivation for that was that the register package can already handle bus protocols that don't support burst operation, but it requires more user guidance for protocols that do support it. A question that came up afterwards on the conference floor was what the best way to handle burst accesses to multiple registers might be. I tried to sketch out an answer ...

El Correo Libre Issue 44

by Gareth Halfacree on LibreCores - Medium 09 November 2021 09:36 UTC

Cocotb 1.6.0 Provides Better HDL Datatypes, Improved Coroutine Scheduling, and MoreThe cocotb project — the COroutine based COsimulation TestBench — has announced the release of v1.6.0, which adds a range of improvements to the popular Python-based VHDL/Verilog RTL verification platform. “This release concludes a seven month development period,” says Philipp Wagner of the project’s development progress. “Instead of going directly to cocotb 2.0, we threw in another backwards-compatible ...

All Invited to the OpenTapeOut Open Source ASIC Design Conference This Weekend

by Gareth Halfacree on FOSSi – AB Open 05 November 2021 15:30 UTC

The free and open source silicon community, both established and simply interested, is invited to a new event this weekend: the OpenTapeOut Conference 2021, hosted by Zero to ASIC course creator Matt Venn. “We encourage all of you folks to join us at what we hope will be the start of a revolution! No matter who you are or where you are from, don’t care what you did, as long as you love ASICs [Application Specific Integrated Circuits] and electronics in general,” the event’s organisers ...

How the Imagination RVfpga: Understanding Computer Architecture course is giving engineering under-grads real-world skills | Robert Owen, Imagination Technologies

by RISC-V Community News on Blog – RISC-V International 05 November 2021 15:14 UTC

If you were to take a look through the academic materials now available about RISC-V you will find a wealth of information around SoC creation, including inventing special instructions and numerous implementation enhancements. But what about the vital “Start Here” materials – the foundation needed by teachers to bring the fundamentals of computer architecture to life? This content contains the relatively unglamorous beginnings of the education process. Every computer science, computer ...

Improving the OpenLane ASIC build flow with open source SystemVerilog support | Antmicro

by Antmicro on Blog – RISC-V International 04 November 2021 01:53 UTC

Open source toolchains are key to building collaborative ecosystems, welcoming to new approaches, opportunistic/focused innovations and niche use cases. The ASIC design domain, especially in the view of the rising tensions around manufacturing and supply chains, are in dire need of a software-driven innovation based on an open source approach. The fledgling open source hardware ecosystem has been energized by the success of RISC-V and is now being vastly expanded to cover the entire ASIC ...

How Alibaba is Porting RISC-V to the Android OS | Guoyin Chen, Alibaba

by RISC-V Community News on Blog – RISC-V International 02 November 2021 16:40 UTC

With the high performance Alibaba T-Head XuanTie processor coming to market, we believe it will benefit the RISC-V industry to port RISCV to the Android OS. Over the past year, Alibaba T-Head has spent tremendous effort porting Android 10 to the RISC-V instruction set architecture (ISA). Of course, the Android ecosystem is rather complicated. Though we are still far from being done, we have made good progress, especially on some of the key aspects such as Android NDK, Bionic, ART and ...