Planet LibreCores

RISC-V International and seL4 Foundation Announce New Security Milestone

by Kim McMahon on Announcements – RISC-V International
SAN FRANCISCO, May 5, 2021 – Today, the seL4 Foundation and RISC-V International announced that the verified seL4 microkernel on the RV64 architecture has been proved down to the executable code by CSIRO’s Data61, thanks to funding provided by HENSOLDT Cyber GmbH. This guarantees that the seL4 microkernel on RV64 will operate to specification even when built with an untrusted C compiler, GCC. Within and across open collaboration communities it is essential to work together on areas of ...

seL4 on RISC-V Verified to Binary Code

by Gernot Heiser on Blog – RISC-V International
teaser image Author: Gernot Heiser, seL4 Foundation In June 2020 we announced that the seL4 microkernel, the world’s first operating system (OS) kernel with a machine-checked proof of implementation correctness, has now also been verified for the RV64 architecture, making it the first formally verified OS for RISC-V. We are pleased to announce that this verification has now been extended to the executable binary, meaning that the machine code running on the processor is proved to be correct ...

The world’s first DSP based on RISC-V ISA is about to be mass-produced

by Bao Yonggang(包永刚) on Blog – RISC-V International
teaser image RISC-V, the “youngest” ISA (Instruction Set Architecture), which was born in year 2010, has attracted many giant supporters, such as Google, Qualcomm, Western Digital, Alibaba, Huawei, and UNISOC. In recent years, the chip with open source RISC-V ISA has achieved good results in the IoT market, which has brought considerable pressure to ARM which has an advantage in this market. Semico Research predicts that there will be 62.4 billion CPU of RISC-V cores in the world in 2025. ...

CHIPS Alliance, Efabless Announce MPW-TWO Shuttle for More Free FOSSi Chips

by Gareth Halfacree on FOSSi – AB Open
CHIPS Alliance and Efabless have announced the launch of MPW-TWO, the second shuttle in the Open MPW programme – offering a second opportunity for free and open source silicon projects to see their designs manufactured. “MPW-TWO is the second Open MPW Shuttle providing fabrication for fully open-source projects using the SkyWater Open Source PDK announced by Google and SkyWater,” CHIPS Alliance general manager Rob Mains explains. “The shuttle gives designers the freedom to innovate without ...

RISC-V International Launches Development Board Giveaway

by Gareth Halfacree on FOSSi – AB Open
RISC-V International, a non-profit which aims to further develop and promote the use of the free and open-source RISC-V instruction set architecture, has announced a giveaway: Members can apply now to receive a free RISC-V development board with up to 16GB of RAM. “RISC-V is now being engineered into everything from soldering irons to supercomputers,” writes RISC-V International chief technology officer Mark Himelstein. “One step along the way is facilitating the availability of development ...

RISC-V International Welcomes Chengwei Capital as a Premier Member

by Kim McMahon on Announcements – RISC-V International
Investment firm Chengwei Capital to join the RISC-V Board of Directors and Technical Steering Committee Zurich – April 29, 2021 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced that Chengwei Capital has joined the organization as a Premier Member. As part of the Premium membership tier, Chengwei Capital will be joining the RISC-V ...

A first look at Edalize for ASIC flows

by Olof Kindgren on Tales from Beyond the Register Map
teaser image Over the past years there has been a revolution in open source silicon. While there have been open source IP cores and open source chip design tooling available for at least 25 years, a lot of this has been disparate efforts. What we see now is that many of these projects are coming together as a tour de force creating a snowball effect of generating more projects and innovations being built from these earlier efforts. As I mentioned in my 2020 retrospective, we finally reached an important ...

RISC-V Developer Boards to drive innovation

by Mark Himelstein on Blog – RISC-V International
We are at an incredible inflection point for RISC-V. We are making history and we want you to be a part of it! RISC-V is now being engineered into everything from soldering irons to supercomputers. One step along the way is facilitating the availability of development boards for testing and development. We are inviting developers to sign up for a RISC-V developer board sponsored by RISC-V and our RISC-V contributing members. We have boards available and we want you to have one! The boards ...

What’s new in AI & ML from SiFive

by Patrick Little on SiFive
Introducing the SiFive Intelligence X280 This week has been an exciting one for our team at SiFive, with a number of key announcements that are beginning to allow us to publicly share our strategy for the exponentially growing AI/ML market. While we are only scratching the surface of the impact AI/ML will have on our industry and our lives, it’s clear that the workloads, algorithms, and requirements are going to be constantly evolving and improving for the foreseeable future. These changing ...

SiFive Vector Processing Solutions To Be Highlighted at Linley Spring Processor Conference 2021

by Chris Jones on SiFive
Tremendous progress has been made in the last year bringing RISC-V vector (RVV) extensions to market in both hardware implementations and supporting compiler technologies. SiFive has gone a step further with the inclusion of new vector operations specifically tuned for the acceleration of machine learning operations. These new instructions, integrated with a multicore, Linux-capable, dual-issue microarchitecture, with up to 512b wide vectors, and bundled with TensorFlow Lite support, are ...

Bugs: A verification engineer’s dream, a designer’s nightmare

by Ashish Darbari on Blog – RISC-V International
teaser image This blog was originally published on the Axiomise website. Read the original blog. Who wants to have bug escapes? Nobody. Who wants to have bugs in the design? Nobody. Who wants to find bugs in the design? I do. Finding bugs is every verification engineer’s dream, in my case establishing bug absence is as well via mathematical proof. Designers don’t want bugs in the design – they’re a nightmare for ...

SoC Integration Testing: Hw/Sw Coordination (Part 2)

by Matthew Ballance on Bits, Bytes, and Gates
Controlling the outside world -- specifically interface BFMs -- from embedded software is critical to SoC integration tests that exercise interface IP. In the last post, we showed how to pass data from embedded software to Python by tracing execution of the processor core and reading the mirrored values of registers and memory to obtain parameter values. While functional, doing things in this way

SiFive Core IP 21G1

by Graham Wilson on SiFive
The best just got better--SiFive’s latest Processor Core IP Portfolio release We’re pleased to announce a comprehensive update to SiFive’s RISC-V Core IP Portfolio with the SiFive 21G1 release. This release brings important enhancements and new capabilities to SiFive® Core IP, the industry's broadest RISC-V IP Portfolio, ranging from the ultra-capable SiFive U7-Series to the extremely popular SiFive E2-Series, offering up to 35% more performance for bit processing algorithms; and up to 25% ...

SiFive RISC-V Proven in 5nm Silicon

by Chris Jones on SiFive
OpenFive Tapes Out SoC for Advanced AI/HPC Solutions on TSMC 5nm Technology Today, I am pleased to see OpenFive, a SiFive business unit that is the leading provider of customizable, silicon-focused solutions with differentiated IP, is continuing to make progress with AI design solutions with the creation of a reference design chiplet architecture using OpenFive Die-to-Die interface, OpenFive HBM3 IP subsystem, and SiFive 7-Series processor IP, for 2.5D-based SoCs. More details on the full ...

El Correo Libre Issue 37

by Gareth Halfacree on LibreCores - Medium
teaser image Become a GSoC Student with FOSSi Foundation in 2021!We are delighted to announce that we have once again been selected as a mentor organisation for the 2021 edition of Google Summer of Code (GSoC) Google Summer of Code is an excellent program for students to receive a stipend (generously provided by Google) to contribute to open source projects in the FOSSi community. As an organisation, we serve as an umbrella org for projects in the space of open source silicon design, EDA tools, and the ...

Open Source FPGA Foundation Launches to “Democratise and Promote” FPGA Tech

by Gareth Halfacree on FOSSi – AB Open
The cause of free and open source silicon gained a new ally this week with the launch of the Open Source FPGA Foundation, which aims to promote open source tools and methodology in field programmable gate arrays (FPGAs). Founded by members from industry and academia, including board members from the Universities of Utah and Toronto, Quicklogic, Zero ASIC, the École polytechnique fédérale de Lausanne (EPFL), GSG Group, and led by chief executive Dr. Shrikant Lohokare, the Open Source FPGA ...

RISC-V Application to Machine Language | Maven Silicon

by Maven Silicon on Blog – RISC-V International
RISC-V Application to Machine Language March 17, 2021 Sivakumar P R This video explains how a RISC-V processor executes all the software applications written in the high-level language in terms of its machine language. Follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. The post RISC-V Application to Machine Language | Maven Silicon appeared first ...

Antmicro Adds an LPDDR4 PHY to Enjoy Digital’s LiteDRAM, Releases Test Board

by Gareth Halfacree on FOSSi – AB Open
Free and open-source silicon pioneer Antmicro has added a low-power DDR4 (LPDDR4) PHY to Enjoy Digital’s open LiteDRAM project, and has released an open-hardware test board trying it out on a Xilinx Kintex-7 FPGA. “This [adds] support for LPDDR4 PHYs in LiteDRAM,” Antmicro’s Jędrzej Boczar wrote of the original pull request to the LiteDRAM project, which exists to offer a small-footprint and configurable dynamic RAM (DRAM) core for open hardware projects. “[The] base PHY’s job is to convert ...

Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT project

by Antmicro on Blog – RISC-V International
teaser image The EU-funded Very Efficient Deep Learning in IoT (VEDLIoT) project is underway. Launched at the end of 2020, it aims to build a next-generation IoT platform powered by deep learning algorithms. VEDLIoT comprises 12 partners from 5 countries, including Strategic Founding RISC-V International member Antmicro as well as research institutions such as our partner RISE and industry heavyweights like Veoneer or Siemens. Antmicro’s role will focus on bringing the strengths of the RISC-V ISA and ...

Opening Up New Design Possibilities with OmniXtend

by Rob Mains on Blog – RISC-V International
I am thrilled to see the announcement and initiation of collaboration between CHIPS Alliance and RISC-V International on the OmniXtend Cache Coherency protocol. We have formed a joint working group to strengthen and harden the architecture to allow for the effective collaboration of heterogeneous computational cores, which will open a wide design ecosystem. The collaboration will drive new architectural ideas and will result in innovative products by companies that wish to leverage and ...

SoC Integration Testing: Hw/Sw Test Coordination (Part 1)

by Matthew Ballance on Bits, Bytes, and Gates
IP- and subsystem-level testbenches are quite monolithic. There is a single entity (the testbench) that applies stimulus to the design, collects metrics, and checks results. In contrast, an SoC-level testbench is composed of at least two islands: the software running on the design’s processor and the external testbench connected to the design interfaces. Efficiently developing SoC tests

The Cybersecurity Pincushion and a Myriad of Tiny Threat Points

by Abhi Arora on Blog – RISC-V International
teaser image “Large organizations are using over 130 tools on average. This is just massive!” – Matt Chiodi, CSO, Palo Alto Networks’ public cloud A new Cloud Defense (CD) white paper reports on this critical need for centralized security policy and reporting controls. Tech companies today use way too many security tools; wasting their developers’ time, increasing attack surfaces, with most tools being incompatible or not talking to each other.  This folktale-esque hydra problem has partial ...

SiFive collaborates with new Intel Foundry Services to enable innovative new RISC-V computing platforms

by Patrick Little on SiFive
Enabling more choice for Next-Generation Heterogeneous Compute Platforms I am excited to see Intel's new Foundry services business (IFS) in the U.S. and Europe increase the opportunity and choice for the semiconductor industry. We’re pleased to see Intel recognize the utility and opportunity for the RISC-V instruction set architecture in partnering to enable SiFive’s industry-leading Core IP portfolio to enable a new wave of leading-edge technology. SiFive is the leading provider of ...

CHIPS Alliance and RISC-V International Invite the RISC-V Community to Participate in Updating a New Unified Memory Architecture Standard

by Kim McMahon on Announcements – RISC-V International
New joint working group will enhance the OmniXtend Cache Coherency architecture SAN FRANCISCO, March 24, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), and CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced a joint collaboration to update the OmniXtend Cache ...

Check out the new RISC-V Careers page and RISC-V Mentorship program!

by Kim McMahon on Blog – RISC-V International
teaser image We are excited to announce the new RISC-V Careers page and RISC-V Mentorship program! As the RISC-V ecosystem and community grow, we’re bringing together those seeking RISC-V careers and our member companies seeking talent. RISC-V Careers RISC-V Careers is our online forum for posting RISC-V career opportunities. RISC-V Member organizations are welcome to post their open full-time, part-time, co-op, or internship positions. The community will find this an excellent resource to find their ...

FOSSi Fever 2020

by Olof Kindgren on Blog – RISC-V International
teaser image 2020 was a year with a lot of bad news and so it feels slightly strange to cheerfully write about a very specific topic in the light of this. But there will always be good and bad things happening in the world. So let’s keep fighting the bad things and for now take look at what happened last year within the amazing world of open source silicon. I will start by mentioning the most significant, but by no means the only, milestones for the FOSSi movement as a whole and then take a more ...

RISC-V Security Forum 2021 – Schedule Announced!

by Kim McMahon on Blog – RISC-V International
teaser image The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events – providing technical content to the RISC-V community. Our first Forum is on Security, April 14, 7-10am Pacific Daylight Time. Registration is open and complimentary to both members and non-members. With the many exciting things happening in the Security area, we have an amazing agenda that covers the latest trends on Security, how people are using ...

NVDLA Deep Learning Inference Compiler is Now Open Source

by on SiFive
teaser image Designing new custom hardware accelerators for deep learning is clearly popular, but achieving state-of-the-art performance and efficiency with a new design is a complex and challenging problem. Two years ago, NVIDIA opened the source for the hardware design of the NVIDIA Deep Learning Accelerator (NVDLA) to help advance the adoption of efficient AI inferencing in custom hardware designs. The same NVDLA is shipped in the NVIDIA Jetson AGX Xavier Developer Kit, where it provides ...

SiFive Connect : SiFive in Virtual World-Webinar Series

by Swamy Irrinki on SiFive
teaser image A Platform Designed for Continued Engagement with the Global Hardware and Software Community Developing RISC-V Based Semiconductor Solutions. After hosting the SiFive Tech Symposiums in a record 52 cities in 2019, it became amply evident that the RISC-V revolution has reached all corners of the globe and is here to stay. RISC-V cores are being designed into many SoCs and domain-specific custom silicon. To take our previous engagement with the global community to the next level, we’re ...

SiFive’s Approach to Embedding Intelligence Everywhere

by Tom Simon on SiFive
teaser image Published by SemiWiki. Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made over many years. RISC-V was conceived with a clean well thought out architecture and designed for expansion that would not create inconsistencies. Because it is open source, there is a rich set of ...

PDKMaster v0.1 release and FreePDK45 example

by Fatsie on Chips4Makers.io
After a lot of blood, sweat and tears I have now reached a new milestone for my NGI0 NLnet project. I released v0.1 of the PDKMaster python framework together with a standard cell library generator and an example PDK implementation for the FreePDK45 technology. It consist of the following three releases: PDKMaster v0.1 (PyPI) PDK Master is a tool to manage PDKs for ASIC design and a framework for designing circuits and layouts in those technologies. It consists of different parts: Python ...

Cocotb 1.5.0 is out!

by FOSSi Foundation on FOSSi Foundation - News & Posts
The cocotb project is proud to announce the release of its new version 1.5.0. cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. Cocotb can be installed and updated from PyPi through pip: pip install --upgrade cocotb For full installation instructions refer to the documentation at https://docs.cocotb.org/en/v1.5.0/install.html. This release concluces a nine month development period, slightly longer than the last releases. A major ...

OpenHW Group, Mitacs Announce £16.2m OpenHW Accelerate Research Funding Programme

by Gareth Halfacree on FOSSi – AB Open
OpenHW Group has announced a partnership with fellow not-for-profit Mitacs to launch a £16.2 million multi-year co-funded research programme for free and open-source silicon: OpenHW Accelerate. “OpenHW Group is transforming how the industry adopts open-source hardware and is bringing relevant research projects to leading industry and academic institutions worldwide,” says OpenHW Group founder and chief executive Rick O’Connor. “With strong support from Mitacs, the OpenHW Accelerate ...

Become a GSoC student 2021!

by FOSSi Foundation on FOSSi Foundation - News & Posts
We are delighted to announce that we have once again been selected as a mentor organisation for the 2021 edition of Google Summer of Code (GSoC) Google Summer of Code is an excellent program for students to receive a stipend (generously provided by Google) to contribute to open source projects in the FOSSi community. As an organisation, we serve as an umbrella org for projects in the space of open source silicon design, EDA tools, and the surrounding ecosystem. For those previously ...

Growing an Open and Inclusive Community

by Kim McMahon on Blog – RISC-V International
Collaboration underpins everything we do in the RISC-V community. That’s why we encourage everyone to join us and participate, and why we are working hard to foster an inclusive global community that celebrates diversity in all its forms, including gender identity and expression, ethnicity, race, nationality, sexual identity or orientation, disability, religion, age, and beyond. We are committed to providing an open and welcoming environment that is safe and harassment-free, which is both ...

El Correo Libre Issue 36

by Gareth Halfacree on LibreCores - Medium
teaser image 45 Chips in 30 Days — Open-Source ASIC at its BestOnly seven months ago, open source chips were a dream of some, and clearly impossible to others. Today we know better. In a joint effort between efabless, Google, and the SkyWater foundry, everybody got a chance to send an open source chip to fabrication. And many did!One of the key people who made all of that happen is Mohamed Kassem, co-founder and CEO of efabless. He joined us at FOSSi Dial-Up to discuss how the “Open MPW” program went so ...

45 Chips in 30 Days: Open Source ASIC at its best!

by FOSSi Foundation on FOSSi Foundation - News & Posts
Only seven months ago, open source chips were a dream of some, and clearly impossible to others. Today we know better. In a joint effort between efabless, Google, and the SkyWater foundry, everybody got a chance to send an open source chip to fabrication. And many did! One of the key people who made all of that happen is Mohamed Kassem, co-founder and CEO of efabless. He joined us at FOSSi Dial-Up to discuss how the “Open MPW” program went so far. (A recording of the talk is available on ...

RISC-V Execution Stages | Maven Silicon

by Maven Silicon on Blog – RISC-V International
This video explains the execution stages of a RISC-V processor and how it executes all the instructions. Follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc.To know more, explore our RISC-V courses. The post RISC-V Execution Stages | Maven Silicon appeared first on RISC-V International.

Wave Computing Rebrands to MIPS, Embraces RISC-V For Next-Gen Cores

by Gareth Halfacree on FOSSi – AB Open
Wave Computing has emerged from bankruptcy proceedings with the surprise news that it’s taking the name of its MIPS subsidiary and moving to the free and open-source RISC-V ISA for future processor IP. Wave Computing dipped its toes in the free and open-source silicon movement back in 2018, announcing that its subsidiary MIPS Tech, acquired from Imagination Technologies in June that year, would provide 32- and 64-bit versions of the MIPS instruction set architecture (ISA) and full licences ...

Learn About the RISC-V ISA with Two Free Training Courses from The Linux Foundation and RISC-V International

by Kim McMahon on Announcements – RISC-V International
The online courses are offered on edX.org and will make RISC-V training more accessible SAN FRANCISCO – EMBEDDED WORLD – March 2, 2021 – The Linux Foundation, the non-profit organization enabling mass innovation through open source, and RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), have announced the release of two new free online training courses ...

RISC-V Star Rising from the East – Introducing StarFive

by Chloe Ma on Blog – RISC-V International
teaser image With the recent announcement of BeagleVTM, reported by premium technology media Ars Technica, Tom’s Hardware, CNX Software, as well as many others, a new name has emerged in front of the eyes of tech enthusiasts and geeks – StarFive. The BeagleV board was brought to the RISC-V and open source community as the first affordable RISC-V computer designed to run Linux by three companies/organizations – BeagleBoard.org, Seeed Studio and StarFive. I really like the analogy made by Jason Kridner, ...

RISC-V growth and successes in technology and industry : embedded world 2021

by Kim McMahon on Blog – RISC-V International
  RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and healthy RISC-V ecosystem. It is projected that by 2025 there will be over 62 billion RISC-V CPU cores and the total market for RISC-V IP and software is expected to grow to over $1b by 2025.   In 2020 alone, we saw successes with newly defined RISC-V accelerator architectures, affordable RISC-V open ...

SoC Integration Testing: IP-Integrated Debug and Analysis

by Matthew Ballance on Bits, Bytes, and Gates
One of the things I've always liked about side projects is the freedom to stop and explore a topic of interest as it comes up. One such topic that came up for me recently is IP-integrated debug and analysis instrumentation. I started thinking about this after the last post (link) which focused on exposing a higher-abstraction-level view of processor-core execution. My initial approach to doing

FuseSoC 1.12

by Olof Kindgren on Tales from Beyond the Register Map
teaser image It's February 25th 2021 today and you all know what that means! It's time for another FuseSoC release! So what happened since last time? Well, let's find out.  First of all, as I mentioned in the 2020 retrospective, most of the work during this development cycle has been done by Philipp Wagner. Thanks Philipp! He wasn't the alone though. This release had in total 11 people contributing code and looking at the history this is the most people contributing on a single release ever. As always, ...

OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IP

by Kevin McDermott on Blog – RISC-V International
teaser image The RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition, implementations may be shared commercially or as open-source, and adopters beyond the original design team can use these directly or as a basis for further modifications and enhancements. The OpenHW Group is a not-for-profit, global organization of members based on the principles of open-source hardware IP, with ...

RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension

by Kim McMahon on Announcements – RISC-V International
RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension Fast Track significantly accelerates the ratification of small architecture extensions Zurich – Feb. 23, 2021 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), unveiled its Fast Track Architecture Extension Process (Fast Track) that streamlines ...

FOSSi Fever 2020

by Olof Kindgren on Tales from Beyond the Register Map
teaser image 2020 was a year with a lot of bad news and so it feels slightly strange to cheerfully write about a very specific topic in the light of this. But there will always be good and bad things happening in the world. So let's keep fighting the bad things and for now take look at what happened last year within the amazing world of open source silicon. I will start by mentioning the most significant, but by no means the only, milestones for the FOSSi movement as a whole and then take a more ...

RISC-V Becoming Less Risky with the Right Verification

by Rob van Blommestein on Blog – RISC-V International
teaser image RISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first RISC-V core, the CV32E40P. If you attended last month’s RISC-V Summit, perhaps you attended “CORE-V: Industrial Grade Open-Source RISC-V Cores” by Rick O’Connor, president of the OpenHW Group. In this session, Rick discussed how the organization teamed with OneSpin and several other verification partners to develop the CORE-V-VERIF ...

High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platform

by Antmicro on Blog – RISC-V International
teaser image Originally published by Antmicro   In the daily work at Antmicro, they use FPGAs primarily for their flexibility and parallel data processing capabilities that make them remarkably effective in advanced vision and audio processing systems involving high-speed interfaces such as PCI Express, USB, Ethernet, HDMI, SDI etc. that they develop and integrate as open source, portable building blocks. Many of their customers, however, use FPGAs also in a different context, namely for designing ...

Poor Men's SMU, part 4: Calibration

by Fatsie on Chips4Makers.io
teaser image As reported in my previous blog on using the AD5522 SMU development board it was mentioned calibration would be needed to get more accurate low-voltage and low-current measurements. Procedure An important aspect of doing calibration is the order in which the parameters are calibrated and what references are used during the calibration. The order is important as metrics are correlated; for example calibrating input offsets should be calibrated before output offsets are calibrated as ...

El Correo Libre Issue 35

by Gareth Halfacree on LibreCores - Medium
teaser image Looking Forward to Another Virtual YearLast year we started FOSSi Dial-Up as a premier online replacement for our various popular physical events. We chose to launch FOSSi Dial-Up as a monthly, in-depth event with one presenter. With that format and thanks to our awesome speakers, we were able to focus on a particular topic each time and attract many new people. Our entire series last year was focused on the Skywater Open Source PDK and the various improvements of the open source EDA tool ...

Hardware Description Language Chisel & Diplomacy Deeper dive

by dev_msyksphinz on Blog – RISC-V International
teaser image Are you using Chisel? A hardware building language based on Scala. Not a high-level synthesis language. SiFive’s RISC-V IP use Chisel Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom Chisel Basics : “Chiselを始めたい人に読んで欲しい本” https://nextpublishing.jp/book/12162.html How Chisel generates Verilog Chisel is a Scala DSL, so the Chisel Compiler is written in Scala. Chisel Compiler generates an intermediate language called FIR (Flexible ...

SoC Integration Testing: Higher-Level Software Debug Visibility

by Matthew Ballance on Bits, Bytes, and Gates
Debug is a key task in any development task. Whether debugging application-level software or a hardware design, a key to productive debug is getting a higher-level view of what is happening in the design. Blindly stepping around in source code or staring at low-level waveforms is rarely a productive approach to debugging. Debug-log messages provide a high-level view of what's happening in an

Where to start with RISC-V

by Rhys Davies on Blog – RISC-V International
teaser image Originally posted on Medium How to get started, where to contribute, and what to do next RISC-V made the news recently when BeagleBoard.org revealed the BeagleV (Beagle Five) SBC (single board computer). The first affordable, highly available SBC that uses the RISC-V architecture. The board isn’t yet commercially available but you can register to be considered for the first wave when they ship in April. For those who don’t know anything about RISC-V, let me explain. ...

Squeezing FPGA memory

by DP on FPGA – Dangerous Prototypes
teaser image Squeezing FPGA memory @ Big Mess o’Wires: I’m developing an Apple II disk controller that’s based on the UDC disk controller design. The original UDC card had 8K of ROM and 2K of RAM, so it needs 10K of combined memory. The FPGA device I’m using for prototyping, a Lattice MachXO2-1200, has 8K of embedded block RAM and 1.25K of distributed RAM. It also has 8K of “user flash memory”. So will the UDC design fit? It’s close, but I think the answer is no.

OpTiMSoC Enabled Demonstrator System with Fault-Tolerant NoC

by OpTiMSoC on OpTiMSoC
teaser image Although it has been silent around OpTiMSoC in recent months, some development is still ongoing. Based on OpTiMSoC, a demonstrator system has been developed in the scope of the ARAMiS II research project and has since been further improved. This blog post describes the demonstrator system, its architecture and building blocks, and the alterations and extensions made to OpTiMSoC in order to build it. Purpose of the demonstrator The demonstrator was implemented to demonstrate the ...

Alibaba’s T-Head Releases Full Android 10 Port for RISC-V

by Gareth Halfacree on FOSSi – AB Open
T-Head, the semiconductor division of Alibaba, has released the source code for a functional port of Android 10 to the RISC-V architecture – including a guide to getting it up and running in the QEMU emulator. The earliest success in porting the Android Open Source Project (AOSP) version of Android 10 to the free and open source RISC-V architecture came late last year when PLCT Lab announced its first successful minimal boot. T-Head’s effort, by contrast, goes considerably further: The ...

Overview of Diplomacy for writing effective hardware design language Chisel (Japanese)

by dev_msyksphinz on Blog – RISC-V International
teaser image ハードウェア記述言語Chiselをもっともっと活用するためのDiplomacy概説 発表者:msyksphinz (FPGA開発日記著者) @msyksphinz_dev https://msyksphinz.hatenablog.com Chisel使ってますか? Scalaをベースとしたハードウェア構築言語. 高位合成言語ではない SiFiveのRISC-V IPで採用されている Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom Chiselの基礎 : 「Chiselを始めたい人に読んで欲しい本」 https://nextpublishing.jp/book/12162.html ChiselがVerilogを生成するまで ChiselはScalaのDSLなので、Chisel CompilerはScalaで記述してある Chisel CompilerはFIR (Flexible ...

RISC-V CPU Performance | Maven Silicon

by RISC-V Community News on Blog – RISC-V International
This video explains how Maven Silicon measures the CPU performance and how we try to improve the processor performance by improving its clock frequency and CPI. Also, it shows the importance of maintaining CPI as 1 for any multistage pipelined processor. To know more, explore our RISC-V courses, https://elearn.maven-silicon.com/risc-v The post RISC-V CPU Performance | Maven Silicon appeared first on RISC-V International.

Embench 1.0 Benchmark Suite for IoT Class Devices Released

by FOSSi Foundation on FOSSi Foundation - News & Posts
The Embench group announces the first full release of its free and open source benchmark suite for IoT class devices. The benchmark suite, comprising 19 real programs, has proved popular across industry and academia since the pre-release version 0.5 was made available in February 2020. The project is developed by an open group, with contributors from companies and universities worldwide. The code is available under a free and open source license on GitHub (see ...

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Last updated 08 May 2021 00:30 UTC