Planet Librecores

45 Chips in 30 Days: Open Source ASIC at its best!

by FOSSi Foundation on FOSSi Foundation - News & Posts 07 March 2021 00:00 UTC

Only seven months ago, open source chips were a dream of some, and clearly impossible to others. Today we know better. In a joint effort between efabless, Google, and the SkyWater foundry, everybody got a chance to send an open source chip to fabrication. And many did! One of the key people who made all of that happen is Mohamed Kassem, co-founder and CEO of efabless. He joined us at FOSSi Dial-Up to discuss how the “Open MPW” program went so far. (A recording of the talk is available on ...

RISC-V Execution Stages | Maven Silicon

by Maven Silicon on Blog – RISC-V International 05 March 2021 15:54 UTC

This video explains the execution stages of a RISC-V processor and how it executes all the instructions. Follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc.To know more, explore our RISC-V courses. The post RISC-V Execution Stages | Maven Silicon appeared first on RISC-V International.

Wave Computing Rebrands to MIPS, Embraces RISC-V For Next-Gen Cores

by Gareth Halfacree on FOSSi – AB Open 04 March 2021 15:57 UTC

Wave Computing has emerged from bankruptcy proceedings with the surprise news that it’s taking the name of its MIPS subsidiary and moving to the free and open-source RISC-V ISA for future processor IP. Wave Computing dipped its toes in the free and open-source silicon movement back in 2018, announcing that its subsidiary MIPS Tech, acquired from Imagination Technologies in June that year, would provide 32- and 64-bit versions of the MIPS instruction set architecture (ISA) and full licences ...

Learn About the RISC-V ISA with Two Free Training Courses from The Linux Foundation and RISC-V International

by Kim McMahon on Announcements – RISC-V International 02 March 2021 14:30 UTC

The online courses are offered on edX.org and will make RISC-V training more accessible SAN FRANCISCO – EMBEDDED WORLD – March 2, 2021 – The Linux Foundation, the non-profit organization enabling mass innovation through open source, and RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), have announced the release of two new free online training courses ...

RISC-V Star Rising from the East – Introducing StarFive

by Chloe Ma on Blog – RISC-V International 01 March 2021 15:00 UTC

With the recent announcement of BeagleVTM, reported by premium technology media Ars Technica, Tom’s Hardware, CNX Software, as well as many others, a new name has emerged in front of the eyes of tech enthusiasts and geeks – StarFive. The BeagleV board was brought to the RISC-V and open source community as the first affordable RISC-V computer designed to run Linux by three companies/organizations – BeagleBoard.org, Seeed Studio and StarFive. I really like the analogy made by Jason Kridner, ...

RISC-V growth and successes in technology and industry : embedded world 2021

by Kim McMahon on Blog – RISC-V International 01 March 2021 13:53 UTC

RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and healthy RISC-V ecosystem. It is projected that by 2025 there will be over 62 billion RISC-V CPU cores and the total market for RISC-V IP and software is expected to grow to over $1b by 2025. In 2020 alone, we saw successes with newly defined RISC-V accelerator architectures, affordable RISC-V open ...

SoC Integration Testing: IP-Integrated Debug and Analysis

by Matthew Ballance on Bits, Bytes, and Gates 28 February 2021 18:27 UTC

One of the things I've always liked about side projects is the freedom to stop and explore a topic of interest as it comes up. One such topic that came up for me recently is IP-integrated debug and analysis instrumentation. I started thinking about this after the last post (link) which focused on exposing a higher-abstraction-level view of processor-core execution. My initial approach to doing

FuseSoC 1.12

by Olof Kindgren on Tales from Beyond the Register Map 25 February 2021 21:41 UTC

It's February 25th 2021 today and you all know what that means! It's time for another FuseSoC release! So what happened since last time? Well, let's find out. First of all, as I mentioned in the 2020 retrospective, most of the work during this development cycle has been done by Philipp Wagner. Thanks Philipp! He wasn't the alone though. This release had in total 11 people contributing code and looking at the history this is the most people contributing on a single release ever. As always, ...

OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IP

by Kevin McDermott on Blog – RISC-V International 23 February 2021 22:43 UTC

The RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition, implementations may be shared commercially or as open-source, and adopters beyond the original design team can use these directly or as a basis for further modifications and enhancements. The OpenHW Group is a not-for-profit, global organization of members based on the principles of open-source hardware IP, with ...

RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension

by Kim McMahon on Announcements – RISC-V International 23 February 2021 16:52 UTC

RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension Fast Track significantly accelerates the ratification of small architecture extensions Zurich – Feb. 23, 2021 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), unveiled its Fast Track Architecture Extension Process (Fast Track) that streamlines ...

FOSSi Fever 2020

by Olof Kindgren on Tales from Beyond the Register Map 23 February 2021 12:49 UTC

2020 was a year with a lot of bad news and so it feels slightly strange to cheerfully write about a very specific topic in the light of this. But there will always be good and bad things happening in the world. So let's keep fighting the bad things and for now take look at what happened last year within the amazing world of open source silicon. I will start by mentioning the most significant, but by no means the only, milestones for the FOSSi movement as a whole and then take a more ...

RISC-V Becoming Less Risky with the Right Verification

by Rob van Blommestein on Blog – RISC-V International 12 February 2021 16:45 UTC

RISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first RISC-V core, the CV32E40P. If you attended last month’s RISC-V Summit, perhaps you attended “CORE-V: Industrial Grade Open-Source RISC-V Cores” by Rick O’Connor, president of the OpenHW Group. In this session, Rick discussed how the organization teamed with OneSpin and several other verification partners to develop the CORE-V-VERIF ...

High-throughput open source PCIe on Xilinx VU19P-based ASIC prototyping platform

by Antmicro on Blog – RISC-V International 11 February 2021 16:21 UTC

Originally published by Antmicro In the daily work at Antmicro, they use FPGAs primarily for their flexibility and parallel data processing capabilities that make them remarkably effective in advanced vision and audio processing systems involving high-speed interfaces such as PCI Express, USB, Ethernet, HDMI, SDI etc. that they develop and integrate as open source, portable building blocks. Many of their customers, however, use FPGAs also in a different context, namely for designing ...

Poor Men's SMU, part 4: Calibration

by Fatsie on Chips4Makers.io 10 February 2021 23:00 UTC

As reported in my previous blog on using the AD5522 SMU development board it was mentioned calibration would be needed to get more accurate low-voltage and low-current measurements. Procedure An important aspect of doing calibration is the order in which the parameters are calibrated and what references are used during the calibration. The order is important as metrics are correlated; for example calibrating input offsets should be calibrated before output offsets are calibrated as ...

El Correo Libre Issue 35

by Gareth Halfacree on LibreCores - Medium 09 February 2021 10:02 UTC

Looking Forward to Another Virtual YearLast year we started FOSSi Dial-Up as a premier online replacement for our various popular physical events. We chose to launch FOSSi Dial-Up as a monthly, in-depth event with one presenter. With that format and thanks to our awesome speakers, we were able to focus on a particular topic each time and attract many new people. Our entire series last year was focused on the Skywater Open Source PDK and the various improvements of the open source EDA tool ...

Hardware Description Language Chisel & Diplomacy Deeper dive

by dev_msyksphinz on Blog – RISC-V International 05 February 2021 17:04 UTC

Are you using Chisel? A hardware building language based on Scala. Not a high-level synthesis language. SiFive’s RISC-V IP use Chisel Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom Chisel Basics : “Chiselを始めたい人に読んで欲しい本” https://nextpublishing.jp/book/12162.html How Chisel generates Verilog Chisel is a Scala DSL, so the Chisel Compiler is written in Scala. Chisel Compiler generates an intermediate language called FIR (Flexible ...

SoC Integration Testing: Higher-Level Software Debug Visibility

by Matthew Ballance on Bits, Bytes, and Gates 30 January 2021 22:39 UTC

Debug is a key task in any development task. Whether debugging application-level software or a hardware design, a key to productive debug is getting a higher-level view of what is happening in the design. Blindly stepping around in source code or staring at low-level waveforms is rarely a productive approach to debugging. Debug-log messages provide a high-level view of what's happening in an

Where to start with RISC-V

by Rhys Davies on Blog – RISC-V International 29 January 2021 19:07 UTC

Originally posted on Medium How to get started, where to contribute, and what to do next RISC-V made the news recently when BeagleBoard.org revealed the BeagleV (Beagle Five) SBC (single board computer). The first affordable, highly available SBC that uses the RISC-V architecture. The board isn’t yet commercially available but you can register to be considered for the first wave when they ship in April. For those who don’t know anything about RISC-V, let me explain. ...

Squeezing FPGA memory

by DP on FPGA – Dangerous Prototypes 26 January 2021 23:58 UTC

Squeezing FPGA memory @ Big Mess o’Wires: I’m developing an Apple II disk controller that’s based on the UDC disk controller design. The original UDC card had 8K of ROM and 2K of RAM, so it needs 10K of combined memory. The FPGA device I’m using for prototyping, a Lattice MachXO2-1200, has 8K of embedded block RAM and 1.25K of distributed RAM. It also has 8K of “user flash memory”. So will the UDC design fit? It’s close, but I think the answer is no.

OpTiMSoC Enabled Demonstrator System with Fault-Tolerant NoC

by OpTiMSoC on OpTiMSoC 26 January 2021 00:00 UTC

Although it has been silent around OpTiMSoC in recent months, some development is still ongoing. Based on OpTiMSoC, a demonstrator system has been developed in the scope of the ARAMiS II research project and has since been further improved. This blog post describes the demonstrator system, its architecture and building blocks, and the alterations and extensions made to OpTiMSoC in order to build it. Purpose of the demonstrator The demonstrator was implemented to demonstrate the ...

Alibaba’s T-Head Releases Full Android 10 Port for RISC-V

by Gareth Halfacree on FOSSi – AB Open 22 January 2021 16:20 UTC

T-Head, the semiconductor division of Alibaba, has released the source code for a functional port of Android 10 to the RISC-V architecture – including a guide to getting it up and running in the QEMU emulator. The earliest success in porting the Android Open Source Project (AOSP) version of Android 10 to the free and open source RISC-V architecture came late last year when PLCT Lab announced its first successful minimal boot. T-Head’s effort, by contrast, goes considerably further: The ...

Overview of Diplomacy for writing effective hardware design language Chisel (Japanese)

by dev_msyksphinz on Blog – RISC-V International 21 January 2021 22:03 UTC

ハードウェア記述言語Chiselをもっともっと活用するためのDiplomacy概説発表者：msyksphinz (FPGA開発日記著者) @msyksphinz_dev https://msyksphinz.hatenablog.com Chisel使ってますか？ Scalaをベースとしたハードウェア構築言語. 高位合成言語ではない SiFiveのRISC-V IPで採用されている Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom Chiselの基礎 : 「Chiselを始めたい人に読んで欲しい本」 https://nextpublishing.jp/book/12162.html ChiselがVerilogを生成するまで ChiselはScalaのDSLなので、Chisel CompilerはScalaで記述してある Chisel CompilerはFIR (Flexible ...

RISC-V CPU Performance | Maven Silicon

by RISC-V Community News on Blog – RISC-V International 20 January 2021 16:23 UTC

This video explains how Maven Silicon measures the CPU performance and how we try to improve the processor performance by improving its clock frequency and CPI. Also, it shows the importance of maintaining CPI as 1 for any multistage pipelined processor. To know more, explore our RISC-V courses, https://elearn.maven-silicon.com/risc-v The post RISC-V CPU Performance | Maven Silicon appeared first on RISC-V International.

Embench 1.0 Benchmark Suite for IoT Class Devices Released

by FOSSi Foundation on FOSSi Foundation - News & Posts 19 January 2021 00:00 UTC

The Embench group announces the first full release of its free and open source benchmark suite for IoT class devices. The benchmark suite, comprising 19 real programs, has proved popular across industry and academia since the pre-release version 0.5 was made available in February 2020. The project is developed by an open group, with contributors from companies and universities worldwide. The code is available under a free and open source license on GitHub (see ...

SoC Integration Testing: Intro and Challenges

by Matthew Ballance on Bits, Bytes, and Gates 17 January 2021 02:29 UTC

As I mentioned in my end-of-year post, one of my 2020 projects was to develop a design for the Google/eFabless/SkyWater Multi-Project Wafer (MPW) fab run. One thing I looked forward to was applying elements of the Python-based verification flow that I've been developing. Doing so highlighted a gap in my verification toolkit: reusable infrastructure for SoC-level verification.Caravel and the User

Poor Men's SMU, part 3: Diodes are Forever

by Fatsie on Chips4Makers.io 16 January 2021 23:00 UTC

This is third part on my adventures with the AD5522 SMU development board. For history you can look at part 1 and part 2. After getting the SMU working and being able to operate it from Jupyter notebooks on a raspberry Pi I now decided to use the device to measure some diodes/LEDs. I did the measurement and the plotting again in a Python notebook. I also used the notebook to comment on the results. Head over to the html version of the notebook to learn all about the diode and LED ...

Open-Hardware BeagleV, at $149, is the Most Affordable RISC-V Linux Computer Yet

by Gareth Halfacree on FOSSi – AB Open 13 January 2021 13:07 UTC

BeagleBoard.org and Seeed Studio, in partnership with StarFive, have opened applications for an open-source, highly-affordable, Linux-capable RISC-V single-board computer: the $149 BeagleV. Launching with an initial pilot production batch in late March to early April, the BeagleV is an open-source single-board computer built around a StarFive system-on-chip implementing SiFIve’s U74 RISC-V cores. The two 64-bit application-processor-class RISC-V cores run at 1.5GHz, while accelerators ...

El Correo Libre Issue 34

by Gareth Halfacree on LibreCores - Medium 12 January 2021 09:19 UTC

Looking Back on 2020, The Year of the Open-Source Chip2020 was quite a year. Even though it played out different for each of us, we were united in that many of our plans didn’t work out. Much has been written about missed chances, but let’s end this year on a positive note and focus on the good things. After all, that’s something the software and hardware development community have always been good at: embracing change. So let’s call 2020 an “agile year” and do a “sprint recap.”A key part ...

Poor Men's SMU, part 2

by Fatsie on Chips4Makers.io 08 January 2021 23:00 UTC

This is a continuation of my adventure with the AD5522 development board (see part 1 ). I did make progress on setting it up but as always it has taken much more time than wanted to debug the setup. Schrödinger's cat One problem I had to solve was that the setup sometimes seemed to work flawlessly but other times not. Especially when I tried to debug the setup by looking at it though an oscilloscope all seemed to work but it did not seem to work when not looking at it. After some more ...

Let’s Make RISC-V Connected Systems Synonymous with Security

by Jon Jacobsen on Blog – RISC-V International 06 January 2021 14:00 UTC

This blog was submitted by Silex Insight. If you are designing systems based on a RISC-V architecture, for example to run highly connected applications, you want to include tight, future-proof security. Both for your customers’ experience and your reputation, you want to avoid a breach of security – leaking private data or even changing the functionality. Therefore, security should be part of the fabric of your system. Luckily, the RISC-V architecture offers a solid ground for security. ...

Poor Men's Source Measurement Unit (SMU)

by Fatsie on Chips4Makers.io 02 January 2021 23:00 UTC

SMU ? In my previous professional life doing semiconductor process development I used so called source measure units (SMUs) for measuring out transistors. Although I don't remember the exact type number, I guess I had access to a HP 4145A semiconductor parametric analyzer. Nice thing about these units is that these allow 4-quadrant operation, e.g. allow all the 4 combinations of positive or negative voltage with positive or negative current. It allows to force a voltage and measure current ...

Looking back on 2020, the year of the open source chip

by FOSSi Foundation on FOSSi Foundation - News & Posts 31 December 2020 00:00 UTC

Dear Free and Open Source Silicon enthusiasts! 2020 was quite a year. Even though it played out different for each of us, we were united in that many of our plans didn’t work out. Much has been written about missed chances, but let’s end this year on a positive note and focus on the good things. After all, that’s something the software and hardware development community have always been good at: embracing change. So let’s call 2020 an “agile year” and do a “sprint recap.” A key part of ...

2020: Nights and Weekends Projects in Review

by Matthew Ballance on Bits, Bytes, and Gates 29 December 2020 02:20 UTC

2020 in ReviewLast year was my first year-end blog post looking back at the prior year's projects, and I thought I'd continue the (now) tradition this year. 2020 has definitely been a different year for me, and not just because of the COVID19 situation. It's been a year to take a step back and consider directions, next steps, and the tools I'll need to get there. But it's also included some

OpenTitan at One Year

by lowRISC on lowRISC: Collaborative open silicon engineering 22 December 2020 12:00 UTC

Last year, along with our partners, lowRISC announced OpenTitan, the world’s first open source silicon root of trust. The project has progressed rapidly since then. A recent Google Security Blog post detailed key milestones met, our growth in contributors, and revealed news of the first commercial OpenTitan tapeout. OpenTitan’s success demonstrates the value of the lowRISC collaborative engineering model, wherein our full-stack engineering team allows us to serve as an essential ...

RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDA

by Steve Hoover on Blog – RISC-V International 15 December 2020 16:00 UTC

Last month I had the great pleasure of sharing a blog post about Nicholas Sharkey, an amazing 13 year-old who participated with graduate students and professionals in an online workshop of mine and developed his own pipelined RISC-V CPU core — an amazing feat for an 8th grader! Well, now, a month later, we just offered the workshop again and… I kinda feared when I posted about Nicholas that folks might get the wrong idea about the workshop. In fact, we had a second 12-year-old in this ...

RISC-V International Annual Awards

by Jeffrey Osier-Mixon on Announcements – RISC-V International 15 December 2020 01:52 UTC

Each year, RISC-V International recognizes certain members of the community who have gone above and beyond in their dedication and effort with RISC-V. These are the awards for 2020. RISC-V Innovation Founders Awards In recognition of the industry impact initiated by the technical leadership and generous contribution of the founding inventors and innovators of the RISC-V ISA. ...

Stream Computing Joins RISC-V International as a Premium Member

by Kim McMahon on Announcements – RISC-V International 08 December 2020 17:00 UTC

Silicon startup Stream Computing to join the RISC-V Board of Directors and Technical Steering Committee to advance open source AI innovation Zurich – Dec. 8, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced Stream Computing has joined RISC-V International as a Premium Member. A Stream Computing executive will join the RISC-V ...

RISC-V International Reports Another Strong Year of Growth with New Technical Milestones, Educational Programs, RISC-V Adoption and More

by Kim McMahon on Announcements – RISC-V International 08 December 2020 17:00 UTC

RISC-V sees widespread commercial adoption across industries, from embedded to AI, from IoT to HPC and beyond Zurich – Dec. 8, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), highlighted the organization’s incredible year of growth in a keynote today by Calista Redmond, CEO of RISC-V International, at the RISC-V Summit, which is being held ...

What is Processor Core Complexity?

by Roddy Urquhart on Blog – RISC-V International 29 November 2020 15:00 UTC

This blog was originally published on the Codasip blog. The more complex a processor core, the larger the area and power consumption. But increasing complexity is not a single dimension as processors can be more complex in different ways. In selecting a processor IP core, it is important to choose the right sort of complexity for your project. Some ways of thinking about complexity include: Word length Execution units Privilege/protection Virtual memory Security features Generally, the ...

RISC-V Gets an Early, Minimal Android 10 Port Courtesy of PLCT Lab

by Gareth Halfacree on FOSSi – AB Open 27 November 2020 10:22 UTC

PLCT Lab, a group working on compilers, runtimes, and emulators, has announced a milestone for its effort to port the Android Open Source project to the free and open-source RISC-V instruction set architecture: a successful minimal boot, with step-by-step instructions for trying it out yourself. With increasing interest in using the RISC-V instruction set architecture for mobile-centric devices, a major hurdle is a lack of software support. It’s long been possible to boot mainstream Linux ...

What is Needed to Support an Operating System?

by Roddy Urquhart on Blog – RISC-V International 25 November 2020 15:01 UTC

This blog was originally published on the Codasip blog. For each embedded product, software developers need to consider whether they need an operating system; and if so, what type of an OS. Operating systems vary considerably, from real-time operating systems with a very small memory footprint to general-purpose OSes such as Linux with a rich set of features. Choosing a proper type of operating system for your product – and consequently working out the required features of the embedded ...

A Comparison of Formal and Simulation for a Simple, Yet Non-Trivial Design - Part 1

by Tudor Timi on Verification Gentleman 24 November 2020 23:11 UTC

I've talked a lot about constrained random verification on the blog, but now it's time to branch out to formal verification. As a fun first post on the topic, I thought we could do a comparative study. We can take a design and write two verification environments for it, one using formal verification and the other using simulation, based on UVM. Once we're done, it should be very interesting to be able to look at them side-by-side and to do an analysis.I thought long and hard about which one ...

Kactus2 website has moved

by Esko Pekkarinen on Kactus2: News 24 November 2020 06:32 UTC

As part of the recent university merger, our previous website funbase.cs.tut.fi domain will be closed. The website have been moved to a new location at https://research.tuni.fi/system-on-chip/. The source code will continue to be hosted at https://github.com/kactus2/kactus2dev.

OTA: LimeSDR on the Traverse Ten64, LimeRFE Production Update, and More

by Gareth Halfacree on MyriadRF 23 November 2020 20:11 UTC

Traverse Technologies has showcased the flexibility of its Ten64 eight-core Linux-based networking platform for wireless use, demonstrating its compatibility with the LimeSDR USB and GNU Radio. “There has been quite a bit of interest in using Ten64 for software-defined radio (SDR) applications,” the company explains, “so we have put together a simple demo using a LimeSDR to tune into an FM radio station and stream it to the internet.” Built as a Docker container, the project uses GNU Radio ...

Understanding the Performance of Processor IP Cores

by Roddy Urquhart on Blog – RISC-V International 23 November 2020 14:52 UTC

This blog was originally published on the Codasip blog. Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider performance. The first thing to think about is what aspect of performance you care about. Do you care more about the absolute throughput that you want (performance ...

SiFive Strengthens Foothold in Storage Applications for Data-Centric AI Computing

by James Prior on SiFive 20 November 2020 14:00 UTC

SiFive RISC-V processors are powering flash drives in production as well as addressing emerging In-Storage Computing (ISC) needs In the current digital age, where data powers increasing levels of decision making, industrial control and automation, efficient data storage, movement, and processing become the focal point of technological innovations in silicon, system, and software. At SiFive, we have been designing and optimizing RISC-V based domain-specific solutions to address the ...

BBC Picks SiFive’s RISC-V-Powered HiFive Inventor for Doctor Who Coding Push

by Gareth Halfacree on FOSSi – AB Open 20 November 2020 09:56 UTC

The BBC has announced a partnership with SiFive to bring RISC-V-powered development to kids around the world with the launch of the BBC Doctor Who HiFive Inventor educational development board and supporting coursework bundle. Announced late last year, the SiFive Learn Inventor is a hand-shaped educational development board inspired by the popular BBC micro:bit but powered by SiFive’s Freedom E310 processor – itself driven by the free and open-source RISC-V instruction set architecture ...

RPC DRAM support in open source DRAM controller

by Antmicro on Blog – RISC-V International 18 November 2020 17:14 UTC

Original content published October 28, 2020 on the Antmicro blog. The Internet of Things is one of the areas that is hugely benefiting from miniaturization of semiconductor technologies, as more computing power can be encapsulated into increasingly smaller devices. Shrinking in size and requiring less power, various devices – including AI-capable ones – are applied in ways that were not possible a few years ago. One of the new and exciting developments in this space is the emergence of RPC ...

13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core

by Steve Hoover on Blog – RISC-V International 13 November 2020 15:00 UTC

One of my great pleasures operating my EDA startup, Redwood EDA, is working with enthusiastic college students and open-source developers and seeing how our technology is renewing excitement for logic design. Recently, Kunal Ghosh of VLSI System Design and I conducted our third “Microprocessor for You in Thirty Hours” (MYTH) Workshop, where participants learn about RISC-V and build their own RISC-V CPU cores (something that’s typically done over the course of a semester or two). In addition ...

PicoRio: the Raspberry Pi-like Small-Board Computer for RISC-V

by RISC-V International Open Source Laboratory Tsinghua-Berkeley Shenzhen Institute on Blog – RISC-V International 12 November 2020 15:11 UTC

By Zhangxi Tan, Lin Zhang, Yi Li, and David Patterson of the RISC-V International Open Source Laboratory Tsinghua-Berkeley Shenzhen Institute RISC-V, the royalty-free open-source alternative to proprietary instruction sets, is growing globally in popularity. This has led to many free and open-source processor designs, a free and open software stack and an international organization that maintains and promotes the instruction set. However, while key pieces of an open-source ecosystem for ...

Open Source Digital Library in HPC

by John Davis on Blog – RISC-V International 10 November 2020 15:00 UTC

This post was originally published on the MEEP (MareNostrum Exascale Emulation Platform) website. John Davis, MEEP project coordinator, explains how the European project MEEP will develop an open source digital library for the RISC-V ecosystem in HPC, its hardware and software developments and a performance modeling tool called Coyote. MEEP is a digital laboratory that enables us to build hardware that does not yet exist to test ideas on Hardware. It will be fast enough to enable software ...

El Correo Libre Issue 33

by Gareth Halfacree on LibreCores - Medium 10 November 2020 09:04 UTC

Matt Guthaus Showcases OpenRAM on SkyWater’s 130nm Process in FOSSi Dial-UpProfessor Matt Guthaus has offered an overview of OpenRAM, an open-source Python framework designed to handle the integration of static RAM (SRAM) into application-specific integrated circuit (ASIC) design, as part of the ongoing FOSSi Dial-Up video series. “I’ve been working on OpenRAM for actually quite a few years now,” Matt explained by way of introduction in the live video presentation, “and it’s turning into a ...

PolarFire SoC and RISC-V

by Antmicro on Blog – RISC-V International 09 November 2020 14:23 UTC

Hitting the market as the world’s first mass-produced, Linux-capable RISC-V implementation, PolarFire SoC FPGA turned heads among designers of computer systems who work with open processor architectures. This low-power, 4+1 core FPGA family with 23-461K logic elements from Microchip is becoming a major prototyping, research and experimentation platform for RISC-V-based solutions, allowing system designers to leverage its FPGA resources and the ability to run a plethora of Linux-based apps ...

Third Workshop on RISC-V Activities – It’s the ecosystem!

by RISC-V Community News on Blog – RISC-V International 02 November 2020 17:00 UTC

On Thursday October 8, the third Workshop on RISC-V Activities was hosted by edacentrum, due to the pandemic situation as an online workshop. First of all I have to say that with more than 230 registrations the workshop was very well attended. On the other hand, this comes not as a real surprise, since RISC-V is getting a lot of attention lately. Calista Redmond, RISC-V International CEO reported a tremendous 62% growth to now more than 750 RISC-V members across 50 countries – wow! What is ...

Fixing the ESD generator

by Fatsie on Chips4Makers.io 31 October 2020 23:00 UTC

This is a continuation on my previous blog on first tests on the ESD generator. Problems After some more debugging the voltage multiplier of the ESD Generator has been made to work. Detailed simulation results of the problems can be found in this Jupyter notebook in the created sim folder in the ESD Generator source folder. Summary of the problems: Leakage problem reported on in the previous blog post is mainly caused by the 10MΩ input impedance on the oscilloscope input not the diode ...

OTA: New srsLTE, Lime Suite, LuaRadio, GQRX, SDR#, and More

by Gareth Halfacree on MyriadRF 30 October 2020 09:14 UTC

The open-source srsLTE cellular communications suite has hit version 20.10, bringing new functionality including mobility functions and performance-enhancing PHY changes – and a range of bug-fixes, too. The srsLTE 20.10 release brings with it a new logging framework alongside initial NR PHY layer and stack components. The srsENB package receives Mobility – Intra eNB and S1 – functionality and RRC Re-establishment functionality, too, while the UE PHY layer is non-blocking and PHY ...

The Heart of RISC-V Development is Unmatched

by James Prior on SiFive 29 October 2020 15:30 UTC

Creating a RISC-V PC Ecosystem for Linux application development Today, SiFive introduces the new HiFive platform for professional RISC-V developers, the HiFive Unmatched! The HiFive Unmatched enables developers to create the RISC-V-based software they need for RISC-V platforms. From real-time operating systems to custom Linux distributions, and the compilers, libraries, and applications that go with product design, developers can use the HiFive Unmatched to natively test and build RISC-V ...

SiFive VIU75 Accelerates Vector Math

by Abhishek Jadhav on FOSSi – AB Open 28 October 2020 14:54 UTC

At the Linley Fall Conference 2020, SiFive Chief Architect and co-founder Krste Asanovic announced the RISC-V based VIU7 series. In that, the VIU75 CPU core is 64-bit, runs Linux, and supports “RV vector extension”. When it comes to RISC-V based core IP, SiFive has always dominated with new CPU IP with a huge portfolio. The RISC-V core VIU75 comes from the VI7 series and U cores. The VI7 series has a high-performance, 8-stage dual-issue in-order pipeline with an integrated vector unit, ...

RISC-V International Announces Agenda for the Third Annual RISC-V Summit

by Kim McMahon on Announcements – RISC-V International 26 October 2020 12:00 UTC

The leading RISC-V conference will be held virtually this year, featuring keynotes, tutorials, exhibitions, networking opportunities and more WHAT: The RISC-V International Association has announced the online program for the RISC-V Summit 2020. WHEN: Tuesday, Dec. 8 to Thursday, Dec. 10, 2020. WHERE: Register online here. DETAILS: RISC-V International will hold its third annual RISC-V Summit online from Dec. 8-10, 2020. The RISC-V Summit brings together innovators, academics and business ...

A birthday present for lowRISC: We won an OpenUK Award!

by lowRISC on lowRISC: Collaborative open silicon engineering 22 October 2020 12:00 UTC

On October 20th, lowRISC CIC won in the Open Hardware category at the 2020 OpenUK Awards, describing lowRISC as “the jewel in the crown of the UK’s open silicon companies”. The OpenUK awards promote “UK Leadership in Open Technology”, and are given out by OpenUK, a UK-based not-for-profit company which supports open source collaboration and open technologies within the United Kingdom. On receiving the award, lowRISC CTO, Alex Bradbury, said “We’re incredibly grateful to have been ...

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