Planet LibreCores

OTA: New LimeNET Gets AMD Ryzen Power, uSDR Launched, Open RAN Competition, and More

by Gareth Halfacree on MyriadRF
Lime Microsystems has announced a new version of its LimeSDR-powered LimeNET 5G-capable software-defined radio-network-in-a-box – now featuring a 16-core high-performance AMD Ryzen processor. “We are excited to collaborate with Lime Microsystems and the LimeNET ecosystem,” said AMD’s senior director of applications engineering Kun-Yip Liu of the project, “to enable innovative and high-performance 5G edge services running on AMD Ryzen and embedded processors.” “LimeNET powered by AMD leading ...

The 2021 RISC-V Summit Will Demonstrate Adoptions and Technical Advances This December in San Francisco

by Kim McMahon on Announcements – RISC-V International
ZURICH and SAN FRANCISCO – July 28, 2021 – RISC-V International announced the 2021 RISC-V Summit that will bring together the open hardware community for three days of deep technical talks, industry updates, networking, and more. The RISC-V Summit will be held at Moscone West in San Francisco from December 6-8, 2021, and will feature hybrid in-person and virtual activities to connect with a global audience. “Every year the RISC-V Summit draws larger crowds who gather with other RISC-V ...

Wavious Releases a RISC-V LPDDR4x/5 PHY as an Apache-Licensed Open-Source Project

by Gareth Halfacree on FOSSi – AB Open
Wavious, a fabless semiconductor company which offers a platform based on mix-and-match “chiplets,” has launched a RISC-V-powered open-source LPDDR4x/5 PHY – under the permissive Apache 2.0 licence. “We are strong believers in open-source hardware and software,” the company said in its announcement, “and Wavious is dedicated to making significant contributions to the open source community. Open-source HW [hardware] and chiplets are both necessary to remove barriers to entry and to drive ...

Life in a Formal Verification Lane | Shivani Shah

by Shivani Shah on Blog – RISC-V International
teaser image This summer, I got the opportunity to work as a Formal Verification Intern with Axiomise for six weeks. I’m a keen designer and love working in design and architecture. Although, I’ve not started my professional career yet, I have done most of my projects as a designer in my undergraduate and postgraduate studies. Having said that, I was always curious to know – how do we test that the design works? How is verification done in the industry? I had a prior design experience in building ...

What You Need to Know About Verilator Open Source Tooling | Rob Mains, CHIPS Alliance

by Rob Mains on Blog – RISC-V International
Verilator is a high performance, open source functional simulator that has gained tremendous popularity in its usage and adoption in the verification of chip design. The ASIC development community has widely embraced Verilator as an effective, often even superior alternative to proprietary solutions, and it is now the standard approach in RISC-V CPU design as the community has worked to provide Verilator simulation capabilities out of the box. CHIPS Alliance and RISC-V leaders Antmicro and ...

A Free RISC-V CPU Core Builder – Democratizing CPUs | Steve Hoover, Redwood EDA

by Steve Hoover on Blog – RISC-V International
teaser image There are now over a hundred RISC-V CPU cores listed in the RISC-V Exchange! Amazing. If you need a RISC-V CPU core, you’ll likely be able to find one that suits your needs… if you evaluate a hundred CPU cores to find it. Or, now, you can configure exactly the core you need, and have it built in seconds, for free! WARP-V is the most flexible RISC-V CPU core available, and recently, Indiana University student, Adam Ratzman, created an online configurator for WARP-V. If you need a ...

El Correo Libre Issue 40

by Gareth Halfacree on LibreCores - Medium
teaser image Google Summer of Code (GSoC) Class of 2021The FOSSi Foundation is happy to introduce our Google Summer of Code Class of 2021 projects. This year we are grateful that we have been granted eleven slots by Google to support projects and students. We are thankful for all mentors who volunteered to supervise students, and we’re looking forward to a great summer working together on Free and Open Source Silicon projects.Virtual FPGA Lab (Bala Dhinesh)Mentored by Kunal Ghosh, Ákos Hadnagy, and ...

FOSSi Foundation welcomes Jonathan Balkind on the board of directors

by FOSSi Foundation on FOSSi Foundation - News & Posts
The Free and Open Source Silicon Foundation is happy to announce today that Jonathan Balkind is joining the board of directors. Jonathan has been a trusted member of the FOSSi community for many years, where he has shown great skill in solving challenging technical problems, as well as teaching hardware design, and communicating the benefits of doing so openly. Jonathan is most well-known for his work on OpenPiton, an open source research processor which can be scaled up to multiple ...

RISC-V RV32I Assembly – Multiplication | Maven Silicon

by Maven Silicon on Blog – RISC-V International
This video shows how we can implement the Multiplication using add and shift RV32I instructions. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc.   To know more, explore our RISC-V courses. The post RISC-V RV32I Assembly – Multiplication | Maven Silicon appeared first on RISC-V International.

The Importance of Increasing Diversity in the Open Source Community

by Kim McMahon on Blog – RISC-V International
It’s no secret that the past twenty years has seen remarkable progress in technology innovation.  Smartphones opened up a whole new ecosystem of applications and possibilities, cars have become more connected and safer, and there are now RISC-V based software systems created to work in space! We’ve truly created a world that is unlike anything we’ve ever seen. As globalization promotes the exchange of ideas across borders, we’re continuing to reap the benefits of collaboration in our highly ...

NeuralScale: Industry Leading General Purpose Programmable NPU Architecture based on RISC-V

by Mark Zhan on Blog – RISC-V International
teaser image AI and its diverse applications have seen significant increasing demand for AI computing in clouds over the last few years. Typical AI-enabled services include image and speech recognition, natural language processing, medical diagnosis, visual search, and personalized recommendations. AI computing in clouds includes two distinct workloads: training and inference. AI inference is reported to constitute more than 95% of AI computing workloads in clouds.  Meanwhile, we have seen significant ...

A Process Independent Power Optimised Register File Architecture

by Tony Stansfield on Blog – RISC-V International
teaser image Overview This white paper describes how low-power memory technology, originally designed for large, high density, SRAMs has been enhanced and adapted to deliver low-power, low-voltage register files. Introduction There is a large, and growing, class of applications for which power is a critical factor, sometimes as a result of a desire to add increased functionality to already power-constrained devices, and in some cases where on-chip SRAM gives the most power efficient implementations. For ...

Wanxiang Blockchain Organized the First Public Activity of RISC-V Blockchain SIG with Partners

by Wanxiang Blockchain on Blog – RISC-V International
teaser image On June 24, during the RISC-V World Conference China 2021 hosted by ShanghaiTech University, Institute of Software Chinese Academy of Sciences, CRVIC, CRVA and CNRV, Wanxiang Blockchain, as one of the initiators of RISC-V Blockchain Special Interest Group (SIG), organized a Blockchain + RISC-V Forum and Workshop. The RISC-V Blockchain SIG, jointly established in February 2021 by Wanxiang Blockchain, ...

OTA: OpenBSC Setup Scripts, 80MSPS from a LimeSDR Mini, a Satellite Hunt, and More

by Gareth Halfacree on MyriadRF
Community member Bastien Baranoff has shared scripts for getting a Raspberry Pi system running Ubuntu Server up-and-running as an open cellular base station with Osmocom’s OpenBSC and a LimeSDR. Designed for Raspberry Pi systems running Canonical’s free and open source Ubuntu Server Linux distribution, Bastien’s scripts begin by installing the necessary software for turning a LimeSDR software-defined radio into a cellular base station. The first script automates the installation of ...

Version 3.9.0 released

by Esko Pekkarinen on Kactus2: News
New PythonAPI for accessing Kactus2 data+ New interfaces for IP-XACT data read and modify+ Generator runs for selected generators e.g. Verilog New Python console in graphical user interface+ Run interactive scripts+ View command history+ Save and run script files Kactus2 editors adapted to new interfaces+ Ports+ Parameters+ Fields+ Field resets+ Registers+ Address block+ Memory maps+ Files+ File sets+ Component instantiations+ Port maps+ Port abstractions+ Bus interfaces Added ...

GSoC Class of 2021

by FOSSi Foundation on FOSSi Foundation - News & Posts
The FOSSi Foundation is happy to introduce our Google Summer of Code Class of 2021 projects. This year we are grateful that we have been granted eleven slots by Google to support projects and students. We are thankful for all mentors who volunteered to supervise students, and we’re looking forward to a great summer working together on Free and Open Source Silicon projects. These projects are our “GSoC Class of 2021”. Please give our students a warm welcome! Virtual FPGA Lab (Bala ...

RISC: Open Hardware

by David Patterson on Blog – RISC-V International
Peggy and David Patterson, pardee professor of computer science, Emeritus, University of California at Berkeley, talk about RISC and how it brings openness to hardware design. He says in the beginning ease of use was the top priority with technology, and now we are paying the price with security. They also discuss: Why testing can reveal the presence of bugs but can’t reveal the absence of bugs. How RISC lets someone do security themselves. How to inspire the next ...

The Heart of SiFive is Performance, Intelligence, & Essential

by Patrick Little on SiFive
teaser image Introducing the new era of SiFive Performance for RISC-V When I joined SiFive last year, I found a dedicated team working on great technology with a vision to do no less than to change the world. As I talked to our customers and partners, it was clear that while we had satisfied users, the industry expected and desired greater things from SiFive. The message was loud and clear that SiFive needed to push the boundaries of what’s possible to bring high value, differentiated products to ...

Embedded Programming and IoT – Memory Management Criticality!

by Tan Rahman on Blog – RISC-V International
teaser image There are two types of IoT devices: high-end devices and low-end devices. The operating systems that are used for high-end devices include fully functional ones like Windows, Linux or Android. For example, Amazon’s echo device uses Fire OS based on Android whilst Samsung smartwatches use Tizen based on Linux. These devices are wired for power or have batteries that are regularly charged. However, low-end devices have a very small amount of memory and work with a low amount of energy often ...

RISC-V QEMU Part 1: Privileged ISA v1.10, HiFive1 and VirtIO

by Michael Clark on SiFive
This post covers recent development in RISC-V QEMU, the open source machine emulator and virtualizer. We’ve been playing a game of catch-up with the hardware folks so that we can match the capabilities of the Freedom U500 SDK. We’re not quite there yet, but we’ve made some important improvements that will allow for a more usable emulator. First, some background on software emulation of Instruction Set Architectures. There are several forms of emulators and they fall broadly into these ...

All Aboard, Part 10: How to Contribute to the RISC-V Software Ecosystem

by Palmer Dabbelt on SiFive
We recently announced the HiFive Unleashed, a development board for Freedom U540-C000, the world's first Linux-capable RISC-V ASIC. The announcement of this board roughly lined up with the first upstream releases of Linux and glibc that contain RISC-V support. As a result, our news has driven a lot of interest from the open source software community -- that was really the whole point of announcing the board in the first place, so in that sense it's working out very well. This new wave of ...

SiFive’s Approach to Embedding Intelligence Everywhere

by Tom Simon on SiFive
teaser image Published by SemiWiki. Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made over many years. RISC-V was conceived with a clean well-thought-out architecture and designed for expansion that would not create inconsistencies. Because it is open source, there is a rich set of ...

The SiFive 20G1 Update for 7-Series Core IP

by Drew Barbier on SiFive
Faster, More Efficient SiFive 7-Series Core IP Today, we’re announcing the SiFive 20G1 6.0 update, which is focused on improving the 7-Series line of products. Our previous release, SiFive 20G1, was a comprehensive update that spanned from the 7-Series to the 2-Series, including U-, S-, and E-Cores. Similarly, the 20G1 6.0 update improves the performance, features, and functionality of SiFive 7-Series U-, S-, and E-Cores. Ever since the 7-Series introduction in 2018, SiFive has been able to ...

All Aboard, Part 2: Relocations in ELF Toolchains

by Palmer Dabbelt on SiFive
Our first stop on our exploration of the RISC-V toolchain will be an overview of ELF relocations and how they are used by the RISC-V toolchain. We'll shy away from discussing linker relaxations and their impact on performance for a follow-up blog post so this doesn't get too long. The example has been carefully constructed to be unrelaxable as to avoid confusion. Additionally, we're only going to discuss the relocations used by statically linked executables, avoid discussing position ...

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part I

by Camille Kokozaki on SiFive
teaser image SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing, Calista Redmond was just appointed the new CEO of the RISC-V Foundation). He shared a slide showing the growing RISC-V ecosystem from tools vendors, to IP/semi chip ...

All Aboard, Part 1: The -march, -mabi, and -mtune arguments to RISC-V Compilers

by Palmer Dabbelt on SiFive
Before we can board the RISC-V train, we'll have to take a stop at the metaphorical ticket office: our machine-specific GCC command-line arguments. These arguments all begin with -m, and are all specific to the RISC-V architecture port. In general, we've tried to match existing conventions for these arguments, but like pretty much everything else there are enough quirks to warrant a blog post. This blog discusses the arguments most fundamental to the RISC-V ISA: the -march, -mabi, ...

All Aboard, Part 9: Paging and the MMU in the RISC-V Linux Kernel

by Palmer Dabbelt on SiFive
This entry will cover the RISC-V port of Linux's memory management subsystem. Since the vast majority of the memory management code in Linux is architecture-independent, the vast majority of our memory management code handles interfacing with our MMU, defining our page table format, and interfacing with drivers that have memory allocation constraints. I will refrain from discussing the RISC-V memory model in this blog, both because it isn't yet finished and because it's complicated ...

All Aboard, Part 3: Linker Relaxation in the RISC-V Toolchain

by Palmer Dabbelt on SiFive
Last week's blog entry discussed relocations and how they apply to the RISC-V toolchain. This week we'll be delving a bit deeper into the RISC-V linker to discuss linker relaxation, a concept so important it has greatly shaped the design of the RISC-V ISA. Linker relaxation is a mechanism for optimizing programs at link-time, as opposed to traditional program optimization which happens at compile-time. This blog will follow an example linker relaxation through the toolchain, demonstrate an ...

All Aboard, Part 4: The RISC-V Code Models

by Palmer Dabbelt on SiFive
The RISC-V ISA was designed to be both simple and modular. In order to achieve these design goals, RISC-V minimizes one of the largest costs in implementing complex ISAs: addressing modes. Addressing modes are expensive both in small designs (due to decode cost) and large designs (due to implicit dependencies). RISC-V only has three addressing modes: PC-relative, via the auipc, jal and br* instructions. Register-offset, via the jalr, addi and all memory instructions. Absolute, via the lui ...

Part 3: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

by Shubu Mukherjee on SiFive
teaser image This is the third in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in system-on-chip (SoC) designs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance. Part #2 addressed the challenges associated with point-to-point ordering between cores and DSA ...

All Aboard, Part 7: Entering and Exiting the Linux Kernel on RISC-V

by Palmer Dabbelt on SiFive
Continuing our journey into the RISC-V Linux kernel port, this week we'll discuss context switching. Context switching is one of the more important parts of an architecture port: it is all but impossible to completely abstract away the details of entering and exiting the kernel, Since this is on many critical paths (system calls and scheduling) it must go fast, but since it's the one line of protection the kernel has from userspace it must also be secure. Traps on RISC-V Systems One of the ...

All Aboard, Part 6: Booting a RISC-V Linux Kernel

by Palmer Dabbelt on SiFive
This post begins a short detour into Linux land, during which we'll be discussing the RISC-V Linux kernel port. SiFive has recently announced the Linux-capable U54-MC RISC-V Core IP, and our Linux port was recently submitted to linux-next, Linux's staging branch, so assuming that everything goes smoothly we should be merged at the end of the next merge window. Along with Linux we should soon have the full suite of core system components upstream, both for embedded systems (via binutils, ...

Dhrystone Performance Tuning on the Freedom Platform

by Fu-Ching Yang on SiFive
teaser image For consumers of low-end processors, the Dhrystone benchmark can be a valuable tool for estimating performance. Due to the nature of the Dhrystone benchmark, high-end Application Processor performance is incompletely represented by a Dhrystone score. For processor providers a Dhrystone score is a commonly used metric for instruction throughput comparison in early stage evaluation. To fairly compare Dhrystone scores, the test conditions must be published. To that end SiFive offers two ...

Last Week in RISC-V: October 19, 2018

by Palmer Dabbelt on SiFive
It's been another week, which means it's time to find another host for "Last Week in RISC-V". This week we're going to attempt a blog at riscv.org, which will hopefully be a good long-term home for this series of articles. As usual, you can find this week's entry on GitHub. glibc Floating-Point Test Suite As part of the RV32I glibc submission process, Zong from Andes has submitted a glibc patch set to fix a generic floating-point bug that crosses the boundary between GCC and glibc. ...

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part II

by Camille Kokozaki on SiFive
teaser image During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded Processors, and E Cores 32-bit Embedded Processors. Embedded intelligence allows mixing of application cores with embedded cores, extensible custom instructions, ...

The Design Revolution in APAC and Australia

by Aijaz Qaisar on SiFive
teaser image Highlights From the SiFive Tech Symposiums In its endeavor to educate the tech world about the benefits of the RISC-V ISA, SiFive just completed its APAC and Australia series of tech symposiums. Throughout the month of June, symposiums were held in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney. The audience included academia, the business industry, and many RISC-V ecosystem partners. On average, in all seven cities, 60% of the audience came from the tech industry and 40% belonged to ...

SiFive Strengthens Foothold in Storage Applications for Data-Centric AI Computing

by James Prior on SiFive
teaser image SiFive RISC-V processors are powering flash drives in production as well as addressing emerging In-Storage Computing (ISC) needs In the current digital age, where data powers increasing levels of decision-making, industrial control and automation, efficient data storage, movement, and processing become the focal point of technological innovations in silicon, system, and software. At SiFive, we have been designing and optimizing RISC-V based domain-specific solutions to address the ...

Last Week in RISC-V: Sept 28, 2018

by Palmer Dabbelt on SiFive
I spent too much time writing my single entry this week so it's all I have. The issue itself is somewhat complex, so I thought it warranted a deep dive. Relaxing R_RISCV_PCREL_* in the Presence of Addends Jim recently found an issue with our ELF relocation scheme. While technically it's a somewhat wide-ranging ABI bug, the actual set of cases in which the issue will manifest is somewhat restricted -- in other words: while I'm sure the proper long-term fix for this will be quite involved, ...

Last Week in RISC-V: August 31, 2018

by Palmer Dabbelt on SiFive
Welcome to the first issue of "Last Week in RISC-V", a weekly newsletter tracking the RISC-V community. This newsletter was born out of a discussion in SiFive's internal RISC-V software team and I'm compiling it so it'll have a somewhat heavy focus on the open source software community for now as that's where I spend most of my time. The general idea behind "Last Week in RISC-V" is that the RISC-V ecosystem is getting big enough that it's impossible for any single person to ...

Embedded Intelligence Everywhere

by Jack Kang on SiFive
teaser image In 2018, we saw the rapid proliferation of the RISC-V architecture, with commercial deployments of SiFive Core IP in a broad range of applications ranging from wearables and edge devices to the enterprise core. Modern compute workloads are evolving rapidly and require the ability to scale performance on demand and very often have real-time, deterministic requirements. This diversity of workloads poses computational challenges that can be resolved only by domain-specific architectures. With ...

With SiFive, We Can Change the World

by Chris Lattner on SiFive
A Note from Chris Lattner, New SVP of Platform Engineering My quest is to build beautiful things that help change the world, and I’ve been fortunate to spend the last 15 years in Silicon Valley, working with some of the major players shaping all sorts of technology. Today, I’m super excited to join SiFive - the company I believe is best positioned to transform the silicon industry, to lead the Platform Engineering team. With experience building and leading large-scale production systems ...

Last Week in RISC-V: Sept 14, 2018

by Palmer Dabbelt on SiFive
GNU Tools Cauldron Trip Report, Part 2 I was at the GNU tools cauldron last week. I summarized the two BoF sessions in last week's entry. While that was the extent of the RISC-V specific events at the cauldron, I attended the remainder of the cauldron where there were some great sessions. Vector ABI I attended the aarch64 BoF session, where one of the major issues at hand is to implement a system ABI that allows argument passing via SVE registers. This brought up a mirror in RISC-V land: ...

Introducing the U54-MC RISC-V Core IP – The First RISC-V Core with Linux Support

by Jack Kang on SiFive
Since we launched the industry’s first open-source RISC-V SoC back in July of last year, we’ve had the pleasure of pushing the boundaries of the RISC-V ecosystem and have been delighted by the support that SiFive – and RISC-V – has gained from system designers and Makers alike. Today, we are proud to announce we have taken the next step in our journey to deliver custom silicon to everyone who needs it. Introducing the U54-MC RISC-V Core IP, the industry’s first RISC-V based, 64-bit, ...

SiFive Core IP 21G1

by Graham Wilson on SiFive
The best just got better--SiFive’s latest Processor Core IP Portfolio release We’re pleased to announce a comprehensive update to SiFive’s RISC-V Core IP Portfolio with the SiFive 21G1 release. This release brings important enhancements and new capabilities to SiFive® Core IP, the industry's broadest RISC-V IP Portfolio, ranging from the ultra-capable SiFive U7-Series to the extremely popular SiFive E2-Series, offering up to 35% more performance for bit processing algorithms; and up to 25% ...

All Aboard, Part 5: Per-march and per-mabi Library Paths on RISC-V Systems

by Palmer Dabbelt on SiFive
A previous blog described how the -march and -mabi command-line arguments to GCC can be used to control code generation for the sources you compile as a user, but most programs require linking against system libraries in order to function correctly. Since users generally don't want to compile every library along with their program, either because they're too complicated or because they're meant to be shared, a mechanism is needed for linking against the correct set of system libraries to ...

When Hardware Roadmaps Look Like Software Roadmaps

by Drew Barbier on SiFive
The traditional cadence for microarchitecture updates is usually tied to process technology nodes or ground-up redesigns. The SiFive Core IP portfolio offers scalable microarchitectures from efficient application multi-core processors capable of running Linux, to tiny, power-sipping cores suitable for the most area constrained design points. The SiFive quarterly update program delivers key improvements, new features, and more capabilities to SiFive Core IP in a measured, methodical way. ...

Andy Hopper knighted for services to Computer Technology

by lowRISC on lowRISC: Collaborative open silicon engineering
lowRISC is delighted that Andy Hopper, lowRISC’s independent chair, has been knighted for services to Computer Technology. Andy said “As you might imagine I am delighted. What I have achieved is all a result of teamwork. The University of Cambridge and the Cambridge Cluster have provided a wonderfully collaborative and flexible environment within which I have had the good fortune to work for over 40 years.” The culture he created, and his interest in and support for doing things ...

RISC-V SIG-HPC Enabling RISC-V in HPC, Supercomputers to the Edge, and Emerging AI/ML/DL HPC Workloads

by John Davis on Blog – RISC-V International
RISC-V was first deployed as a microcontroller or embedded processor. However, in the future, the RISC-V ISA can also power the most powerful computers as processors and accelerators. In order to do that, the ISA must have features and an ecosystem to support HPC and these features are different from what is defined as an embedded system, where the RISC-V ISA first got traction.  The RISC-V Special Interest Group on High Performance Computing (SIG-HPC) was formed to address the requirements ...

El Correo Libre Issue 39

by Gareth Halfacree on LibreCores - Medium
teaser image European Processor Initiative Tapes-Out First EPAC RISC-V Test ChipThe European Processor Initiative (EPI), a joint project of 28 partners looking to produce European Union-native high-performance computing (HPC) technologies and infrastructure, has announced a milestone: the tape-out of its first RISC-V test chip, EPAC1.0. “I am really happy how partners with different backgrounds and motivations have been able to collaboratively develop this chip, putting all their efforts towards a ...

Getting Started with Zephyr RTOS v1.13.0 On RISC-V

by Nathaniel Graff on SiFive
teaser image Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architectures, and targets including SiFive's E-series CoreIP, and the HiFive 1 development board. I'm particularly excited about this release because it incorporates recent work making the RISC-V port of ...

RISC-V RV32I RTL Architecture | Maven Silicon

by Maven Silicon on Blog – RISC-V International
This video explains the RTL architecture of an RV32I RISC-V processor. Also, it shows how we can create the RISC-V RTL using basic building blocks like the adder, decoder, memory, register, multiplexer, and control logic. Follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. The post RISC-V RV32I RTL Architecture | Maven Silicon ...

The Zephyr Project Celebrates 5th Anniversary with new members and inaugural Zephyr Developer Summit on June 8-10

by RISC-V Community News on Blog – RISC-V International
“RISC-V and Zephyr were both designed to drive innovation in the hardware space with open source technologies that are accessible to everyone,” said Mark Himelstein, CTO of RISC-V. “Many of our members are already taking advantage of the flexibility of RISC-V and Zephyr to design end-to-end open source solutions for resource-constrained devices. We look forward to collaborating with the Zephyr Project to offer even more opportunities for the open source community to innovate.” Click to read ...

Antmicro Open Source Portal launched

by Antmicro on Blog – RISC-V International
teaser image Antmicro was founded on the belief that open source can dramatically accelerate technological progress by enabling collaboration, transparency and freedom to customize, improve and combine various solutions, unlocking system design possibilities that would be otherwise unavailable. For more than a decade we’ve been providing commercial support and engineering services around open source software and hardware to our customers, building cutting-edge computer systems for industries such as ...

New Open Source Contributor Model: RISC-V Development Partners

by Kim McMahon on Blog – RISC-V International
teaser image The growth of RISC-V is built on the collaborative efforts of the individuals and organizations in the technical community. Our continued progress relies on the dedication and investment that make such contributions possible. RISC-V is incredibly grateful for the investments each of our members make in furthering the success of RISC-V, and in particular, the comprehensive dedication provided by organizations to take on specific technical missions. In appreciation of the efforts of our ...

OTA: LimeRFE Shipping Begins, LibreCellular Launches, OpenWifi, and More

by Gareth Halfacree on MyriadRF
Lime Micro has announced that the first batch of LimeRFE boards has now been shipped to Crowd Supply, with all backers’ orders expected to be fulfilled by the end of June. Designed to bring the same flexibility as the LimeSDR range to the radio-frequency front-end field, the programmable LimeRFE promises to give any LimeSDR project a stronger, clearer signal for transmission, reduced noise for reception, and improved range for both. Now, after a last delay driven by the COVID-19 pandemic, ...

Google Summer of Code 2021

by OpenRISC Community on OpenRISC
The Google Summer of Code is a yearly event which teams open source projects with college students. Students learn about technology and the open source community and projects benefit from new contributions. As in previous years this year OpenRISC is participating as part of the FOSSi foundation project. This year we the pleasure of working with a talented student Harshita S (@Harshit49678822) on formally verifying the mor1kx OpenRISC cpu implementation. Harshita has already started ...

Awards Season Brings Big Surprises

by Jack Kang on SiFive
It’s that time of year again--awards season, the time when companies submit their best-of-year products and initiatives for consideration by industry watchers and judging panels. It’s a familiar, fairly predictable cycle, but sometimes it can take one by surprise. When UBM announced the finalists for the Annual Creativity in Engineering (ACE) awards earlier this month everyone at SiFive was proud to see that the team behind our HiFive1 development board was shortlisted as a finalist for ...

NLnet018TV Measurement Report

by Fatsie on Chips4Makers.io
teaser image Almost a year ago I reported on the NLnet018TV test chip design for my NLnet project. I did have verification measurements of the chip available now for several weeks but because of the Libre-SOC prototype tape-out taking all of my time I did not find time and motivation to summarize the measurements for this blog up to now. The test chip was manually wirebonded in 85-pin PGA package using Europractice's standard packaging services through imec as can be seen in the following picture: For ...

Coming June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!

by Kim McMahon on Blog – RISC-V International
teaser image The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events – providing technical content to the RISC-V community for free! If you joined us for our forum on Security, you were one of 700 (!) people that registered for the event and maybe one of the nearly 2,000 (!!) people that watched the content on our YouTube channel.  It’s wonderful to see so much interest! The schedule for the Developer Tools and Tool ...

RISC-V RV32I Instructions Format | Maven Silicon

by Maven Silicon on Blog – RISC-V International
This video explains all RV 32I Instruction formats, R, I, S, B, J, and U types, and how it simplifies the instruction decoder logic. Follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. The post RISC-V RV32I Instructions Format | Maven Silicon appeared first on RISC-V International.

What's happing in the open silicon ecosystem around you? Planet LibreCores helps you to get the latest news from all corners of the community by aggregating blog posts.

All content here is unfiltered and uncensored, and represents the views of the post authors. Individual posts are owned by their authors; please see the original source for licensing information.

Subscribe to Planet LibreCores

In addition to reading the posts here, you can subscribe to Planet LibreCores in your favorite feed reader.

Planet Librecores Atom feed

Or get the subscription list through FOAF or OPML.

Last updated 01 August 2021 19:30 UTC