Planet LibreCores

OTA: Kimera Video Transmission, GNU Radio for Android, QO-100 QSO, and More

by Gareth Halfacree on MyriadRF
Community member Luigi Cruz has published a tool which is capable of encoding any video source, complete with hardware acceleration, and transmitting it over the airwaves using a LimeSDR. “Kimera can capture any camera connected to your computer, hardware encode it with any codec available (e.g. HEVC, AVC, AV1), and transmit over TCP, UNIX Socket, or this GNU Radio Transport Layer,” Luigi writes of his latest software release. “On the receiver, it will decode and emulate a native ...

El Correo Libre Issue 27

by Gareth Halfacree on LibreCores - Medium
teaser image Google Summer of Code Class of 2020The FOSSi Foundation is happy to announce that we have been granted eight slots by Google to support projects and students for another year’s edition of Google Summer of Code. We are thankful for all mentors who volunteered to supervise students, and we’re looking forward to a great summer working together on Free and Open Source Silicon projects. These projects are our “GSoC Class of 2020”. The students will introduce themselves over the coming days to ...

The Eclipse Foundation Announces a Move to Europe to Boost Growth

by Gareth Halfacree on FOSSi – AB Open
The Eclipse Foundation, which acts as a not-for-profit steward of the Eclipse open source software development community working on projevts as diverse as edge computing, artificial intelligence, and free and open source silicon, has announced it is moving to Europe – a move which it says will enable it to better foster international growth and collaboration. ”Over the last several years, the Eclipse Foundation has grown its membership with technology leaders from around the world, ...

Python Verification Stimulus and Coverage: Constraints

by Matthew Ballance on Bits, Bytes, and Gates
Over the past few blog posts, we've looked at:The fundamentals of modeling stimulus and functional coverage in PythonModeling verification data types in PythonModeling and capturing functional coverage in PythonMaking use of captured coverage dataIn this post, we will look at how to model constraints in Python using the PyVSC library. Several libraries that I'm familiar with (mostly C++) provide

SiFive In The Time of COVID-19

by Naveed Sherwani on SiFive
A Message From The CEO Innovation in SiFive’s product portfolio and business model differentiates our company, but the employee team is the heart of our success. SiFive employees enable our company to offer the full idea-to-silicon journey, from configurable processor cores with comprehensive pre-integrated security, trace and debug capabilities, and modern SoC IP, to scalable chip manufacturing development and management using a broad range of foundries and process technologies. To support ...

GSoC Accepted Projects Announcement

by Sam Elliott and Pirmin Vogel on lowRISC: Collaborative open silicon engineering
We are pleased to announce that we will be mentoring two students as part of Google Summer of Code (GSoC). We are looking forward to working with Flavien and Yuichi on features and tools to improve IP such as Ibex, our open-source RISC-V core. Flavien Solt: Simulated Memory Controller It is a common pitfall to misinterpret or incorrectly scale performance numbers derived from benchmarks run on an FPGA-based SoC design. The problem is that the external memory interface is running at a ...

GSoC Class of 2020 announced

by FOSSi Foundation on FOSSi Foundation - News & Posts
The FOSSi Foundation is happy to announce that we have been granted eight slots by Google to support projects and students for another year’s edition of Google Summer of Code. We are thankful for all mentors who volunteered to supervise students, and we’re looking forward to a great summer working together on Free and Open Source Silicon projects. These projects’s are our “GSoC Class of 2020”. The students will introduce themselves over the coming days to the various projects, please give ...

Verilator - Verilator 4.034 Released

by Wilson Snyder on Veripool: News
Verilator 4.034 2020-05-03 Add simplistic class support with many restrictions, see manual, #377. Support IEEE time units and time precisions, #234. Includes `timescale, $printtimescale, $timeformat. VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed and the time precision must now match the SystemC time precision. To get closer behavior to older versions, use e.g. --timescale-override "1ps/1ps". Add --build to ...

SiFive’s Approach to Embedding Intelligence Everywhere

by Tom Simon on SiFive
teaser image Published by SemiWiki. Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made over many years. RISC-V was conceived with a clean well thought out architecture and designed for expansion that would not create inconsistencies. Because it is open source, there is a rich set of ...

Last Week in RISC-V: Sept 28, 2018

by Palmer Dabbelt on SiFive
I spent too much time writing my single entry this week so it's all I have. The issue itself is somewhat complex, so I thought it warranted a deep dive. Relaxing R_RISCV_PCREL_* in the Presence of Addends Jim recently found an issue with our ELF relocation scheme. While technically it's a somewhat wide-ranging ABI bug, the actual set of cases in which the issue will manifest is somewhat restricted -- in other words: while I'm sure the proper long-term fix for this will be quite involved, ...

Python Verification: Working with Coverage Data

by Matthew Ballance on Bits, Bytes, and Gates
Before jumping into this week's post, I wanted to offer a bit of an apology to my readers. I recently realized that, despite being a Google property, Blogger only notifies authors of comments for moderation if the author has specifically registered a 'moderator' email with the site. So, apologies to those of you that have commented on posts directly on the Blogger site and watched those

OTA: Portsdown LimeSDR USB Support, DragonOS and PiSDR Updated, and More

by Gareth Halfacree on MyriadRF
The British Amateur Television Club’s Portsdown digital TV transmitter project now supports the LimeSDR USB open software-defined radio, in addition to its earlier compatibility with the smaller LimeSDR Mini and all-in-one LimeNET Micro. Detailed over on the Lime Micro Community Hub, the Portsdown project offers radio amateurs an easy route into digital TV transmission. In its original incarnation, the Portsdown was based around a Raspberry Pi single-board computer and a LimeSDR Mini ...

El Correo Libre Issue 26

by Gareth Halfacree on LibreCores - Medium
teaser image Google Summer of Code 2020Since 2016 the FOSSi Foundation has participated every year in the Google Summer of Code, a Google-sponsored summer internship for students from all over the world. We are honoured to be part of GSoC again this year. As in previous years, the FOSSi Foundation acts as an umbrella organization, supporting community members to mentor students in their respective FOSSi-related projects. Today, the student applications closed, and we’ll hopefully soon be able to ...

SiFive Connect : SiFive in Virtual World-Webinar Series

by Swamy Irrinki on SiFive
teaser image A Platform Designed for Continued Engagement with the Global Hardware and Software Community Developing RISC-V Based Semiconductor Solutions. After hosting the SiFive Tech Symposiums in a record 52 cities in 2019, it became amply evident that the RISC-V revolution has reached all corners of the globe and is here to stay. RISC-V cores are being designed into many SoCs and domain-specific custom silicon. To take our previous engagement with the global community to the next level, we’re ...

Python Verification Stimulus and Coverage: Functional Coverage

by Matthew Ballance on Bits, Bytes, and Gates
In my last two posts (here and here), I've been talking about modeling random stimulus, constraints, and functional coverage in Python. After looking at the fundamentals of capturing the specifics of data types such that they can be used for hardware verification last week, lets look at using those data types for modeling functional coverage. As I mentioned last week, I'm using this series

Celebration of IoT Day 2020: How Open Hardware & Software Is Stimulating IoT Innovation

by Jeffrey Osier-Mixon on Events – RISC-V International
teaser image In the last year, we have seen the internet of things (IoT) significantly grow globally with the market showing no signs of slowing down. Today an increasing number of devices are connected, from consumer electronics to household appliances and vehicles. Commercial adoption of the IoT in the manufacturing, logistics and transportation fields is also at an all-time high. Business Insider Intelligence forecasts that there will be more than 64 billion IoT devices installed around the globe by ...

Special Edition: Embedded World 2020 – UltraSoC

by Jeffrey Osier-Mixon on Events – RISC-V International
Ensuring systems do what they were designed to do, safely and securely Andy Gothard, Director of Marketing, UltraSoC On-chip monitoring is vital to understand what’s happening in real life, not only in the chip but throughout the system. Andy describes, how, by using UltraSoC’s embedded analytics, to improve performance, reliability and importantly, security, UltraSoC’s hardware IP can help solve increasingly complex system level problems. These problems are increasingly too difficult for ...

Python Verification Stimulus and Coverage: Data Types

by Matthew Ballance on Bits, Bytes, and Gates
In my last post, Modeling Random Stimulus and Functional Coverage in Python, I introduced a Python library for modeling random variables, constraints, and functional coverage. Starting with this post, I'll go through several aspects of the PyVSC library in greater detail. In this post, I'll cover the data types supported by PyVSC. There are two reasons for doing this. For one thing, I

Verilator - Verilator 4.032 Released

by Wilson Snyder on Veripool: News
Verilator 4.032 2020-04-04 Add column numbers to errors and warnings. Add GCC 9-style line number prefix when showing source text for errors. Add setting VM_PARALLEL_BUILDS=1 when using --output-split, #2185. Change --quiet-exit to also suppress 'Exiting due to N errors'. Suppress REALCVT for whole real numbers. Support split_var in vlt files, #2219. [Marco Widmer] Fix parameter type redeclaring a type, #2195. [hdzhangdoc] ...

The RISC-V Revolution is Going Strong in Ahmedabad

by Shivaram Venkatesh Nellaiappan on SiFive
teaser image As part of our ongoing effort to spread knowledge about the RISC-V ISA around the globe, we hosted a two-day long RISC-V Symposium/Workshop in the ancient city of Ahmedabad, India. The event was co-hosted by Nirma University at their campus at Ahmedabad. The first day of the event was the symposium portion, and it was attended by students of various universities, research scholars, and many prominent industrial experts from Ahmedabad. Anand Bariya, VP of engineering at SiFive, delivered a ...

Your input is needed for the Cocotb User Survey 2020!

by FOSSi Foundation on FOSSi Foundation - News & Posts
Are you a cocotb user? Then please help out by taking 10 minutes to fill out this year’s cocotb user survey. This survey gives the development community important feedback to steer future of cocotb into the right direction for your use case. Take the cocotb user survey now! cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. It is a community-driven project under the stewardship of the FOSSi Foundation. Cocotb is free to download, ...

Google Summer of Code 2020

by FOSSi Foundation on FOSSi Foundation - News & Posts
Since 2016 the FOSSi Foundation has participated every year in the Google Summer of Code, a Google-sponsored summer internship for students from all over the world. We are honored to be part of GSoC again this year. As in previous years, the FOSSi Foundation acts as an umbrella organization, supporting community members to mentor students in their respective FOSSi-related projects. Today, the student applications closed, and we’ll hopefully soon be able to announce a list of students who ...

Favor Composition Over Inheritance - Even for Constraints

by Tudor Timi on Verification Gentleman
teaser image Simulation is currently the dominant functional verification technique, with constrained random verification the most widely used methodology. While producing random data is a big part of it, letting the solver blindly generate stimulus isn't going to be very efficient. Constraints are needed to guide the stimulus toward interesting scenarios.A good constrained random test suite contains a mixture of tests with varying degrees of randomness. This is achieved by progressively adding ...

Modeling Random Stimulus and Functional Coverage in Python

by Matthew Ballance on Bits, Bytes, and Gates
If you've been following the blog over the last year, you've probably noticed that I've spent quite a bit of time over the last year learning and using Python. For several reasons, it's become my new favorite programming language. Until recently, I've mostly used Python as an implementation language. However, I've been curious as to how well Python works for implementing an embedded

OTA: DreamCatcher’s Lab Kit, LuaRadio 0.6.1, Antenna Simulation, and More

by Gareth Halfacree on MyriadRF
Technical training specialist DreamCatcher has launched a training course with LimeSDR-powered lab kit, designed to teach university-level students Long Term Evolution (LTE) network concepts. “The ME1130 serves as a ready-to-teach package for in-depth understanding and hands-on experience on LTE and LTE-Advanced technologies,” DreamCatcher explains of the hardware that backs the course. “The PC-based implementation of LTE’s eNodeB [Evolved Node B] and EPC [Evolved Packet Core] is a powerful ...

Collaboration, Inspiration and Progressive RISC-V Based Innovation in India and Bangladesh is Increasing at a Steady Pace

by Aijaz Qaisar on SiFive
teaser image Our SiFive Tech Symposiums and Workshops in India and Bangladesh were a huge success, and an inspirational endeavor as well. We hosted events in six cities total, including symposiums in Noida/Delhi, Pune, Bangalore and Hyderabad, and workshops in Chennai and Bangladesh’s capital city of Dhaka. Attendance was at capacity in all locations, and was over capacity in Pune and Bangalore. Highlights From India Our co-hosts in India – Western Digital, Microchip and IIT Madras – delivered powerful ...

NVDLA Deep Learning Inference Compiler is Now Open Source

by on SiFive
teaser image Designing new custom hardware accelerators for deep learning is clearly popular, but achieving state-of-the-art performance and efficiency with a new design is a complex and challenging problem. Two years ago, NVIDIA opened the source for the hardware design of the NVIDIA Deep Learning Accelerator (NVDLA) to help advance the adoption of efficient AI inferencing in custom hardware designs. The same NVDLA is shipped in the NVIDIA Jetson AGX Xavier Developer Kit, where it provides ...

Israel is Evolving as a High-Tech Hub, and RISC-V is Playing a Vital Role

by Aijaz Qaisar on SiFive
teaser image Israel, and specifically the city of Tel Aviv, is said to have one of the highest densities of startups per capita in the world. At our SiFive Tech Symposium, we heard from some of the brightest minds residing at the epicenter of this high-tech hub. They shared their visions for the industry as well as their contributions to the semiconductor ecosystem via RISC-V based solutions. This is the second year in a row that we’ve hosted the SiFive Tech Symposium is Israel. With our partners, ...

Supporting A World Leading RISC-V IP Portfolio

by Drew Barbier on SiFive
teaser image The second SiFive quarterly engineering release has arrived, and includes some great new Trace & Debug features. Static source code analysis may not offer a complete view of real world operation. Real time analysis enabled via tracing permits a deeper insight into the interactions of software and hardware to accelerate development, debug, validation of modern, configurable SoC designs. A major focus of the Q3 Engineer Update was adding support for Nexus 5001™ compliant instruction trace. ...

Cloud Accelerated Idea To Silicon

by Chris Lattner on SiFive
teaser image The SiFive Mission SiFive’s mission is to accelerate chip design, closing the time between the definition of a chip to silicon being available - we call this the ‘idea to silicon' journey. The solutions to modern computing challenges increasingly require domain-specific accelerators, silicon chips designed to solve a focused problem with built-in adaptability to provide flexibility for shifting workloads. Today, Synopsys announced that SiFive has selected Synopsys Fusion Design Platform™ ...

Introducing SiFive Insight

by James Prior on SiFive
teaser image Access, Observe, Control The term ‘debug’ has a storied history. It’s widely reported as being coined by computing pioneer, US Navy Rear Admiral Grace Hopper, when she removed a moth from Harvard’s Mark II computer in 1945. Use of the word bug can also be traced to the great inventor, Thomas Edison, from a letter he wrote in 1878. Whatever the origin, we all agree that we don’t want bugs in our systems, our hardware, our code. With computer systems long past the size where physical ...

Making It Easy To Get It Right

by Drew Barbier on SiFive
teaser image Today, SiFive is excited to announce the general availability of the Q3 2019 Engineering Update, packed with new features, tools, and improvements. In the first SiFive quarterly update, we discussed the transition from the “Information Age” to the “Experience Age.” In the Q3 Engineering Update, SiFive is delivering on our customer experience mantra: “Make It Easy” and “Get It Right.” - two principles at the heart of our Sales, FAE, and Engineering mindset for supporting and enabling our ...

The SiFive Tech Symposiums are Heading To Portland and Seattle This Month – See You There!

by Swamy Irrinki on SiFive
We’re confirming seats in Portland and Seattle for the Pacific Northwest leg of our worldwide 2019 SiFive Tech Symposiums. We are pleased to have Mentor, A Siemens Business as our co-host, and Lauterbach, a leader in microprocessor development tools, as our partner in both cities. The Portland symposium will take place Tuesday, October 22 at the Portland Community College. Our Seattle symposium will be on Wednesday, October 23 at thinkspace Seattle. All of the SiFive Tech Symposiums have ...

The SiFive Tech Symposiums in Portland and Seattle are a Wrap

by Purvi Shenoy on SiFive
teaser image Our SiFive Tech Symposiums in Portland and Seattle were a big success, thanks in large part to our co-host, Mentor, a Siemens business; and our partner, Lauterbach, a leader in microprocessor development tools. Many leading OEMs were in attendance, such as Amazon, Facebook, Intel, Microsoft and Google There were presentations by the RISC-V Foundation, SiFive, Mentor and Lauterbach, as well as other ecosystem partners. We’d like to offer our thanks to the faculty and students at Portland ...

SiFive’s Tech Symposiums and Workshops Throughout South America Included Participation by Both Academia and Industry

by Swamy Irrinki on SiFive
teaser image We completed our tour through South America, which included tech symposiums and workshops in São Paulo, Porto Alegre, Montevideo, Buenos Aires and Bucaramanga. We are proud to have co-hosted these events with South America’s most prestigious universities, including the Polytechnic School of the University of São Paulo (Poli-USP), the Federal University of Rio Grande do Sul (UFRGS), the Universidad Católica del Uruguay (UCU), the University of Bueno Aires (UBA), the Universidad Industrial de ...

SiFive Completes its Global 52-City Tech Symposium/Workshop Tour

by Swamy Irrinki on SiFive
teaser image The RISC-V ISA is rapidly becoming the new standard for compute, and has literally spawned a worldwide revolution in the semiconductor industry. At the beginning of 2019, SiFive set out to foster education about SiFive’s RISC-V based technologies and to advance deeper collaboration within the global hardware community. We succeeded! We completed 52 Tech Symposiums/Workshops reaching 26 countries and six continents – reaching all corners of the world. Over 10,000 people attended these ...

Part 1: Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V

by Shubu Mukherjee on SiFive
teaser image This is the first in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). A DSA provides higher performance per watt than a general-purpose processor by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI ...

Part 2: High-Bandwidth Core Access to Accelerators: Enabling Optimized Data Transfers with RISC-V

by Shubu Mukherjee on SiFive
teaser image This is the second in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in SoCs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance. To recap, a DSA provides higher performance per watt by optimizing the specialized function it implements. Examples of ...

Part 3: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

by Shubu Mukherjee on SiFive
teaser image This is the third in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in system-on-chip (SoC) designs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance. Part #2 addressed the challenges associated with point-to-point ordering between cores and DSA ...

Students for GSoC projects wanted

by Pirmin Vogel on lowRISC: Collaborative open silicon engineering
We are excited to be back as a mentoring organisation for Google Summer of Code (GSoC) and are currently looking for enthusiastic students interested in doing a project with us. The GSoC initiative gives students the opportunity to spend the summer break gaining real-world hardware and software development experience while earning a stipend from Google. If you’re a student interested in applying, we strongly recommend you read up on how GSoC works and study the Google Summer of Code Student ...

Our SiFive Tech Symposiums in Costa Rica and Mexico Underscore the Global Adoption of the RISC-V ISA in Industry and Academia

by David Connelly on SiFive
teaser image Our SiFive Tech Symposiums in San José, Costa Rica and Mexico City, Mexico were well attended by not only those in industry, but in academia as well. There is a great deal of enthusiasm and engagement in RISC-V in both of these regions. Many new friendships were formed, and we look forward to the continued networking and idea sharing that open source brings to the hardware community. Western Digital co-hosted the symposium in Costa Rica, which was co-located with LASCAS 2020, the flagship ...

Part 4: High-Performance Interconnect for Accelerators: Enabling Optimized Data Transfers with RISC-V

by Shubu Mukherjee on SiFive
teaser image This is the fourth in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). Parts 1, 2 and 3 addressed key challenges such as data transfers between DSAs and the core complex, point-to-point ordering between cores and DSA memory, and data transfers between DSA and memories. This fourth instalment in the series will focus on the frequent interaction with and amongst cores, which is required by DSAs, and how the TileLink ...

El Correo Libre - Issue 25

by FOSSi Foundation on FOSSi Foundation - News & Posts
A new issue of the FOSSi Foundation’s monthly roundup of all things Open Source semiconductor design, El Correo Libre, is out there for all to enjoy. Follow the link for FOSSi-related FOSDEM 2020 video presentations, OpenPower updates and more RISC-V news. El Correo Libre Issue 24 - LibreCores - Medium

El Correo Libre Issue 25

by Gareth Halfacree on LibreCores - Medium
teaser image FOSDEM 2020 Video Presentations Now AvailableVideo presentations and, where available, slide decks have been published for the FOSDEM 2020 event, held in Brussels on the 1st and 2nd of February 2020. For the free and open-source silicon enthusiast, topics of interest are likely include: Drew Fustini on running Linux on RISC-V with open hardware and software; Anton Kuzmin on debugging IP cores on-hardware with free tools; Mario Behling on continuous integration (CI) for open hardware ...

RISC-V Foundation Formally Ratifies the Processor Trace Specification

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has announced the formal ratification of the processor trace specification, introducing a standardised trace encoder algorithm for the free and open-source instruction set architecture as a means of assisting with debugging. “RISC-V is rapidly gaining popularity due to its open and modular design that supports customisation on top of a standard core ISA,” says Krste Asanović, chair of the RISC-V Foundation Board of Directors. “The RISC-V ecosystem continues to showcase ...

Verilator - Verilator 4.030 Released

by Wilson Snyder on Veripool: News
Verilator 4.030 2020-03-08 Add split_var metacomment to assist UNOPTFLAT fixes, #2066. [Yutetsu TAKATSUKASA] Add support for $dumpfile and $dumpvars, #2126. [Alexander Grobman] Add support for dynamic arrays, #379. Add +verilator+noassert flag to disable assertion checking. [Tobias W\303\266lfel] Add check for assertOn for asserts, #2162. [Tobias W\303\266lfel] Add --structs-packed for forward compatibility. Fix genblk naming ...

The OpenPOWER Foundation Releases Compliance Definitions, Forms ISA Work Group

by Gareth Halfacree on FOSSi – AB Open
The OpenPOWER Foundation has officially released the compliance definition for its now-open instruction set architecture, defining test suite requirements for both POWER8 and POWER9 ISAs, and has pledged to form a new Work Group for ISA-related activities. “There is much excitement in the August 2019 announcement of open-sourcing the POWER Instruction Set Architecture (ISA), which provides the opportunity for experimentation and collaboration,” says Sandy Woodward, chair of the OpenPOWER ...

OTA: Lime Suite 20.01.0, cuSignal Acceleration, MIT’s RFocus, and More

by Gareth Halfacree on MyriadRF
teaser image The Lime Suite software bundle has received a significant update, to version 20.01.0, bundling new support for the LimeRFE software-defined front end, improved tuning and PLL locking, and other improvements. In its latest release, the open-source Lime Suite library comes with support for the LimeRFE front end, following on from last year’s addition of support for the final LimeNET Micro design. The new release also includes improvements and bug-fixes for PLL locking during calibration, ...

El Correo Libre - Issue 24

by FOSSi Foundation on FOSSi Foundation - News & Posts
A new issue of the FOSSi Foundation’s monthly roundup of all things Open Source semiconductor design, El Correo Libre, is out there for you to induldge in. News about upcoming Latch-up Cambridge, Massachusetts; bigger and better, how Microwatt OpenPOWER Core is Now GHDL Compatible, new uses for SpinalHDL and much more. El Correo Libre Issue 24 - LibreCores - Medium

El Correo Libre Issue 24

by Gareth Halfacree on LibreCores - Medium
teaser image Announcing Latch-Up Cambridge, MassachusettsFollowing up on the fantastic event we had in Portland, Oregon last year we have set our sights on the US East coast this year. We hope to make this Latch-Up slightly bigger and better this year, but in all other regards it will be a familiar setup in the spirit of previous Latch-Up and our long-running ORConf Latch-Up is a community-focused conference for open source semiconductor, digital design and embedded systems professionals and ...

Bigger Is Not Always Better: Builds Are Faster with Smaller Packages

by Tudor Timi on Verification Gentleman
teaser image One trend over the past few years is that the projects I've been working on tend to get bigger and more complicated. Bigger projects come with new challenges. Among these are the fact that it's much more difficult to keep the entire project in one's head, the need to synchronize with more developers because team sizes grow, a higher risk of having to re-write code because of poorly understood requirements or because some requirements change, and many more.There's one thing, though, that ...

What's happing in the open silicon ecosystem around you? Planet LibreCores helps you to get the latest news from all corners of the community by aggregating blog posts.

All content here is unfiltered and uncensored, and represents the views of the post authors. Individual posts are owned by their authors; please see the original source for licensing information.

Subscribe to Planet LibreCores

In addition to reading the posts here, you can subscribe to Planet LibreCores in your favorite feed reader.

Planet Librecores Atom feed

Or get the subscription list through FOAF or OPML.

Last updated 27 May 2020 11:30 UTC