Planet LibreCores

Verilator - Verilator 4.024 Released

by Wilson Snyder on Veripool: News
Verilator 4.024 2019-12-08 Support associative arrays (excluding [*] and pattern assignments), bug544. Support queues (excluding {} notation and pattern assignments), bug545. Add +verilator+error+limit to see more assertion errors. [Peter Monsson] Support string.toupper and string.tolower. Support $rewind and $ungetc. Support shortreal as real, with a SHORTREAL warning. Add -Wpedantic and -Wno-context for compliance testing. Add error on redefining preprocessor ...

OTA: QO-100 FreeDV Transmissions, Lime-Powered 5G Testbeds, O-RAN Code, and More

by Gareth Halfacree on MyriadRF
Lime Microsystems has published an interview with Gerhard Burian, David Rowe, and Steve Sampson on using FreeDV Mode 2020 for transmitting digital voice via the Es’Hail-2 satellite’s amateur radio transponder (QO-100) using just 1,600 Hz of radio frequency bandwidth. “The bandwidth regulation on the [QO-100] narrow band transponder, being 2,700 Hz, prevents the use of other digital voice modes like D-Star or DMR, normally used on VHF/UHF,” Gerhard explains. “FreeDV is a narrowband mode, ...

Dependable Real-time Infrastructure for Safety-critical Computer (De-RISC) Aims for the Stars

by Gareth Halfacree on FOSSi – AB Open
Cobham Gaisler and fentISS have confirmed that the now-funded De-RISC project is forging ahead with its efforts to built a RISC-V based space-qualified computing platform centred in Europe, in partnership with Barcelona Supercomputing Centre and Thales. “With the first RISC-V based, fully European platform for space, De-RISC will guarantee access to made-in-Europe technology for aerospace applications,” claims Paco Gomez Molinero, chief executive officer of fentISS and coordinator of the ...

lowRISC 101: Introduction to lowRISC at the RISC-V Summit

by lowRISC on lowRISC: Collaborative open silicon engineering
With the recent announcement of OpenTitan, we at lowRISC had many great conversations about the work we do to produce high-quality open source hardware and software. A great place to continue these discussions is the RISC-V Summit in San Jose, CA (Dec 10 - 12, 2019). lowRISC will showcase its work in the conference track and in the exhibit hall. At booth 101, lowRISC will showcase its recent work and our engineers will be around to answer your questions. Stop by if you have questions about ...

SiFive Unveils Learn Inventor Educational RISC-V Development Board

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneer SiFive has announced the SiFive Learn Inventor, a development board aimed at the education and maker markets which merges the popular BBC micro:bit design with its own HiFive1. Launched via crowdfunding in late 2016, though not shipping in volume until January 2017, the SiFive HiFive1 took its design inspiration from the Arduino Uno microcontroller development board but with a Freedom E310 RISC-V chip at its heart. The SiFive Learn Inventor takes a more recent revision of ...

Final Countdown to RISC-V Summit in San Jose

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
teaser image The RISC-V Summit in San Jose starts on Monday, December 9. There is still time to register for both the Summit itself and the all-members working day on December 9, but the window is closing soon. This Summit will bring together the principal movers and shakers in the hardware industry. This is not an event to miss.For more information and details on the event, please see the agenda page. If you are not yet registered, visit the registration page.See you at the Summit! The post Final ...

Think Silicon to Demonstrate its NEOX|V RISC-V GPGPU at the RISC-V Summit 2019

by Gareth Halfacree on FOSSi – AB Open
Think Silicon has announced the development of a general-purpose graphics processor (GPGPU) with 3D acceleration capabilities built on the free and open RISC-V instruction set architecture (ISA) – and claims it will be the first in the industry to demonstrate such a device working, at the RISC-V Summit later this month. “Building a GPGPU on RISC-V instruction set architecture is another significant milestone in the young history of Think Silicon,” says Think Silicon’s senior vice president ...

RISC-V Summit Member Day Schedule

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
teaser image The RISC-V Summit is only one week away! This is the schedule for Member Day on December 9. Registration is required, as is RISC-V member status – see the Join page for details. The post RISC-V Summit Member Day Schedule appeared first on RISC-V Foundation.

CRU: RISC-V for Beginners, Sensors, and Browsers, MIPS Open Closes, and More

by Gareth Halfacree on FOSSi – AB Open
Bootlin’s Michael Opdenacker has published a guide to getting started with embedded Linux on RISC-V in just 40 minutes, as part of a presentation given during the Capitole du Libre 2019 event earlier this month. Building on a presentation first given at the Libre Software Meeting 2005, in which Opdenacker demonstrated how to get Linux 2.6 up and running on a QEMU-emulated Arm device in under 40 minutes, the new presentation was triggered by a range of changes – including the ...

Get started with OpenTitan

by Greg Chadwick on lowRISC: Collaborative open silicon engineering
Interested in trying out the recently announced OpenTitan? We’ve put together a video that goes through an overview of how the OpenTitan prototype system is put together and how to get up and running with our pre-built release (providing simulator binaries and pre-built FPGA images for the Nexys Video Artix-7 board). It follows the steps from the OpenTitan Quickstart Guide. You can find out more about OpenTitan from our announcement blog and the OpenTitan website.

Workshop on Open Source Design Automation (OSDA) 2020 Opens Call for Participation

by Gareth Halfacree on FOSSi – AB Open
The Workshop on Open Source Design Automation (OSDA), now on its second year, has announced a call for contributions with a deadline of the 12th of January 2020 – and is, as with the year before, taking place at the Conference on Design, Automation, and Test in Europe (DATE). “There is no doubt that proprietary EDA [Electronic Design Automation] tools are successful, mature, and are fundamental for hardware development,” write workshop organisers Clifford Wolf and Christian Kreig. “However, ...

OTA: LimeRFE Shipping Update, Signals Everywhere on the LimeSDR Mini, and More

by Gareth Halfacree on MyriadRF
The LimeRFE software-definable RF front-end has officially passed verification in its updated v1.0 revision form, with production of the backer boards on-track for a late-January shipping schedule. As detailed back in August, the LimeRFE board – which offers low-noise amplification, power amplification, and filtering under software control from the LimeSDR and LimeNET families of software defined radios – is entering into production as a slightly modified design. Compared to the prototype, ...

Bootlin’s Michael Opdenacker Gets You Started with Embedded Linux on RISC-V in Just 40 Minutes

by Gareth Halfacree on FOSSi – AB Open
Bootlin’s Michael Opdenacker has published a guide to getting started with embedded Linux on RISC-V in just 40 minutes, as part of a presentation given during the Capitole du Libre 2019 event earlier this month. Building on a presentation first given at the Libre Software Meeting 2005, in which Opdenacker demonstrated how to get Linux 2.6 up and running on a QEMU-emulated Arm device in under 40 minutes, the new presentation was triggered by a range of changes – including the ...

We Just Completed Five Energy-Filled Tech Symposiums and RISC-V Workshops Throughout the Middle East Region

by Aijaz Qaisar on SiFive
teaser image Our tour through the Middle East region included Istanbul, Amman, Cairo, Abu Dhabi and Dubai. This tour was dedicated to academia, and included presentations, tutorials and hands-on workshops. Attendees primarily consisted of PhD research scholars, professors and engineering students. It was humbling to see that the region’s universities have included the book, The RISC-V Reader: An Open Architecture Atlas, authored by SiFive Technical Adviser David Peterson and Co-Founder and Chief ...

Our SiFive Tech Symposiums in Pakistan Drew Over 2,500 Attendees!

by Shivaram Venkatesh Nellaiappan on SiFive
teaser image SiFive’s Tech Symposiums in Pakistan were a huge success, with the participation of more than 2,500 people from across the country. One of the symposiums was held at the NED University of Engineering and Technology in Karachi, and the other took place at the University of Engineering and Technology in Lahore. We are grateful to both of these universities for co-hosting these events with us, and to Lampro Mellon for partnering with us. All three were instrumental in making these symposiums ...

Wave Computing Shutters MIPS Open Programme with Immediate Effect

by Gareth Halfacree on FOSSi – AB Open
Wave Computing has officially shuttered its MIPS Open programme, providing “open use” to selected MIPS core IP and the underlying instruction set architecture, less than a year after the initiative was launched – and with zero advance warning. Wave Computing, which acquired the rights to the proprietary MIPS ISA and core IP from Imagination Technologies in mid-2018, announced the MIPS Open Initiative back in December last year. “Having spent years in the open source technology movement, I ...

BSC Opens the European Laboratory for Open Computer Architecture, LOCA

by Gareth Halfacree on FOSSi – AB Open
The Barcelona Supercomputer Centre (BSC) has announced the opening of the European Laboratory for Open Computer Architecture (LOCA), which aims to develop both energy-efficient and high-performance chips based on open instruction set architectures (ISAs). “LOCA will be a collaborative laboratory that welcomes companies, foundations and academic institutions that share the vision that it is necessary to create open architectures to guarantee transparency, competitiveness, and technological ...

El Correo Libre Issue 21

by Gareth Halfacree on LibreCores - Medium
teaser image ORConf 2019 Presentation Videos Now AvailableThose who were not able to attend ORConf 2019, or those who were but need a refresher on everything that happened, will be pleased to hear that videos for all 42 presentations at the event are now available on the FOSSi Foundation’s YouTube Channel. Presentations given at the event and captured for posterity include, but are most certainly not limited to, a look at open-source formal verification from Pepijn de Vos, an introduction to the ...

Observer Tacks RISC-V Cores to Sensors to Simplify Heterogeneous Aggregation

by Gareth Halfacree on FOSSi – AB Open
Olof Kindgren, director of the Free and Open Source Silicon Foundation (FOSSi Foundation), has released a tool designed to make multi-sensor aggregation on field-programmable gate arrays (FPGAs) simpler: the RISC-V-powered Observer. “Implementing the logic for sensor communication, post processing and format conversion directly in an FPGA can quickly become very time-consuming. This is a task much better suited for a CPU,” Kindgren explains of the project. “On an FPGA it’s no problem to add ...

Verilator - Verilator 4.022 Released

by Wilson Snyder on Veripool: News
Verilator 4.022 2019-11-10 Add --protect-lib, bug1490. [Todd Strader] Add cmake support, bug1363. [Patrick Stewart] Examples have been renamed. Add --protect-ids to obscure information in objects, bug1521. [Todd Strader] Add --trace-coverage. Add --xml-output. Support multithreading on Windows. [Patrick Stewart] Suppress 'command failed' on normal errors. Support some unpacked arrays in parameters, bug1315. [Marshal Qiao] Add interface port visibility in ...

The SiFive Tech Symposiums in Portland and Seattle are a Wrap

by Purvi Shenoy on SiFive
teaser image Our SiFive Tech Symposiums in Portland and Seattle were a big success, thanks in large part to our co-host, Mentor, a Siemens business; and our partner, Lauterbach, a leader in microprocessor development tools. Many leading OEMs were in attendance, such as Amazon, Facebook, Intel, Microsoft and Google There were presentations by the RISC-V Foundation, SiFive, Mentor and Lauterbach, as well as other ecosystem partners. We’d like to offer our thanks to the faculty and students at Portland ...

OTA: LimeNET Manufacturing Update, LimeSDR Mini External Reference Guide, and More

by Gareth Halfacree on MyriadRF
Manufacturing of the LimeNET Micro is underway, after initial volume production was delayed by selected components entering end-of-life (EOL) status. “A few of the parts we were planning to use went end-of-life just as we were in the process of setting up a volume production run,” explains Lime Micro’s Andrew Back of the delay. “The good news is that we’ve identified alternative parts and updated our design to accommodate them. “Doing so took us a little while, as we had to go through our ...

European Commission Publishes Final Open Source Beyond 2020 Agenda

by Gareth Halfacree on FOSSi – AB Open
The European Commission is to host the Open Source Beyond 2020 workshop on the future of open source hardware and software next week, featuring a panel on the advent of open source hardware and the Internet of Things chaired by the head of the Competitive Electronics Industry DG Connect A3 Unit Colette Maloney. “Open Source has become mainstream across all sectors of the software industry during the past 10 years,” the Commission writes of the event. “To a large extent, open software re-use ...

Announcing OpenTitan, the First Transparent Silicon Root of Trust

by lowRISC on lowRISC: Collaborative open silicon engineering
teaser image Today, we are excited to unveil the OpenTitan silicon root of trust (RoT) project, a new effort built using the successful collaborative engineering model created by lowRISC in partnership with Google and other commercial and academic partners. This effort sets a new bar for transparency in trusted silicon, and lowRISC is proud to serve as both steward and not-for-profit engineering contributor to OpenTitan, the world’s first open source silicon RoT. Silicon root of trust chips increase ...

lowRISC Collaborates with Industry Leaders to Create OpenTitan

by lowRISC on lowRISC: Collaborative open silicon engineering
Organisations aim to make the hardware root more transparent, trustworthy, and secure for everyone. CAMBRIDGE, England–(BUSINESS WIRE)–lowRISC C.I.C., the open source silicon and tools collaborative engineering company, today announced that it has partnered with ETH Zürich, Google, G+D Mobile Security, Nuvoton Technology and Western Digital in support of OpenTitan, an open source hardware root of trust (RoT) reference design and integration guidelines that enable chip producers and ...

Andy Hopper joins lowRISC CIC Board as Independent Chair

by lowRISC on lowRISC: Collaborative open silicon engineering
teaser image Today, we are delighted to announce that Professor Andy Hopper, CBE FRS FIET FREng, has joined the lowRISC Board of Directors as Independent Chair. “I’m delighted to be joining lowRISC CIC,” said Prof. Hopper, speaking today from Cambridge UK, “As digital systems pervade every aspect of our lives trust and transparency become crucial. An open source approach allows for public inspection of the principles and implementations being used. I believe the future of digital systems will be ...

RISC-V Hits the Browser Courtesy of Martin Strubel’s CI Docker Image

by Gareth Halfacree on FOSSi – AB Open
Martin Strubel has released a guide to running a RISC-V core directly in a browser – though admits that it’s unsurprisingly not quite as performant as if it were running in a native emulator or on dedicated hardware. “I though I’d share some open source approach to let a RISC-V spin in the cloud – a few 1000 times slower than reality, but still fast enough to run the ISA tests and – for fun – to talk to the SoC through a virtual UART,” Strubel writes in a post to the RISC-V hardware ...

CRU: Next-Gen Wishbone, FOSSi Events, and FOSSi Hits the Cloud

by Gareth Halfacree on FOSSi – AB Open
The maintainers of the Wishbone interconnect specification are calling for input on its future evolution, after converting the specification into an editor-friendly format for ease of participation. Offering eight, 16, 32, and 64 bit widths and originally created by the Silicore Corporation before being released under a permissive licence, the Wishbone bus is a popular choice for cross-core interconnections in free and open source silicon designs. Its maintainers, though, are looking to ...

OpenPiton+Ariane Reaches the Clouds via Amazon’s EC2 FPGAs

by Gareth Halfacree on FOSSi – AB Open
The free and open OpenPiton+Ariane heterogeneous research processor is now available on Amazon’s Elastic Compute Cloud (EC2) field-programmable gate arrays, providing an easy route to test it out without needing dedicated hardware. A partnership between the PULP Platform and the OpenPiton project released back in December last year, OpenPiton+Ariane combines the OpenSPARC and RISC-V cores to build what its creators call “the ideal permissive open-source RISC-V system that scales from ...

Bringing OpenPiton to Amazon EC2 F1 FPGAs

by Jonathan Balkind on OpenPiton Blog
teaser image OpenPiton release 13 (19-10-23-r13) is now available. The headline feature of this release is support for running OpenPiton+Ariane in the cloud via Amazon EC2 F1. Release 13 also offers other bug fixes and improvements that you can see on our GitHub repository. We now provide a step-by-step guide in the README of OpenPiton on GitHub which explains how to emulate OpenPiton+Ariane on Amazon EC2 F1 cloud FPGAs. You can make use of our existing release image to test software and firmware, or ...

OTA: Sending CSVs Over The Air, QRadioLink 0.8.2, In-Band Full-Duplex Breakthrough, and More

by Gareth Halfacree on MyriadRF
Salil Tembe has published a guide on using GNU Radio and a LimeSDR Mini to transmit a comma-separated value (CSV) text file over the airwaves. “We have seen the LimeSDR Mini several times on this blog,” Salil writes in the introduction to the piece. “So far, we have only seen how it can generate analogue modulation to transmit voice and what not. Being an SDR capable to transmit practically anything, we can even transmit binary data.” The project – which comes with downloadable GNU Radio ...

Incredibly Scalable High-Performance RISC-V Core IP

by James Prior on SiFive
teaser image Introducing the new SiFive U8-Series Core IP SiFive is pleased to introduce the SiFive U8-Series Core IP, an incredibly scalable high-performance microarchitecture for modern SoC designs. The SiFive U8-Series is the highest performance RISC-V ISA based Core IP available today, based on a superscalar out-of-order pipeline with configurable pipeline depth and issue queue width. SiFive U8-Series Core IP is designed for use in performance- and latency-sensitive markets, such as automotive, ...

SiFive Shield: An Open, Scalable Platform Architecture for Security

by James Prior on SiFive
teaser image Securing The RISC-V Revolution SiFive Shield is an open, scalable platform architecture designed to enable whole SoC security for RISC-V designs. The needs of modern SoC design dictate the need for a scalable solution for security, offering a low trusted computing base with clear root-of-trust and crucially, is auditable. Customization is also key, as a single offering fits all approach does not align to the needs of the next generation of domain specific processors now being ...

Introducing Greg & Tom

by lowRISC on lowRISC: Collaborative open silicon engineering
teaser image Greg Chadwick and Tom Roberts recently joined lowRISC’s growing engineering team. They’ve both taken some time to share a little about what they’re doing at lowRISC and what motivated them to join. Greg “It’s an exciting time to join the lowRISC team! Our Ibex core provides a solid foundation and clearly demonstrates the value of open source silicon, which I’m excited to be working on. My work so far has focused on the performance of Ibex; whilst it’s not ...

Wishbone Interconnect Maintainers Seek Input on Next-Generation Evolution

by Gareth Halfacree on FOSSi – AB Open
The maintainers of the Wishbone interconnect specification are calling for input on its future evolution, after converting the specification into an editor-friendly format for ease of participation. Offering eight, 16, 32, and 64 bit widths and originally created by the Silicore Corporation before being released under a permissive licence, the Wishbone bus is a popular choice for cross-core interconnections in free and open source silicon designs. Its maintainers, though, are looking to ...

FOSDEM 2020 RISC-V Devroom Opens Call for Participation

by Gareth Halfacree on FOSSi – AB Open
The organisers of the RISC-V Devroom at the FOSDEM 2020 conference, taking place in Brussels this coming February, have opened the call for talk proposals. “FOSDEM 2020 will take place on February 1-2, 2020 in Brussels, Belgium. There will be a half day RISC-V developer’s room on February 1st (Saturday),” writes Arun Thomas in a message to the RISC-V Foundation’s software mailing list. “The topic of the devroom encompasses the RISC-V ISA, open source RISC-V hardware (e.g. cores, SoCs, ...

CHIPS Alliance Growth Continues With New Members And Design Workshop This November | PR Newswire

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
SAN FRANCISCO, Oct. 15, 2019 /PRNewswire/ — CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced Codasip GmbH and Munich University of Applied Science have joined the CHIPS Alliance. In addition, on November 14–15, CHIPS Alliance will be joining the university for a workshop on open source design verification.CHIPS Alliance is a project hosted by the Linux Foundation to foster a collaborative environment to accelerate ...

The SiFive Tech Symposiums are Heading To Portland and Seattle This Month – See You There!

by Swamy Irrinki on SiFive
We’re confirming seats in Portland and Seattle for the Pacific Northwest leg of our worldwide 2019 SiFive Tech Symposiums. We are pleased to have Mentor, A Siemens Business as our co-host, and Lauterbach, a leader in microprocessor development tools, as our partner in both cities. The Portland symposium will take place Tuesday, October 22 at the Portland Community College. Our Seattle symposium will be on Wednesday, October 23 at thinkspace Seattle. All of the SiFive Tech Symposiums have ...

RISC-V Foundation Announces RISC-V Summit 2019 Agenda

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has announced the agenda for its second annual RISC-V summit, taking place this December in San Jose, California. “The RISC-V Foundation, in partnership with Informa’s Tech Division, is hosting its annual RISC-V Summit, a four-day conference featuring keynotes, smaller breakout sessions, tutorials, exhibitions and networking receptions, as well as member meetings to open the week’s events,” the Foundation explains. “Leading technology companies and research ...

NVDLA Deep Learning Inference Compiler is Now Open Source

by on SiFive
teaser image Designing new custom hardware accelerators for deep learning is clearly popular, but achieving state-of-the-art performance and efficiency with a new design is a complex and challenging problem. Two years ago, NVIDIA opened the source for the hardware design of the NVIDIA Deep Learning Accelerator (NVDLA) to help advance the adoption of efficient AI inferencing in custom hardware designs. The same NVDLA is shipped in the NVIDIA Jetson AGX Xavier Developer Kit, where it provides ...

VSDOpen 2019 Online Conference Scheduled for Saturday 19th October

by Gareth Halfacree on FOSSi – AB Open
VLSI System Design (VSD) has announced VSDOpen 2019, its second annual online conference for the semiconductor industry – with a focus on open-source electronics design automation (EDA) and the RISC-V instruction set architecture. Following the success of VSDOpen 2018, VLSI System Design has scheduled its second annual online conference – and this year it will includes a “virtual booth” for demonstrations of eFabless’ Raven, PULP Project’s RI5CY, Ariane, and Ibex, RISC-V BOOM, and SHAKTI. ...

The RISC-V Foundation Announces Agenda for the Second Annual RISC-V Summit

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
teaser image The three-day conference will feature keynotes, exhibitions, smaller breakout sessions, tutorials and networking receptionsWHAT: The RISC-V Foundation has announced the agenda for the RISC-V Summit 2019WHERE: San Jose Convention Center in San Jose, Calif.WHEN: Monday, Dec. 9 to Thursday, Dec. 12, 2019DETAILS: The RISC-V Foundation, in partnership with Informa’s Tech Division of Informa PLC, is hosting its annual RISC-V Summit, a four-day conference featuring keynotes, smaller breakout ...

OTA: Osmocom Updates, OpenRAN Hits the UK, Seeing Through Walls, and More

by Gareth Halfacree on MyriadRF
The Osmocom open-source cellular communications project has released an updated Cellular Network Infrastructure (CNI) stack, which brings with it improved support for the LimeSDR family. “The Osmocom project has released new version of the CNI (Cellular Network Infrastructure) software, including OsmoTRX, OsmoBTS, OsmoBSC, OsmoMGW, OsmoMSC, OsmoHLR, OsmoSGSN, OsmoGGSN,” project maintainer Harald Welte writes in the release announcement. “Those new tagged/released versions contain four ...

CHIPS Alliance Announces Two-Day Open-Source Design Verification Workshop

by Gareth Halfacree on FOSSi – AB Open
CHIPS Alliance has opened registration for a two-day open-source design verification workshop, taking place on the 14th and 15th of November in Munich, Germany. Launched back in March, CHIPS Alliance is a Linux Foundation project focused on supporting the burgeoning free and open source silicon (FOSSi) movement. Its first official workshop was held back in June at the Google Sunnyvale campus, and now the organisation has announced its second will take place in November at the Munich ...

The Economist Switches On to the Potential of Free and Open Source Silicon

by Gareth Halfacree on FOSSi – AB Open
The free and open source silicon movement is continuing to capture mainstream interest, with The Economist becoming the latest publication to examine the impact the movement is having both generally and in specific cases. There’s a temptation to view free and open source silicon purely in terms of economic value to established ventures, where companies like Western Digital and Nvidia can cut a considerable cost from their bottom line by investing in customised silicon based on open ...

Ibex on FPGA - Get stuff executed

by Pirmin Vogel on lowRISC: Collaborative open silicon engineering
teaser image Our microcontroller-class RISC-V processor core Ibex for sure is a solid base with which to start your own project. Over the past months, we have invested a lot of effort in making the design more mature. This includes refactoring the RTL to make the design more understandable and programmer friendly, adding UVM-based verification to the source tree, but also integrating support for the RISC-V compliance suite and enabling publicly visible, open-source powered continuous integration (CI) to ...

CRU: New Open Silicon Releases, Xilinx’ Vitis, and More

by Gareth Halfacree on FOSSi – AB Open
Semiconductor Engineering’s Ann Steffora Mutschler has highlighted the growing popularity of open instruction set architectures (ISAs) like RISC-V and the newly-opened Power ISA, in a piece with input from a range of industry experts. “It’s become so cumbersome to go into building chips because of all these factors,” OpenPOWER processor enablement director Mendy Furmanek tells Mutschler, referring to the complexity of entering into multiple agreements with multiple intellectual property ...

El Correo Libre Issue 20

by Gareth Halfacree on LibreCores - Medium
teaser image ORConf2019 A Resounding SuccessORConf 2019 has come and gone, and thanks to the speakers, attendees and organizers, it was another successful event for all. The superb venue of autumnal Bordeaux provided the backdrop to 3 days of impressive talks from the ever broadening church of the open source digital design scene. Another full house of locals and folks from across the globe meant the buzz was constant throughout the weekend. We’re always pleased by how many new faces we see, and also ...

Verilator - Verilator 4.020 Released

by Wilson Snyder on Veripool: News
Verilator 4.020 2019-10-06 Support $fseek, $ftell, $frewind, bug1496. [Howard Su] Add --public-flat-rw, bug1511. [Stefan Wallentowitz] Support vpiModule, bug1469. [Stefan Wallentowitz] Make Syms file honor --output-split-cfuncs, bug1499. [Todd Strader] Fix make test with no VERILATOR_ROOT, bug1494. [Ahmed El-Mahmoudy] Fix error on multidimensional cells, bug1505. [Anderson Ignacio Da Silva] Fix config_rev revision detection on old versions. Fix false warning on backward ...

Xilinx Turns to Open Source for New Vitis Unified Software Platform

by Gareth Halfacree on FOSSi – AB Open
Xilinx has announced the launch of the Vitis development platform, designed to allow the like of software engineers and artificial intelligence (AI) scientists to take advantage of field-programmable gate arrays (FPGAs) – and it builds on open-source software. “With exponentially increasing compute needs, engineers and scientists are often limited by the fixed nature of silicon,” claims Victor Peng, president and chief executive officer of Xilinx. “Xilinx has created a singular environment ...

RISC-V Foundation Announces Security-Focused Soft-Core CPU Contest Winners

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has announced the winners of its RISC-V Soft CPU Contest, launched back in July with a view to promoting security-focused RISC-V implementations. “With the proliferation of connected devices, security is one of the key challenges in hardware design. The free and open RISC-V ISA presents an incredible opportunity for the ecosystem to collaborate to develop more robust solutions for the growing security demands of today and the future,” said RISC-V Foundation chief ...

Supporting A World Leading RISC-V IP Portfolio

by Drew Barbier on SiFive
teaser image The second SiFive quarterly engineering release has arrived, and includes some great new Trace & Debug features. Static source code analysis may not offer a complete view of real world operation. Real time analysis enabled via tracing permits a deeper insight into the interactions of software and hardware to accelerate development, debug, validation of modern, configurable SoC designs. A major focus of the Q3 Engineer Update was adding support for Nexus 5001™ compliant instruction trace. ...

1st CLaaS and Google Summer of Code Work to “Open The Floodgates” of Free and Open Source Silicon

by Gareth Halfacree on FOSSi – AB Open
Redwood EDA’s Steve Hoover has written of a Google Summer of Code student who “helped open the floodgates” of free and open source silicon (FOSSi) by contributing to the 1st CLaaS framework project: Ákos Hadnagy. “While [the] open source silicon community is a hotbed of enthusiasm, it is several decades behind the world of open source software,” Hoover writes, listing “three reasons this movement has, thus far, not been able to take off like open source software” and “why these three ...

Kumico RISC-V Meetup in Japan Oct 23 & 25

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
さまざまな企業から注目されている「エッジコンピューティング」。 現在、自動車、医療、産業、家電など幅広い分野での導入が進んでいます。しかしながらその技術の進歩は加速度的に進んでおり、ソフトウェアだけでなくハードウェアのレベルでも柔軟に対応できる設計が求められています。 『KUMICO Meetup 2019』では、お客様のエッジコンピューティングを実現に導く、技術・製品・ノウハウをご紹介します。“Edge computing” is attracting attention from various companies. Currently, it is being introduced in a wide range of fields including automobiles, medical care, industry, and home appliances. However, advances in technology are accelerating, and there is a need for designs that can flexibly ...

Making It Easy To Get It Right

by Drew Barbier on SiFive
teaser image Today, SiFive is excited to announce the general availability of the Q3 2019 Engineering Update, packed with new features, tools, and improvements. In the first SiFive quarterly update, we discussed the transition from the “Information Age” to the “Experience Age.” In the Q3 Engineering Update, SiFive is delivering on our customer experience mantra: “Make It Easy” and “Get It Right.” - two principles at the heart of our Sales, FAE, and Engineering mindset for supporting and enabling our ...

Semiconductor Engineering Finds Open ISAs Gaining Traction in Industry

by Gareth Halfacree on FOSSi – AB Open
Semiconductor Engineering’s Ann Steffora Mutschler has highlighted the growing popularity of open instruction set architectures (ISAs) like RISC-V and the newly-opened Power ISA, in a piece with input from a range of industry experts. “It’s become so cumbersome to go into building chips because of all these factors,” OpenPOWER processor enablement director Mendy Furmanek tells Mutschler, referring to the complexity of entering into multiple agreements with multiple intellectual property ...

OTA: LimeNET Micro GNSS Monitoring, QO-100 Power Warnings, SDR# Plugins, and More

by Gareth Halfacree on MyriadRF
Community member Luigi Cruz has written up how he modified a LimeNET Micro to take part in the Galmon global navigation satellite system (GNSS) monitoring network. “In this blog post, I will explain how I managed to get a GNSS multi-constellation monitor called Galmon working on my LimeNET Micro,” Luigi explains by way of introduction to the project, which was discussed in brief in an earlier OTA. “The Galmon project is a crowdsourcing tool developed by @PowerDNS_Bert to monitor the health ...

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Last updated 08 December 2019 20:30 UTC