Planet LibreCores

Modeling Random Stimulus and Functional Coverage in Python

by Matthew Ballance on Bits, Bytes, and Gates
If you've been following the blog over the last year, you've probably noticed that I've spent quite a bit of time over the last year learning and using Python. For several reasons, it's become my new favorite programming language. Until recently, I've mostly used Python as an implementation language. However, I've been curious as to how well Python works for implementing an embedded

OTA: DreamCatcher’s Lab Kit, LuaRadio 0.6.1, Antenna Simulation, and More

by Gareth Halfacree on MyriadRF
Technical training specialist DreamCatcher has launched a training course with LimeSDR-powered lab kit, designed to teach university-level students Long Term Evolution (LTE) network concepts. “The ME1130 serves as a ready-to-teach package for in-depth understanding and hands-on experience on LTE and LTE-Advanced technologies,” DreamCatcher explains of the hardware that backs the course. “The PC-based implementation of LTE’s eNodeB [Evolved Node B] and EPC [Evolved Packet Core] is a powerful ...

Collaboration, Inspiration and Progressive RISC-V Based Innovation in India and Bangladesh is Increasing at a Steady Pace

by Aijaz Qaisar on SiFive
teaser image Our SiFive Tech Symposiums and Workshops in India and Bangladesh were a huge success, and an inspirational endeavor as well. We hosted events in six cities total, including symposiums in Noida/Delhi, Pune, Bangalore and Hyderabad, and workshops in Chennai and Bangladesh’s capital city of Dhaka. Attendance was at capacity in all locations, and was over capacity in Pune and Bangalore. Highlights From India Our co-hosts in India – Western Digital, Microchip and IIT Madras – delivered powerful ...

NVDLA Deep Learning Inference Compiler is Now Open Source

by on SiFive
teaser image Designing new custom hardware accelerators for deep learning is clearly popular, but achieving state-of-the-art performance and efficiency with a new design is a complex and challenging problem. Two years ago, NVIDIA opened the source for the hardware design of the NVIDIA Deep Learning Accelerator (NVDLA) to help advance the adoption of efficient AI inferencing in custom hardware designs. The same NVDLA is shipped in the NVIDIA Jetson AGX Xavier Developer Kit, where it provides ...

Israel is Evolving as a High-Tech Hub, and RISC-V is Playing a Vital Role

by Aijaz Qaisar on SiFive
teaser image Israel, and specifically the city of Tel Aviv, is said to have one of the highest densities of startups per capita in the world. At our SiFive Tech Symposium, we heard from some of the brightest minds residing at the epicenter of this high-tech hub. They shared their visions for the industry as well as their contributions to the semiconductor ecosystem via RISC-V based solutions. This is the second year in a row that we’ve hosted the SiFive Tech Symposium is Israel. With our partners, ...

Supporting A World Leading RISC-V IP Portfolio

by Drew Barbier on SiFive
teaser image The second SiFive quarterly engineering release has arrived, and includes some great new Trace & Debug features. Static source code analysis may not offer a complete view of real world operation. Real time analysis enabled via tracing permits a deeper insight into the interactions of software and hardware to accelerate development, debug, validation of modern, configurable SoC designs. A major focus of the Q3 Engineer Update was adding support for Nexus 5001™ compliant instruction trace. ...

Cloud Accelerated Idea To Silicon

by Chris Lattner on SiFive
teaser image The SiFive Mission SiFive’s mission is to accelerate chip design, closing the time between the definition of a chip to silicon being available - we call this the ‘idea to silicon' journey. The solutions to modern computing challenges increasingly require domain-specific accelerators, silicon chips designed to solve a focused problem with built-in adaptability to provide flexibility for shifting workloads. Today, Synopsys announced that SiFive has selected Synopsys Fusion Design Platform™ ...

Introducing SiFive Insight

by James Prior on SiFive
teaser image Access, Observe, Control The term ‘debug’ has a storied history. It’s widely reported as being coined by computing pioneer, US Navy Rear Admiral Grace Hopper, when she removed a moth from Harvard’s Mark II computer in 1945. Use of the word bug can also be traced to the great inventor, Thomas Edison, from a letter he wrote in 1878. Whatever the origin, we all agree that we don’t want bugs in our systems, our hardware, our code. With computer systems long past the size where physical ...

Making It Easy To Get It Right

by Drew Barbier on SiFive
teaser image Today, SiFive is excited to announce the general availability of the Q3 2019 Engineering Update, packed with new features, tools, and improvements. In the first SiFive quarterly update, we discussed the transition from the “Information Age” to the “Experience Age.” In the Q3 Engineering Update, SiFive is delivering on our customer experience mantra: “Make It Easy” and “Get It Right.” - two principles at the heart of our Sales, FAE, and Engineering mindset for supporting and enabling our ...

The SiFive Tech Symposiums are Heading To Portland and Seattle This Month – See You There!

by Swamy Irrinki on SiFive
We’re confirming seats in Portland and Seattle for the Pacific Northwest leg of our worldwide 2019 SiFive Tech Symposiums. We are pleased to have Mentor, A Siemens Business as our co-host, and Lauterbach, a leader in microprocessor development tools, as our partner in both cities. The Portland symposium will take place Tuesday, October 22 at the Portland Community College. Our Seattle symposium will be on Wednesday, October 23 at thinkspace Seattle. All of the SiFive Tech Symposiums have ...

The SiFive Tech Symposiums in Portland and Seattle are a Wrap

by Purvi Shenoy on SiFive
teaser image Our SiFive Tech Symposiums in Portland and Seattle were a big success, thanks in large part to our co-host, Mentor, a Siemens business; and our partner, Lauterbach, a leader in microprocessor development tools. Many leading OEMs were in attendance, such as Amazon, Facebook, Intel, Microsoft and Google There were presentations by the RISC-V Foundation, SiFive, Mentor and Lauterbach, as well as other ecosystem partners. We’d like to offer our thanks to the faculty and students at Portland ...

SiFive’s Tech Symposiums and Workshops Throughout South America Included Participation by Both Academia and Industry

by Swamy Irrinki on SiFive
teaser image We completed our tour through South America, which included tech symposiums and workshops in São Paulo, Porto Alegre, Montevideo, Buenos Aires and Bucaramanga. We are proud to have co-hosted these events with South America’s most prestigious universities, including the Polytechnic School of the University of São Paulo (Poli-USP), the Federal University of Rio Grande do Sul (UFRGS), the Universidad Católica del Uruguay (UCU), the University of Bueno Aires (UBA), the Universidad Industrial de ...

SiFive Completes its Global 52-City Tech Symposium/Workshop Tour

by Swamy Irrinki on SiFive
teaser image The RISC-V ISA is rapidly becoming the new standard for compute, and has literally spawned a worldwide revolution in the semiconductor industry. At the beginning of 2019, SiFive set out to foster education about SiFive’s RISC-V based technologies and to advance deeper collaboration within the global hardware community. We succeeded! We completed 52 Tech Symposiums/Workshops reaching 26 countries and six continents – reaching all corners of the world. Over 10,000 people attended these ...

Part 1: Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V

by Shubu Mukherjee on SiFive
teaser image This is the first in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). A DSA provides higher performance per watt than a general-purpose processor by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI ...

Part 2: High-Bandwidth Core Access to Accelerators: Enabling Optimized Data Transfers with RISC-V

by Shubu Mukherjee on SiFive
teaser image This is the second in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in SoCs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance. To recap, a DSA provides higher performance per watt by optimizing the specialized function it implements. Examples of ...

Part 3: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

by Shubu Mukherjee on SiFive
teaser image This is the third in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in system-on-chip (SoC) designs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance. Part #2 addressed the challenges associated with point-to-point ordering between cores and DSA ...

Students for GSoC projects wanted

by Pirmin Vogel on lowRISC: Collaborative open silicon engineering
We are excited to be back as a mentoring organisation for Google Summer of Code (GSoC) and are currently looking for enthusiastic students interested in doing a project with us. The GSoC initiative gives students the opportunity to spend the summer break gaining real-world hardware and software development experience while earning a stipend from Google. If you’re a student interested in applying, we strongly recommend you read up on how GSoC works and study the Google Summer of Code Student ...

Our SiFive Tech Symposiums in Costa Rica and Mexico Underscore the Global Adoption of the RISC-V ISA in Industry and Academia

by David Connelly on SiFive
teaser image Our SiFive Tech Symposiums in San José, Costa Rica and Mexico City, Mexico were well attended by not only those in industry, but in academia as well. There is a great deal of enthusiasm and engagement in RISC-V in both of these regions. Many new friendships were formed, and we look forward to the continued networking and idea sharing that open source brings to the hardware community. Western Digital co-hosted the symposium in Costa Rica, which was co-located with LASCAS 2020, the flagship ...

Part 4: High-Performance Interconnect for Accelerators: Enabling Optimized Data Transfers with RISC-V

by Shubu Mukherjee on SiFive
teaser image This is the fourth in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). Parts 1, 2 and 3 addressed key challenges such as data transfers between DSAs and the core complex, point-to-point ordering between cores and DSA memory, and data transfers between DSA and memories. This fourth instalment in the series will focus on the frequent interaction with and amongst cores, which is required by DSAs, and how the TileLink ...

El Correo Libre - Issue 25

by FOSSi Foundation on FOSSi Foundation - News & Posts
A new issue of the FOSSi Foundation’s monthly roundup of all things Open Source semiconductor design, El Correo Libre, is out there for all to enjoy. Follow the link for FOSSi-related FOSDEM 2020 video presentations, OpenPower updates and more RISC-V news. El Correo Libre Issue 24 - LibreCores - Medium

El Correo Libre Issue 25

by Gareth Halfacree on LibreCores - Medium
teaser image FOSDEM 2020 Video Presentations Now AvailableVideo presentations and, where available, slide decks have been published for the FOSDEM 2020 event, held in Brussels on the 1st and 2nd of February 2020. For the free and open-source silicon enthusiast, topics of interest are likely include: Drew Fustini on running Linux on RISC-V with open hardware and software; Anton Kuzmin on debugging IP cores on-hardware with free tools; Mario Behling on continuous integration (CI) for open hardware ...

RISC-V Foundation Formally Ratifies the Processor Trace Specification

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has announced the formal ratification of the processor trace specification, introducing a standardised trace encoder algorithm for the free and open-source instruction set architecture as a means of assisting with debugging. “RISC-V is rapidly gaining popularity due to its open and modular design that supports customisation on top of a standard core ISA,” says Krste Asanović, chair of the RISC-V Foundation Board of Directors. “The RISC-V ecosystem continues to showcase ...

Verilator - Verilator 4.030 Released

by Wilson Snyder on Veripool: News
Verilator 4.030 2020-03-08 Add split_var metacomment to assist UNOPTFLAT fixes, #2066. [Yutetsu TAKATSUKASA] Add support for $dumpfile and $dumpvars, #2126. [Alexander Grobman] Add support for dynamic arrays, #379. Add +verilator+noassert flag to disable assertion checking. [Tobias W\303\266lfel] Add check for assertOn for asserts, #2162. [Tobias W\303\266lfel] Add --structs-packed for forward compatibility. Fix genblk naming ...

The OpenPOWER Foundation Releases Compliance Definitions, Forms ISA Work Group

by Gareth Halfacree on FOSSi – AB Open
The OpenPOWER Foundation has officially released the compliance definition for its now-open instruction set architecture, defining test suite requirements for both POWER8 and POWER9 ISAs, and has pledged to form a new Work Group for ISA-related activities. “There is much excitement in the August 2019 announcement of open-sourcing the POWER Instruction Set Architecture (ISA), which provides the opportunity for experimentation and collaboration,” says Sandy Woodward, chair of the OpenPOWER ...

OTA: Lime Suite 20.01.0, cuSignal Acceleration, MIT’s RFocus, and More

by Gareth Halfacree on MyriadRF
teaser image The Lime Suite software bundle has received a significant update, to version 20.01.0, bundling new support for the LimeRFE software-defined front end, improved tuning and PLL locking, and other improvements. In its latest release, the open-source Lime Suite library comes with support for the LimeRFE front end, following on from last year’s addition of support for the final LimeNET Micro design. The new release also includes improvements and bug-fixes for PLL locking during calibration, ...

El Correo Libre - Issue 24

by FOSSi Foundation on FOSSi Foundation - News & Posts
A new issue of the FOSSi Foundation’s monthly roundup of all things Open Source semiconductor design, El Correo Libre, is out there for you to induldge in. News about upcoming Latch-up Cambridge, Massachusetts; bigger and better, how Microwatt OpenPOWER Core is Now GHDL Compatible, new uses for SpinalHDL and much more. El Correo Libre Issue 24 - LibreCores - Medium

El Correo Libre Issue 24

by Gareth Halfacree on LibreCores - Medium
teaser image Announcing Latch-Up Cambridge, MassachusettsFollowing up on the fantastic event we had in Portland, Oregon last year we have set our sights on the US East coast this year. We hope to make this Latch-Up slightly bigger and better this year, but in all other regards it will be a familiar setup in the spirit of previous Latch-Up and our long-running ORConf Latch-Up is a community-focused conference for open source semiconductor, digital design and embedded systems professionals and ...

Bigger Is Not Always Better: Builds Are Faster with Smaller Packages

by Tudor Timi on Verification Gentleman
teaser image One trend over the past few years is that the projects I've been working on tend to get bigger and more complicated. Bigger projects come with new challenges. Among these are the fact that it's much more difficult to keep the entire project in one's head, the need to synchronize with more developers because team sizes grow, a higher risk of having to re-write code because of poorly understood requirements or because some requirements change, and many more.There's one thing, though, that ...

Selectively Muting your BFMs to Speed up Simulation

by Matthew Ballance on Bits, Bytes, and Gates
Have you ever had the misfortune to be on the CC list for a "lively" email discussion where you're a stakeholder but only case about the conclusion? You can't simply ignore the traffic, because you do care about the conclusion to the discussion. But, it would be a significant time saver if you could just "tune out" all the discussion and simply be notified when a conclusion is reached. I've

Verilator - Verilator 4.028 Released

by Wilson Snyder on Veripool: News
Verilator 4.028 2020-02-08 Support attributes (public, isolate_assignments, etc.) in configuration files. Add -match to lint_off to waive warnings. [Philipp Wagner] Link Verilator binary partially statically, #2146. [Geza Lore] Verilation speed improvements, #2133, #2138. [Geza Lore] Support libgoogle-perftools-dev's libtcmalloc if available, #2137. [Geza Lore] Support $readmem/$writemem with assoc arrarys, #2100. [agrobman] ...

RISC-V Foundation Showcases Unprecedented Momentum and Growth at Embedded World 2020

by Jeffrey Osier-Mixon on Events – RISC-V International
The RISC-V Foundation booth will include live demonstrations and talks of RISC-V implementations from fourteen membersWHERE: Hall 3A, Booth No. 3A-536, NürnbergMesse, Messezentrum 1, 90471 Nürnberg, GermanyWHEN: Tuesday, Feb. 25 – Thursday, Feb. 27, 2020WHAT: At Embedded World 2020, the RISC-V Foundation will be exhibiting at Hall 3A, Booth No. 3A-536, and will feature live demonstrations from co-exhibiting RISC-V Foundation members Andes Technology, CHIPS Alliance, CloudBEAR, Codasip, ...

With SiFive, We Can Change the World

by Chris Lattner on SiFive
A Note from Chris Lattner, New SVP of Platform Engineering My quest is to build beautiful things that help change the world, and I’ve been fortunate to spend the last 15 years in Silicon Valley, working with some of the major players shaping all sorts of technology. Today, I’m super excited to join SiFive - the company I believe is best positioned to transform the silicon industry, to lead the Platform Engineering team. With experience building and leading large-scale production systems ...

High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

by Shubu Mukherjee on SiFive
teaser image Domain-specific accelerators (DSAs) are becoming increasingly common in system-on-chip (SoC) designs. A DSA provides higher performance per watt by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus (Figure 1). SoCs based on RISC-V offer a unique opportunity to optimize ...

At FOSDEM you can hear how we made our Ibex CPU core faster

by Greg Chadwick on lowRISC: Collaborative open silicon engineering
teaser image I’ll be giving a talk in the RISC-V devroom at FOSDEM on Saturday 1st February, in which I’ll describe how we are analysing and improving the performance of the Ibex RISC-V CPU core. I’ll discuss how Verilator is used to simulate Ibex running CoreMark and Embench and how I’ve analysed these simulations to identify major sources of stalls. This is used to inform what improvements should be made. Yosys was used to analyse the impact on area and clock frequency from these changes. I’ll talk ...

Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V

by Shubu Mukherjee on SiFive
teaser image Domain-specific accelerators (DSAs) are becoming increasingly common in systems-on-chip (SoCs). A DSA provides higher performance per watt than a general-purpose processor by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus. Unfortunately, data transfers between DSAs and the ...

High-Bandwidth Core Access to Accelerators: Enabling Optimized Data Transfers with RISC-V

by Shubu Mukherjee on SiFive
teaser image Domain-specific accelerators (DSAs) are becoming increasingly common in SoCs. A DSA provides higher performance per watt by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus (Figure 1). RISC-V offers a unique opportunity to optimize high-bandwidth communication between cores ...

Announcing Latch-Up in Cambridge, Massachusetts

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image The FOSSi Foundation is proud to announce Latch-Up (latchup.io), a conference dedicated to free and open source silicon to be held over the weekend of April 11th and 12th in Cambridge, Massachusetts, USA. Following up on the fantastic event we had in Portland, Oregon last year we set the sight on the US East coast this year. We hope to make it slightly bigger and better this year, but in all other regards it will be a familiar setup in the spirit of previous Latch-Up and our long-running ...

El Correo Libre Issue 23

by Gareth Halfacree on LibreCores - Medium
teaser image Announcing FOSSistanbul 2020FOSSi Foundation is inviting everyone interested in Free and Open Source Silicon to meet in Istanbul, Turkey, between 13th of March and 15th of March for FOSSistanbul. The event is free to attend, but professional tickets for €250 are available for individuals who are kind enough to donate for the event. We ask you to register now, as we have room for only 200. Do you have a project you want to talk about, an announcement to make, results you want to share with ...

Verilator - Verilator 4.026 Released

by Wilson Snyder on Veripool: News
Verilator 4.026 2020-01-11 Docker images are now available for Verilator releases. Support bounded queues. Support implication operator "|->" in assertions, #2069. [Peter Monsson] Support string compare, ato*, etc methods, #1606. [Yutetsu TAKATSUKASA] Support immediate cover statements. Ignore `uselib to end-of-line, #1634. [Frederic Antonin] Update FST trace API for better performance. Add vpiTimeUnit and allow to specify ...

Announcing FOSSistanbul

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image FOSSi Foundation is inviting everyone interested in Free and Open Source Silicon to meet in Istanbul, Turkey, between 13th of March and 15th of March. The event is free to attend, but professional tickets for 250 EUR are available for individuals who are kind enough to donate for the event. We ask you to register now, hurry up, we have room for only 200. Do you have a project you want to talk about, an announcement to make, results you want to share with us? We encourage attendees that ...

Open source mixed RTL synthesis

by Fatsie on Chips4Makers.io
Test designs It has been some time that I posted here and it's one of my New Year Resolutions to be more active here. As reported in a presentation @ ORConf 2019 development of the Chips4Makers low volume ASIC manufacturing process is going on. Plan for this year is to do a beta run where other people can join. In the ORConf presentation test chip tape-outs were presented. One of the test tape-outs contained a MOS6502 core and another a Z80 core. These cores are coming from FPGA ...

Open Source MPSoC Running 620 MIPS (CHStone) of RISC-V (RV32iMC) Programs on the ARTY Board (XC7A35T) Unleashed

by Tobias Strauch on CloudX
It is with great pleasure to announce the release of the Arduissimo open source project on github. The project is created to demonstrate the benefits of System Hyper Pipelining. The Arduissimo project is based on the RISC-V 32bit ISA. The 4 CUBE-V cores reach 620 MIPS on the famous ARTY board. The dynamic multithreading capabilities that come with the thrilling system hyper pipelining technique are outlandish. For further reading, please check out Arduissimo.

2019 - The "Nights and Weekends Projects" Year in Review

by Matthew Ballance on Bits, Bytes, and Gates
It's almost the end of 2019, and I've been thinking back over the year as well as thinking ahead to 2020. In past years, I've often evaluated my "nights and weekends" projects using the same metrics I'm evaluated on at work: projects completed, and results obtained. This year, I've started looking my my "nights and weekends" efforts through a different lens focused more on the knowledge I've

OTA: PiSDR 3.0 brings LimeNET Micro Support, Satellite News, and More

by Gareth Halfacree on MyriadRF
Luigi Cruz has released version 3.0 of PiSDR, an SD Card image for the Raspberry Pi pre-loaded with software defined radio tools compatible with the LimeSDR – and, as of this latest release, the LimeNET Micro too. This latest release of Cruz’ PiSDR includes support for the Raspberry Pi 4 Model B, the newest and most powerful of the single-board computer family and the first to offer up to 4GB of RAM and high-speed USB 3.0 connectivity to external devices including software defined radios, ...

ONiO Unveils Energy-Harvesting, Ultra-Low-Power ONiO.zero RISC-V Microcontroller

by Gareth Halfacree on FOSSi – AB Open
Internet of Things start-up ONiO has announced a new RISC-V microcontroller, the ONiO.zero, which it claims can be powered purely using energy harvested from the radio-frequency spectrum – no batteries required. “ONiO.zero is an ultra-low-power wireless MCU that uses energy harvesting technology,” ONiO, which focuses on the healthcare side of the IoT market, claims. “This means that the ONiO.zero solely operate on energy from its surroundings. No coin cell, no supercap, no lithium, no ...

Writing a Task-Based Cocotb BFM

by Matthew Ballance on Bits, Bytes, and Gates
Background The purpose of a Bus Functional Model (BFM) is to enable interacting with a design via a given protocol at a higher level of abstraction than the signal-level protocol, while knowing the bare minimum about the details of that protocol. Verification IP goes beyond these benefits to provide test plans, functional coverage, test sequence, and often protocol-specific benefits like

Evaluating DejaGnu results with Red Light Green Light

by green on The Moxie Blog
Last year I hacked up a tool in frustration called Red Light Green Light (rlgl) -- a proof-of-concept effort to demonstrate a git-centric way to manage "quality gates" in a CI/CD pipeline. A CI/CD quality gate is a process that evaluates the quality of a software artefact before allowing …

CRU: RISC-V Aplenty, USB3 PIPE Success, An Educational Dev Board, and More

by Gareth Halfacree on FOSSi – AB Open
Enjoy Digital has marked off two major milestones in its USB3 PIPE effort to support USB 3.0 on the built-in SerDes high-speed transceivers of major FPGA platforms – using open-source code and an open-source toolchain. “Current solutions for USB 3.0 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A – SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces) or external FIFO chip (FTDI FT60X or Cypress FX3),” the company explains. “With this ...

Cobham Gaisler Announces SPARC-Based LEON5, RISC-V NOEL-V Processor IP

by Gareth Halfacree on FOSSi – AB Open
Free and open source silicon pioneer Cobham Gaisler has announced two new processor IP families, the SPARC-based LEON5 and the RISC-V-based NOEL-V, which enter the company’s family of space-qualified products. “Cobham has a long-standing tradition of delivering open source solutions in order to expedite the development of next-generation computing devices for the space industry. For nearly 20 years, Cobham’s LEON processors, which are based on the SPARC ISA, have been used in RadHard and ...

Microchip Open Early Access Programme for RISC-V-Enabled PolarFire SoC FPGA Family

by Gareth Halfacree on FOSSi – AB Open
Microchip has opened an early access programme for its RISC-V-enabled PolarFire SoC family of field-programmable gate arrays (FPGAs), providing what the company claims is “the world’s first hardened real-time Linux-capable RISC-V-based microprocessor subsystem” to a low-power FPGA range. “Delivering the industry’s first RISC-V based SoC FPGA along with our Mi-V ecosystem, Microchip and its Mi-V partners are driving innovation in the embedded space, giving designers the ability to develop a ...

OpenHW Group Unveils CORE-V Chassis SoC Project, Building on PULP Project IP

by Gareth Halfacree on FOSSi – AB Open
OpenHW Group has announced a project to create a heterogeneous multi-core processor evaluation system-on-chip (SoC) design, featuring a high-performance 64-bit core coupled with a lower-power 32-bit core: the CORE-V Chassis. “The CORE-V Chassis project will help validate that serious silicon development is possible utilising the ethos of open-source hardware, IP, and tools,” claims OpenHW Group president and chief executive Rick O’Connor. “With the tape out of a functional evaluation SoC ...

Enjoy Digital Announces USB3 PIPE Project Successes for Open-Source USB 3.0 on FPGA SerDes

by Gareth Halfacree on FOSSi – AB Open
Enjoy Digital has marked off two major milestones in its USB3 PIPE effort to support USB 3.0 on the built-in SerDes high-speed transceivers of major FPGA platforms – using open-source code and an open-source toolchain. “Current solutions for USB 3.0 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A – SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces) or external FIFO chip (FTDI FT60X or Cypress FX3),” the company explains. “With this ...

El Correo Libre Issue 22

by Gareth Halfacree on LibreCores - Medium
teaser image Google Funds Development of Yosys Spartan 3, Spartan 6 SupportGoogle has provided funding to Symbiotic EDA to extend the popular Yosys package with Spartan 3 and Spartan 6 support — giving those who had been left out in the cold by Xilinx’ lack of support a free and open source way to continue using the parts. “This is a prime example of the benefits of FOSSi,” says Free and Open Source Silcon Foundation director Olof Kindgren. “There’s nothing wrong with the old Spartan devices other than ...

Verilator - Verilator 4.024 Released

by Wilson Snyder on Veripool: News
Verilator 4.024 2019-12-08 Support associative arrays (excluding [*] and pattern assignments), bug544. Support queues (excluding {} notation and pattern assignments), bug545. Add +verilator+error+limit to see more assertion errors. [Peter Monsson] Support string.toupper and string.tolower. Support $rewind and $ungetc. Support shortreal as real, with a SHORTREAL warning. Add -Wpedantic and -Wno-context for compliance ...

OTA: QO-100 FreeDV Transmissions, Lime-Powered 5G Testbeds, O-RAN Code, and More

by Gareth Halfacree on MyriadRF
Lime Microsystems has published an interview with Gerhard Burian, David Rowe, and Steve Sampson on using FreeDV Mode 2020 for transmitting digital voice via the Es’Hail-2 satellite’s amateur radio transponder (QO-100) using just 1,600 Hz of radio frequency bandwidth. “The bandwidth regulation on the [QO-100] narrow band transponder, being 2,700 Hz, prevents the use of other digital voice modes like D-Star or DMR, normally used on VHF/UHF,” Gerhard explains. “FreeDV is a narrowband mode, ...

Dependable Real-time Infrastructure for Safety-critical Computer (De-RISC) Aims for the Stars

by Gareth Halfacree on FOSSi – AB Open
Cobham Gaisler and fentISS have confirmed that the now-funded De-RISC project is forging ahead with its efforts to built a RISC-V based space-qualified computing platform centred in Europe, in partnership with Barcelona Supercomputing Centre and Thales. “With the first RISC-V based, fully European platform for space, De-RISC will guarantee access to made-in-Europe technology for aerospace applications,” claims Paco Gomez Molinero, chief executive officer of fentISS and coordinator of the ...

lowRISC 101: Introduction to lowRISC at the RISC-V Summit

by lowRISC on lowRISC: Collaborative open silicon engineering
With the recent announcement of OpenTitan, we at lowRISC had many great conversations about the work we do to produce high-quality open source hardware and software. A great place to continue these discussions is the RISC-V Summit in San Jose, CA (Dec 10 - 12, 2019). lowRISC will showcase its work in the conference track and in the exhibit hall. At booth 101, lowRISC will showcase its recent work and our engineers will be around to answer your questions. Stop by if you have questions about ...

SiFive Unveils Learn Inventor Educational RISC-V Development Board

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneer SiFive has announced the SiFive Learn Inventor, a development board aimed at the education and maker markets which merges the popular BBC micro:bit design with its own HiFive1. Launched via crowdfunding in late 2016, though not shipping in volume until January 2017, the SiFive HiFive1 took its design inspiration from the Arduino Uno microcontroller development board but with a Freedom E310 RISC-V chip at its heart. The SiFive Learn Inventor takes a more recent revision of ...

Final Countdown to RISC-V Summit in San Jose

by Jeffrey Osier-Mixon on Events – RISC-V International
teaser image The RISC-V Summit in San Jose starts on Monday, December 9. There is still time to register for both the Summit itself and the all-members working day on December 9, but the window is closing soon. This Summit will bring together the principal movers and shakers in the hardware industry. This is not an event to miss.For more information and details on the event, please see the agenda page. If you are not yet registered, visit the registration page.See you at the Summit! The post Final ...

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Last updated 29 March 2020 11:00 UTC