Planet LibreCores

…and out come SweRVolf | Olof Kindgren, Qamcom

by Olof Kindgren on Blog – RISC-V International 23 September 2021 02:38 UTC

One of the main FOSSi projects I’ve been running the last couple of years is SweRVolf, a FuseSoC-based reference platform for Western Digital’s family of RISC-V cores collectively called SweRV. I have written about SweRVolf before (e.g. here and here) so I won’t go too much into details other than noting that it was created to provide an easy way to get started with the SweRV cores for both software and hardware developers and be simple enough to grasp for aspiring engineers while still ...

RISC-V Launches the Open Hardware Diversity Alliance

by Kim McMahon on Announcements – RISC-V International 16 September 2021 13:52 UTC

Founded in Collaboration with the CHIPS Alliance, OpenPOWER Foundation, and Western Digital, the Alliance is Focused on Providing Support Programs, Learning Opportunities, and Mentoring for Women and Underrepresented Individuals in the Open Hardware Community   ZURICH – Sept. 16, 2021 – RISC-V International, a global open hardware standards organization, today announced the launch of the Open Hardware Diversity Alliance. The global Alliance, created ...

RISC-V Pioneer SiFive Opens its First UK Office, Announces Hiring Push

by Gareth Halfacree on FOSSi – AB Open 16 September 2021 10:02 UTC

RISC-V pioneer SiFive has opened its first office in the UK, and promises that staff there will enjoy “location flexibility” as the company looks to expand its presence and grow the RISC-V ecosystem. “I have exciting news to share,” Andrew Frame, formerly of Cambridge-based proprietary chip IP giant Arm, wrote in an announcement on LinkedIn. “As the very first UK employee of SiFive I’m pleased to announce that SiFive UK is here and we’re hiring.” Founded in 2015 by Krste Asanović, Yunsup ...

El Correo Libre Issue 42

by Gareth Halfacree on LibreCores - Medium 14 September 2021 05:43 UTC

Google Summer of Code (GSoC) 2021 was a Success!As summer comes to an end, we have also completed this year’s iteration of Google Summer of Code (GSoC). We at FOSSi Foundation are delighted to say that all of our students this summer successfully completed their projects. For multiple years now, FOSSi Foundation has acted as an umbrella organization for GSoC projects and this year we were particularly excited to have eleven students receiving mentorship from our community. All projects ...

...and out come SweRVolf

by Olof Kindgren on Tales from Beyond the Register Map 13 September 2021 16:49 UTC

 One of the main FOSSi projects I've been running the last couple of years is SweRVolf, a FuseSoC-based reference platform for Western Digital's family of RISC-V cores collectively called SweRV. I have written about SweRVolf before (e.g. here and here) so I won't go too much into details other than noting that it was created to provide an easy way to get started with the SweRV cores for both software and hardware developers and be simple enough to grasp for aspiring engineers while still ...

LAST CHANCE TO SUBMIT YOUR TALK TO THE 2021 RISC-V SUMMIT!

by RISC-V Community News on Blog – RISC-V International 09 September 2021 13:30 UTC

Time is running out! The Call for Papers is open until Friday, September 10 at 11:59 pm PST. (Yes – TOMORROW!) Don’t miss your opportunity to show off and share your contributions to the RISC-V ISA and ecosystem. The 2021 RISC-V Summit is a fully featured hybrid event so all speakers, attendees and sponsors have the opportunity to attend in-person or virtually. Make sure you’re part of the Open era of computing! ...

GSoC 2021 Was a Success!

by FOSSi Foundation on FOSSi Foundation - News & Posts 09 September 2021 00:00 UTC

As summer comes to an end, we have also completed this year’s iteration of Google Summer of Code (GSoC). We at FOSSi Foundation are delighted to say that all of our students this summer successfully completed their projects. For multiple years now, FOSSi Foundation has acted as an umbrella organization for GSoC projects and this year we were particularly excited to have eleven students receiving mentorship from our community. All projects were mentored by trusted community members, ...

Public Review Period Opens for Proposed RISC-V Scalar Cryptography Extensions

by Gareth Halfacree on FOSSi – AB Open 07 September 2021 14:08 UTC

The RISC-V Cryptography Extensions Task Group has opened a public review period on a raft of instruction set extensions, ahead of their planned adoption as official standards – including instructions for AES encryption and decryption and the SM3 hash and SM4 block cipher. “This specification has been developed by the RISC-V Cryptography Extensions Task Group under the governance of the Unprivileged and the Security Committees,” says Richard Newell, chair of the RISC-V Cryptography ...

European Commission Report Declares Open Source Software and Hardware to be a “Public Good”

by Gareth Halfacree on FOSSi – AB Open 06 September 2021 14:16 UTC

A team in the Future Networks arm of the European Commission has released a report on the impact of open source software and hardware on a series of areas of the European Union’s economy – and formally identifies it as a “public good.” “The objective of the study was to investigate and quantify the economic impact of OSS and OSH [Open Source Software and Open Source Hardware] on the European economy,” the study’s authors, working for the Directorate-General for Communications Networks, ...

RISC-V Cryptography Extensions Task Group Announces Public Review of the Scalar Cryptography Extensions

by Stephano Cetola on Blog – RISC-V International 03 September 2021 16:10 UTC

The Cryptography Extensions Task Group is delighted to announce the start of the public review period for the RISC-V Scalar Cryptography extensions. The RISC-V Scalar Cryptography extensions enable the acceleration of cryptographic workloads and add support for narrow 32 and 64-bit data paths. Additionally, these extensions dramatically lower the barrier to entry for secure and efficient accelerated cryptography in IoT and embedded devices. The proposed standard Scalar Cryptography ...

Google Summer of Code’21 at FOSSi Foundation: TensorCore Extension for Deep Learning | Nitin Mishra

by RISC-V Community News on Blog – RISC-V International 30 August 2021 17:28 UTC

Introduction This has been a great summer! I was fortunate enough to be accepted into the Google Summer Code(GSOC) program for the “TensorCore Extension for Deep Learning” project offered by the Free & Open Source Silicon(FOSSi) foundation under the supervision of Theodore Omtzigt with Steven Hoover and Ákos Hadnagy. And I’ve been able to reach most of the milestones that we set out to achieve. Read on to understand what this project is all about and how you can contribute to it! The link ...

OTA: SDR++ Hits v1.0.0, Bluetooth Hits 5.3, Elektro-L3 Goes LRIT, and More

by Gareth Halfacree on MyriadRF 27 August 2021 12:47 UTC

Alexandre Rouma’s SDR++ project, a cross-platform open-source package for software defined radio work with built-in support for LimeSDR-family hardware, has hit a milestone: the release of version 1.0.0. “For those who don’t know,” Alexandre explains, “SDR++ is a cross-platform (Windows, Linux, MacOS, BSD) and open-source general purpose receiver software meant to be simple and easy to use. It has advanced features like multi-vfo and uses a fully custom DSP making it very efficient.” We ...

Open source custom GitHub Actions runners with Google Cloud and Terraform | Antmicro

by Antmicro on Blog – RISC-V International 26 August 2021 19:26 UTC

As we continue our push for more software-driven hardware development as part of our work within CHIPS Alliance and RISC-V, we see an increasing need for scalable and flexible CI solutions that can be used with a mix of open source and proprietary components. By building on top of existing infrastructure such as GCP, GH Actions and Terraform, it’s possible to achieve noticeable performance gains, better traceability and runtime isolation for some of the advanced use cases we are helping our ...

Google Summer of Code’21 at FOSSI Foundation: M-extension Support for SERV | Zeeshan Rafique, RISC-V Ambassador

by RISC-V Community News on Blog – RISC-V International 23 August 2021 18:40 UTC

This project aims to design and integrate the integer “Multiplication and Division Unit (MDU)” with SERV core as a co-processor. The MDU will support all the instructions that are provided in “‘The RISC-V Instruction Set Manual. Volume I: Unprivileged ISA’ chapter 7, M-Standard Extension for Integer Multiplication and Division, Version 2.0”. This MDU is to be designed in a way that it would use most of the DSP resources on the targeted FPGA board. It would be generic and parameterized so ...

RISC-V RV32I R-Type | Maven Silicon

by Maven Silicon on Blog – RISC-V International 17 August 2021 13:00 UTC

This video explains the RV32I R-Type instructions. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. The post RISC-V RV32I R-Type | Maven Silicon appeared first on RISC-V International.

Announcing public review for RISC-V standard extensions Zfinx, Zdinx, Zhinx, and Zhinxmin

by Stephano Cetola on Blog – RISC-V International 10 August 2021 22:11 UTC

The RISC-V Zfinx Task Group is thrilled to announce the Zfinx extension (pronounced “z-f-in-x”) has entered the public review period. The Zfinx extension brings the much needed instructions for floating point in integer registers to the RISC-V ISA. The current public review period includes consideration of the the following Zfinx extensions: Zfinx – Single-precision floating point in integer registers Zdinx – Double-precision floating point in integer registers Zhinx – Half-precision ...

El Correo Libre Issue 41

by Gareth Halfacree on LibreCores - Medium 10 August 2021 08:54 UTC

FOSSi Foundation Welcomes Jonathan Balkind to the Board of DirectorsThe Free and Open Source Silicon Foundation is happy to announce today that Jonathan Balkind is joining the board of directors. Jonathan has been a trusted member of the FOSSi community for many years, where he has shown great skill in solving challenging technical problems, as well as teaching hardware design, and communicating the benefits of doing so openly. Jonathan is most well-known for his work on OpenPiton, an ...

StarFive open source single board hardware platform will be officially released by the end of Q3 2021

by Selina Zheng on Blog – RISC-V International 05 August 2021 17:50 UTC

At Starfive Technology, we have been committed to promoting the development of the global RISC-V open source software and hardware ecosystem since we were founded. Although the BeagleV-StarLight joint development board is no longer in mass production, we completely respect our partner’s decision and appreciate the contribution of all developers in the Beagle Board community. We look forward to collaborating again in the near future, and will continue to uphold our attitude in creating ...

seL4 Integrity Enforcement Proved for RISC-V

by Gernot Heiser on Blog – RISC-V International 03 August 2021 15:12 UTC

The seL4 Foundation and RISC-V International are pleased to announce that Ryan Barry from UNSW Sydney has completed the proof that the seL4 microkernel on the RISC-V architecture enforces the key security property of integrity. The proof shows that seL4 will only allow a thread to access an object or memory resource if the access is explicitly authorised by a capability. Specifically, user code cannot write to memory for which it does not hold a write capability (nor will the kernel perform ...

“中国信芯” 再迈一步，万向区块链携生态伙伴举办RISC-V区块链行业工作组首次公开活动

by Wanxiang Blockchain on Blog – RISC-V International 03 August 2021 13:17 UTC

(点击这里查看原文) 由上海科技大学和中国科学院软件研究所联合主办，中国RISC-V产业联盟（CRVIC）、中国开放指令生态联盟（CRVA）、CNRV社区协办的第一届「RISC-V中国峰会」于日前盛大开幕。6月24日，万向区块链作为RISC-V 区块链行业工作组（Blockchain SIG）的发起单位，携手上下游生态企业在上海科技大学（张江校区）举办“区块链+RISC-V”专场论坛及研讨会。   RISC-V区块链行业工作组于今年2月由万向区块链携手摩联科技、跃昉科技、赛昉科技、SiFive共同发起成立，致力于通过研究探索芯片和区块链技术的整合构筑“中国信芯”（Chinese ...

OTA: New LimeNET Gets AMD Ryzen Power, uSDR Launched, Open RAN Competition, and More

by Gareth Halfacree on MyriadRF 30 July 2021 04:49 UTC

Lime Microsystems has announced a new version of its LimeSDR-powered LimeNET 5G-capable software-defined radio-network-in-a-box – now featuring a 16-core high-performance AMD Ryzen processor. “We are excited to collaborate with Lime Microsystems and the LimeNET ecosystem,” said AMD’s senior director of applications engineering Kun-Yip Liu of the project, “to enable innovative and high-performance 5G edge services running on AMD Ryzen and embedded processors.” “LimeNET powered by AMD leading ...

The 2021 RISC-V Summit Will Demonstrate Adoptions and Technical Advances This December in San Francisco

by Kim McMahon on Announcements – RISC-V International 28 July 2021 14:00 UTC

ZURICH and SAN FRANCISCO – July 28, 2021 – RISC-V International announced the 2021 RISC-V Summit that will bring together the open hardware community for three days of deep technical talks, industry updates, networking, and more. The RISC-V Summit will be held at Moscone West in San Francisco from December 6-8, 2021, and will feature hybrid in-person and virtual activities to connect with a global audience. “Every year the RISC-V Summit draws larger crowds who gather with other RISC-V ...

Wavious Releases a RISC-V LPDDR4x/5 PHY as an Apache-Licensed Open-Source Project

by Gareth Halfacree on FOSSi – AB Open 21 July 2021 15:16 UTC

Wavious, a fabless semiconductor company which offers a platform based on mix-and-match “chiplets,” has launched a RISC-V-powered open-source LPDDR4x/5 PHY – under the permissive Apache 2.0 licence. “We are strong believers in open-source hardware and software,” the company said in its announcement, “and Wavious is dedicated to making significant contributions to the open source community. Open-source HW [hardware] and chiplets are both necessary to remove barriers to entry and to drive ...

Life in a Formal Verification Lane | Shivani Shah

by Shivani Shah on Blog – RISC-V International 20 July 2021 17:28 UTC

This summer, I got the opportunity to work as a Formal Verification Intern with Axiomise for six weeks. I’m a keen designer and love working in design and architecture. Although, I’ve not started my professional career yet, I have done most of my projects as a designer in my undergraduate and postgraduate studies. Having said that, I was always curious to know – how do we test that the design works? How is verification done in the industry? I had a prior design experience in building ...

What You Need to Know About Verilator Open Source Tooling | Rob Mains, CHIPS Alliance

by Rob Mains on Blog – RISC-V International 19 July 2021 19:06 UTC

Verilator is a high performance, open source functional simulator that has gained tremendous popularity in its usage and adoption in the verification of chip design. The ASIC development community has widely embraced Verilator as an effective, often even superior alternative to proprietary solutions, and it is now the standard approach in RISC-V CPU design as the community has worked to provide Verilator simulation capabilities out of the box. CHIPS Alliance and RISC-V leaders Antmicro and ...

A Free RISC-V CPU Core Builder – Democratizing CPUs | Steve Hoover, Redwood EDA

by Steve Hoover on Blog – RISC-V International 14 July 2021 14:58 UTC

There are now over a hundred RISC-V CPU cores listed in the RISC-V Exchange! Amazing. If you need a RISC-V CPU core, you’ll likely be able to find one that suits your needs… if you evaluate a hundred CPU cores to find it. Or, now, you can configure exactly the core you need, and have it built in seconds, for free! WARP-V is the most flexible RISC-V CPU core available, and recently, Indiana University student, Adam Ratzman, created an online configurator for WARP-V. If you need a ...

El Correo Libre Issue 40

by Gareth Halfacree on LibreCores - Medium 13 July 2021 05:46 UTC

Google Summer of Code (GSoC) Class of 2021The FOSSi Foundation is happy to introduce our Google Summer of Code Class of 2021 projects. This year we are grateful that we have been granted eleven slots by Google to support projects and students. We are thankful for all mentors who volunteered to supervise students, and we’re looking forward to a great summer working together on Free and Open Source Silicon projects.Virtual FPGA Lab (Bala Dhinesh)Mentored by Kunal Ghosh, Ákos Hadnagy, and ...

FOSSi Foundation welcomes Jonathan Balkind on the board of directors

by FOSSi Foundation on FOSSi Foundation - News & Posts 13 July 2021 00:00 UTC

The Free and Open Source Silicon Foundation is happy to announce today that Jonathan Balkind is joining the board of directors. Jonathan has been a trusted member of the FOSSi community for many years, where he has shown great skill in solving challenging technical problems, as well as teaching hardware design, and communicating the benefits of doing so openly. Jonathan is most well-known for his work on OpenPiton, an open source research processor which can be scaled up to multiple ...

RISC-V RV32I Assembly – Multiplication | Maven Silicon

by Maven Silicon on Blog – RISC-V International 12 July 2021 21:11 UTC

This video shows how we can implement the Multiplication using add and shift RV32I instructions. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc.   To know more, explore our RISC-V courses. The post RISC-V RV32I Assembly – Multiplication | Maven Silicon appeared first on RISC-V International.

The Importance of Increasing Diversity in the Open Source Community

by Kim McMahon on Blog – RISC-V International 08 July 2021 15:03 UTC

It’s no secret that the past twenty years has seen remarkable progress in technology innovation.  Smartphones opened up a whole new ecosystem of applications and possibilities, cars have become more connected and safer, and there are now RISC-V based software systems created to work in space! We’ve truly created a world that is unlike anything we’ve ever seen. As globalization promotes the exchange of ideas across borders, we’re continuing to reap the benefits of collaboration in our highly ...

NeuralScale: Industry Leading General Purpose Programmable NPU Architecture based on RISC-V

by Mark Zhan on Blog – RISC-V International 06 July 2021 20:49 UTC

AI and its diverse applications have seen significant increasing demand for AI computing in clouds over the last few years. Typical AI-enabled services include image and speech recognition, natural language processing, medical diagnosis, visual search, and personalized recommendations. AI computing in clouds includes two distinct workloads: training and inference. AI inference is reported to constitute more than 95% of AI computing workloads in clouds.  Meanwhile, we have seen significant ...

A Process Independent Power Optimised Register File Architecture

by Tony Stansfield on Blog – RISC-V International 30 June 2021 20:29 UTC

Overview This white paper describes how low-power memory technology, originally designed for large, high density, SRAMs has been enhanced and adapted to deliver low-power, low-voltage register files. Introduction There is a large, and growing, class of applications for which power is a critical factor, sometimes as a result of a desire to add increased functionality to already power-constrained devices, and in some cases where on-chip SRAM gives the most power efficient implementations. For ...

Wanxiang Blockchain Organized the First Public Activity of RISC-V Blockchain SIG with Partners

by Wanxiang Blockchain on Blog – RISC-V International 29 June 2021 21:39 UTC

On June 24, during the RISC-V World Conference China 2021 hosted by ShanghaiTech University, Institute of Software Chinese Academy of Sciences, CRVIC, CRVA and CNRV, Wanxiang Blockchain, as one of the initiators of RISC-V Blockchain Special Interest Group (SIG), organized a Blockchain + RISC-V Forum and Workshop. The RISC-V Blockchain SIG, jointly established in February 2021 by Wanxiang Blockchain, ...

OTA: OpenBSC Setup Scripts, 80MSPS from a LimeSDR Mini, a Satellite Hunt, and More

by Gareth Halfacree on MyriadRF 29 June 2021 09:46 UTC

Community member Bastien Baranoff has shared scripts for getting a Raspberry Pi system running Ubuntu Server up-and-running as an open cellular base station with Osmocom’s OpenBSC and a LimeSDR. Designed for Raspberry Pi systems running Canonical’s free and open source Ubuntu Server Linux distribution, Bastien’s scripts begin by installing the necessary software for turning a LimeSDR software-defined radio into a cellular base station. The first script automates the installation of ...

Version 3.9.0 released

by Esko Pekkarinen on Kactus2: News 29 June 2021 06:07 UTC

New PythonAPI for accessing Kactus2 data+ New interfaces for IP-XACT data read and modify+ Generator runs for selected generators e.g. Verilog New Python console in graphical user interface+ Run interactive scripts+ View command history+ Save and run script files Kactus2 editors adapted to new interfaces+ Ports+ Parameters+ Fields+ Field resets+ Registers+ Address block+ Memory maps+ Files+ File sets+ Component instantiations+ Port maps+ Port abstractions+ Bus interfaces Added ...

GSoC Class of 2021

by FOSSi Foundation on FOSSi Foundation - News & Posts 28 June 2021 00:00 UTC

The FOSSi Foundation is happy to introduce our Google Summer of Code Class of 2021 projects. This year we are grateful that we have been granted eleven slots by Google to support projects and students. We are thankful for all mentors who volunteered to supervise students, and we’re looking forward to a great summer working together on Free and Open Source Silicon projects. These projects are our “GSoC Class of 2021”. Please give our students a warm welcome! Virtual FPGA Lab (Bala ...

RISC: Open Hardware

by David Patterson on Blog – RISC-V International 25 June 2021 13:20 UTC

Peggy and David Patterson, pardee professor of computer science, Emeritus, University of California at Berkeley, talk about RISC and how it brings openness to hardware design. He says in the beginning ease of use was the top priority with technology, and now we are paying the price with security. They also discuss: Why testing can reveal the presence of bugs but can’t reveal the absence of bugs. How RISC lets someone do security themselves. How to inspire the next ...

The Heart of SiFive is Performance, Intelligence, & Essential

by Patrick Little on SiFive 22 June 2021 13:00 UTC

Introducing the new era of SiFive Performance for RISC-V When I joined SiFive last year, I found a dedicated team working on great technology with a vision to do no less than to change the world. As I talked to our customers and partners, it was clear that while we had satisfied users, the industry expected and desired greater things from SiFive. The message was loud and clear that SiFive needed to push the boundaries of what’s possible to bring high value, differentiated products to ...

Embedded Programming and IoT – Memory Management Criticality!

by Tan Rahman on Blog – RISC-V International 21 June 2021 13:05 UTC

There are two types of IoT devices: high-end devices and low-end devices. The operating systems that are used for high-end devices include fully functional ones like Windows, Linux or Android. For example, Amazon’s echo device uses Fire OS based on Android whilst Samsung smartwatches use Tizen based on Linux. These devices are wired for power or have batteries that are regularly charged. However, low-end devices have a very small amount of memory and work with a low amount of energy often ...

RISC-V QEMU Part 1: Privileged ISA v1.10, HiFive1 and VirtIO

by Michael Clark on SiFive 15 October 2018 23:40 UTC

This post covers recent development in RISC-V QEMU, the open source machine emulator and virtualizer. We’ve been playing a game of catch-up with the hardware folks so that we can match the capabilities of the Freedom U500 SDK. We’re not quite there yet, but we’ve made some important improvements that will allow for a more usable emulator. First, some background on software emulation of Instruction Set Architectures. There are several forms of emulators and they fall broadly into these ...

All Aboard, Part 10: How to Contribute to the RISC-V Software Ecosystem

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

We recently announced the HiFive Unleashed, a development board for Freedom U540-C000, the world's first Linux-capable RISC-V ASIC. The announcement of this board roughly lined up with the first upstream releases of Linux and glibc that contain RISC-V support. As a result, our news has driven a lot of interest from the open source software community -- that was really the whole point of announcing the board in the first place, so in that sense it's working out very well. This new wave of ...

SiFive’s Approach to Embedding Intelligence Everywhere

by Tom Simon on SiFive 29 April 2020 00:52 UTC

Published by SemiWiki. Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made over many years. RISC-V was conceived with a clean well-thought-out architecture and designed for expansion that would not create inconsistencies. Because it is open source, there is a rich set of ...

The SiFive 20G1 Update for 7-Series Core IP

by Drew Barbier on SiFive 15 October 2020 13:00 UTC

Faster, More Efficient SiFive 7-Series Core IP Today, we’re announcing the SiFive 20G1 6.0 update, which is focused on improving the 7-Series line of products. Our previous release, SiFive 20G1, was a comprehensive update that spanned from the 7-Series to the 2-Series, including U-, S-, and E-Cores. Similarly, the 20G1 6.0 update improves the performance, features, and functionality of SiFive 7-Series U-, S-, and E-Cores. Ever since the 7-Series introduction in 2018, SiFive has been able to ...

All Aboard, Part 2: Relocations in ELF Toolchains

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

Our first stop on our exploration of the RISC-V toolchain will be an overview of ELF relocations and how they are used by the RISC-V toolchain. We'll shy away from discussing linker relaxations and their impact on performance for a follow-up blog post so this doesn't get too long. The example has been carefully constructed to be unrelaxable as to avoid confusion. Additionally, we're only going to discuss the relocations used by statically linked executables, avoid discussing position ...

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part I

by Camille Kokozaki on SiFive 27 March 2019 23:37 UTC

SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing, Calista Redmond was just appointed the new CEO of the RISC-V Foundation). He shared a slide showing the growing RISC-V ecosystem from tools vendors, to IP/semi chip ...

All Aboard, Part 1: The -march, -mabi, and -mtune arguments to RISC-V Compilers

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

Before we can board the RISC-V train, we'll have to take a stop at the metaphorical ticket office: our machine-specific GCC command-line arguments. These arguments all begin with -m, and are all specific to the RISC-V architecture port. In general, we've tried to match existing conventions for these arguments, but like pretty much everything else there are enough quirks to warrant a blog post. This blog discusses the arguments most fundamental to the RISC-V ISA: the -march, -mabi, ...

All Aboard, Part 9: Paging and the MMU in the RISC-V Linux Kernel

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

This entry will cover the RISC-V port of Linux's memory management subsystem. Since the vast majority of the memory management code in Linux is architecture-independent, the vast majority of our memory management code handles interfacing with our MMU, defining our page table format, and interfacing with drivers that have memory allocation constraints. I will refrain from discussing the RISC-V memory model in this blog, both because it isn't yet finished and because it's complicated ...

All Aboard, Part 3: Linker Relaxation in the RISC-V Toolchain

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

Last week's blog entry discussed relocations and how they apply to the RISC-V toolchain. This week we'll be delving a bit deeper into the RISC-V linker to discuss linker relaxation, a concept so important it has greatly shaped the design of the RISC-V ISA. Linker relaxation is a mechanism for optimizing programs at link-time, as opposed to traditional program optimization which happens at compile-time. This blog will follow an example linker relaxation through the toolchain, demonstrate an ...

All Aboard, Part 4: The RISC-V Code Models

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

The RISC-V ISA was designed to be both simple and modular. In order to achieve these design goals, RISC-V minimizes one of the largest costs in implementing complex ISAs: addressing modes. Addressing modes are expensive both in small designs (due to decode cost) and large designs (due to implicit dependencies). RISC-V only has three addressing modes: PC-relative, via the auipc, jal and br* instructions. Register-offset, via the jalr, addi and all memory instructions. Absolute, via the lui ...

Part 3: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

by Shubu Mukherjee on SiFive 30 January 2020 17:21 UTC

This is the third in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in system-on-chip (SoC) designs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance. Part #2 addressed the challenges associated with point-to-point ordering between cores and DSA ...

All Aboard, Part 7: Entering and Exiting the Linux Kernel on RISC-V

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

Continuing our journey into the RISC-V Linux kernel port, this week we'll discuss context switching. Context switching is one of the more important parts of an architecture port: it is all but impossible to completely abstract away the details of entering and exiting the kernel, Since this is on many critical paths (system calls and scheduling) it must go fast, but since it's the one line of protection the kernel has from userspace it must also be secure. Traps on RISC-V Systems One of the ...

All Aboard, Part 6: Booting a RISC-V Linux Kernel

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

This post begins a short detour into Linux land, during which we'll be discussing the RISC-V Linux kernel port. SiFive has recently announced the Linux-capable U54-MC RISC-V Core IP, and our Linux port was recently submitted to linux-next, Linux's staging branch, so assuming that everything goes smoothly we should be merged at the end of the next merge window. Along with Linux we should soon have the full suite of core system components upstream, both for embedded systems (via binutils, ...

Dhrystone Performance Tuning on the Freedom Platform

by Fu-Ching Yang on SiFive 06 August 2019 13:00 UTC

For consumers of low-end processors, the Dhrystone benchmark can be a valuable tool for estimating performance. Due to the nature of the Dhrystone benchmark, high-end Application Processor performance is incompletely represented by a Dhrystone score. For processor providers a Dhrystone score is a commonly used metric for instruction throughput comparison in early stage evaluation. To fairly compare Dhrystone scores, the test conditions must be published. To that end SiFive offers two ...

Last Week in RISC-V: October 19, 2018

by Palmer Dabbelt on SiFive 24 October 2018 04:33 UTC

It's been another week, which means it's time to find another host for "Last Week in RISC-V". This week we're going to attempt a blog at riscv.org, which will hopefully be a good long-term home for this series of articles. As usual, you can find this week's entry on GitHub. glibc Floating-Point Test Suite As part of the RV32I glibc submission process, Zong from Andes has submitted a glibc patch set to fix a generic floating-point bug that crosses the boundary between GCC and glibc. ...

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part II

by Camille Kokozaki on SiFive 14 May 2019 23:06 UTC

During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded Processors, and E Cores 32-bit Embedded Processors. Embedded intelligence allows mixing of application cores with embedded cores, extensible custom instructions, ...

The Design Revolution in APAC and Australia

by Aijaz Qaisar on SiFive 17 July 2019 23:45 UTC

Highlights From the SiFive Tech Symposiums In its endeavor to educate the tech world about the benefits of the RISC-V ISA, SiFive just completed its APAC and Australia series of tech symposiums. Throughout the month of June, symposiums were held in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney. The audience included academia, the business industry, and many RISC-V ecosystem partners. On average, in all seven cities, 60% of the audience came from the tech industry and 40% belonged to ...

SiFive Strengthens Foothold in Storage Applications for Data-Centric AI Computing

by James Prior on SiFive 20 November 2020 14:00 UTC

SiFive RISC-V processors are powering flash drives in production as well as addressing emerging In-Storage Computing (ISC) needs In the current digital age, where data powers increasing levels of decision-making, industrial control and automation, efficient data storage, movement, and processing become the focal point of technological innovations in silicon, system, and software. At SiFive, we have been designing and optimizing RISC-V based domain-specific solutions to address the ...

Last Week in RISC-V: Sept 28, 2018

by Palmer Dabbelt on SiFive 19 October 2018 20:37 UTC

I spent too much time writing my single entry this week so it's all I have. The issue itself is somewhat complex, so I thought it warranted a deep dive. Relaxing R_RISCV_PCREL_* in the Presence of Addends Jim recently found an issue with our ELF relocation scheme. While technically it's a somewhat wide-ranging ABI bug, the actual set of cases in which the issue will manifest is somewhat restricted -- in other words: while I'm sure the proper long-term fix for this will be quite involved, ...

Last Week in RISC-V: August 31, 2018

by Palmer Dabbelt on SiFive 15 October 2018 23:40 UTC

Welcome to the first issue of "Last Week in RISC-V", a weekly newsletter tracking the RISC-V community. This newsletter was born out of a discussion in SiFive's internal RISC-V software team and I'm compiling it so it'll have a somewhat heavy focus on the open source software community for now as that's where I spend most of my time. The general idea behind "Last Week in RISC-V" is that the RISC-V ecosystem is getting big enough that it's impossible for any single person to ...

Embedded Intelligence Everywhere

by Jack Kang on SiFive 04 January 2019 17:43 UTC

In 2018, we saw the rapid proliferation of the RISC-V architecture, with commercial deployments of SiFive Core IP in a broad range of applications ranging from wearables and edge devices to the enterprise core. Modern compute workloads are evolving rapidly and require the ability to scale performance on demand and very often have real-time, deterministic requirements. This diversity of workloads poses computational challenges that can be resolved only by domain-specific architectures. With ...