Planet LibreCores

El Correo Libre Issue 23

by Gareth Halfacree on LibreCores - Medium
teaser image Announcing FOSSistanbul 2020FOSSi Foundation is inviting everyone interested in Free and Open Source Silicon to meet in Istanbul, Turkey, between 13th of March and 15th of March for FOSSistanbul. The event is free to attend, but professional tickets for €250 are available for individuals who are kind enough to donate for the event. We ask you to register now, as we have room for only 200. Do you have a project you want to talk about, an announcement to make, results you want to share with ...

Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V

by Shubu Mukherjee on SiFive
teaser image Domain-specific accelerators (DSAs) are becoming increasingly common in systems-on-chip (SoCs). A DSA provides higher performance per watt than a general-purpose processor by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus. Unfortunately, data transfers between DSAs and the ...

Verilator - Verilator 4.026 Released

by Wilson Snyder on Veripool: News
Verilator 4.026 2020-01-11 Docker images are now available for Verilator releases. Support bounded queues. Support implication operator "|->" in assertions, #2069. [Peter Monsson] Support string compare, ato*, etc methods, #1606. [Yutetsu TAKATSUKASA] Support immediate cover statements. Ignore `uselib to end-of-line, #1634. [Frederic Antonin] Update FST trace API for better performance. Add vpiTimeUnit and allow to specify time as string, #1636. [Stefan ...

Announcing FOSSistanbul

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image FOSSi Foundation is inviting everyone interested in Free and Open Source Silicon to meet in Istanbul, Turkey, between 13th of March and 15th of March. The event is free to attend, but professional tickets for 250 EUR are available for individuals who are kind enough to donate for the event. We ask you to register now, hurry up, we have room for only 200. Do you have a project you want to talk about, an announcement to make, results you want to share with us? We encourage attendees that ...

Open source mixed RTL synthesis

by Fatsie on Chips4Makers.io
Test designs It has been some time that I posted here and it's one of my New Year Resolutions to be more active here. As reported in a presentation @ ORConf 2019 development of the Chips4Makers low volume ASIC manufacturing process is going on. Plan for this year is to do a beta run where other people can join. In the ORConf presentation test chip tape-outs were presented. One of the test tape-outs contained a MOS6502 core and another a Z80 core. These cores are coming from FPGA ...

Open Source MPSoC Running 620 MIPS (CHStone) of RISC-V (RV32iMC) Programs on the ARTY Board (XC7A35T) Unleashed

by Tobias Strauch on CloudX
It is with great pleasure to announce the release of the Arduissimo open source project on github. The project is created to demonstrate the benefits of System Hyper Pipelining. The Arduissimo project is based on the RISC-V 32bit ISA. The 4 CUBE-V cores reach 620 MIPS on the famous ARTY board. The dynamic multithreading capabilities that come with the thrilling system hyper pipelining technique are outlandish. For further reading, please check out Arduissimo.

SiFive Completes its Global 52-City Tech Symposium/Workshop Tour

by Swamy Irrinki on SiFive
teaser image The RISC-V ISA is rapidly becoming the new standard for compute, and has literally spawned a worldwide revolution in the semiconductor industry. At the beginning of 2019, SiFive set out to foster education about SiFive’s RISC-V based technologies and to advance deeper collaboration within the global hardware community. We succeeded! We completed 52 Tech Symposiums/Workshops reaching 26 countries and six continents – reaching all corners of the world. Over 10,000 people attended these ...

SiFive’s Tech Symposiums and Workshops Throughout South America Included Participation by Both Academia and Industry

by Swamy Irrinki on SiFive
teaser image We completed our tour through South America, which included tech symposiums and workshops in São Paulo, Porto Alegre, Montevideo, Buenos Aires and Bucaramanga. We are proud to have co-hosted these events with South America’s most prestigious universities, including the Polytechnic School of the University of São Paulo (Poli-USP), the Federal University of Rio Grande do Sul (UFRGS), the Universidad Católica del Uruguay (UCU), the University of Bueno Aires (UBA), the Universidad Industrial de ...

OTA: PiSDR 3.0 brings LimeNET Micro Support, Satellite News, and More

by Gareth Halfacree on MyriadRF
Luigi Cruz has released version 3.0 of PiSDR, an SD Card image for the Raspberry Pi pre-loaded with software defined radio tools compatible with the LimeSDR – and, as of this latest release, the LimeNET Micro too. This latest release of Cruz’ PiSDR includes support for the Raspberry Pi 4 Model B, the newest and most powerful of the single-board computer family and the first to offer up to 4GB of RAM and high-speed USB 3.0 connectivity to external devices including software defined radios, ...

ONiO Unveils Energy-Harvesting, Ultra-Low-Power ONiO.zero RISC-V Microcontroller

by Gareth Halfacree on FOSSi – AB Open
Internet of Things start-up ONiO has announced a new RISC-V microcontroller, the ONiO.zero, which it claims can be powered purely using energy harvested from the radio-frequency spectrum – no batteries required. “ONiO.zero is an ultra-low-power wireless MCU that uses energy harvesting technology,” ONiO, which focuses on the healthcare side of the IoT market, claims. “This means that the ONiO.zero solely operate on energy from its surroundings. No coin cell, no supercap, no lithium, no ...

Evaluating DejaGnu results with Red Light Green Light

by green on The Moxie Blog
Last year I hacked up a tool in frustration called Red Light Green Light (rlgl) -- a proof-of-concept effort to demonstrate a git-centric way to manage "quality gates" in a CI/CD pipeline. A CI/CD quality gate is a process that evaluates the quality of a software artefact before allowing …

CRU: RISC-V Aplenty, USB3 PIPE Success, An Educational Dev Board, and More

by Gareth Halfacree on FOSSi – AB Open
Enjoy Digital has marked off two major milestones in its USB3 PIPE effort to support USB 3.0 on the built-in SerDes high-speed transceivers of major FPGA platforms – using open-source code and an open-source toolchain. “Current solutions for USB 3.0 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A – SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces) or external FIFO chip (FTDI FT60X or Cypress FX3),” the company explains. “With this ...

Cobham Gaisler Announces SPARC-Based LEON5, RISC-V NOEL-V Processor IP

by Gareth Halfacree on FOSSi – AB Open
Free and open source silicon pioneer Cobham Gaisler has announced two new processor IP families, the SPARC-based LEON5 and the RISC-V-based NOEL-V, which enter the company’s family of space-qualified products. “Cobham has a long-standing tradition of delivering open source solutions in order to expedite the development of next-generation computing devices for the space industry. For nearly 20 years, Cobham’s LEON processors, which are based on the SPARC ISA, have been used in RadHard and ...

Microchip Open Early Access Programme for RISC-V-Enabled PolarFire SoC FPGA Family

by Gareth Halfacree on FOSSi – AB Open
Microchip has opened an early access programme for its RISC-V-enabled PolarFire SoC family of field-programmable gate arrays (FPGAs), providing what the company claims is “the world’s first hardened real-time Linux-capable RISC-V-based microprocessor subsystem” to a low-power FPGA range. “Delivering the industry’s first RISC-V based SoC FPGA along with our Mi-V ecosystem, Microchip and its Mi-V partners are driving innovation in the embedded space, giving designers the ability to develop a ...

OpenHW Group Unveils CORE-V Chassis SoC Project, Building on PULP Project IP

by Gareth Halfacree on FOSSi – AB Open
OpenHW Group has announced a project to create a heterogeneous multi-core processor evaluation system-on-chip (SoC) design, featuring a high-performance 64-bit core coupled with a lower-power 32-bit core: the CORE-V Chassis. “The CORE-V Chassis project will help validate that serious silicon development is possible utilising the ethos of open-source hardware, IP, and tools,” claims OpenHW Group president and chief executive Rick O’Connor. “With the tape out of a functional evaluation SoC ...

Enjoy Digital Announces USB3 PIPE Project Successes for Open-Source USB 3.0 on FPGA SerDes

by Gareth Halfacree on FOSSi – AB Open
Enjoy Digital has marked off two major milestones in its USB3 PIPE effort to support USB 3.0 on the built-in SerDes high-speed transceivers of major FPGA platforms – using open-source code and an open-source toolchain. “Current solutions for USB 3.0 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A – SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces) or external FIFO chip (FTDI FT60X or Cypress FX3),” the company explains. “With this ...

El Correo Libre Issue 22

by Gareth Halfacree on LibreCores - Medium
teaser image Google Funds Development of Yosys Spartan 3, Spartan 6 SupportGoogle has provided funding to Symbiotic EDA to extend the popular Yosys package with Spartan 3 and Spartan 6 support — giving those who had been left out in the cold by Xilinx’ lack of support a free and open source way to continue using the parts. “This is a prime example of the benefits of FOSSi,” says Free and Open Source Silcon Foundation director Olof Kindgren. “There’s nothing wrong with the old Spartan devices other than ...

Verilator - Verilator 4.024 Released

by Wilson Snyder on Veripool: News
Verilator 4.024 2019-12-08 Support associative arrays (excluding [*] and pattern assignments), bug544. Support queues (excluding {} notation and pattern assignments), bug545. Add +verilator+error+limit to see more assertion errors. [Peter Monsson] Support string.toupper and string.tolower. Support $rewind and $ungetc. Support shortreal as real, with a SHORTREAL warning. Add -Wpedantic and -Wno-context for compliance testing. Add error on redefining preprocessor ...

OTA: QO-100 FreeDV Transmissions, Lime-Powered 5G Testbeds, O-RAN Code, and More

by Gareth Halfacree on MyriadRF
Lime Microsystems has published an interview with Gerhard Burian, David Rowe, and Steve Sampson on using FreeDV Mode 2020 for transmitting digital voice via the Es’Hail-2 satellite’s amateur radio transponder (QO-100) using just 1,600 Hz of radio frequency bandwidth. “The bandwidth regulation on the [QO-100] narrow band transponder, being 2,700 Hz, prevents the use of other digital voice modes like D-Star or DMR, normally used on VHF/UHF,” Gerhard explains. “FreeDV is a narrowband mode, ...

Dependable Real-time Infrastructure for Safety-critical Computer (De-RISC) Aims for the Stars

by Gareth Halfacree on FOSSi – AB Open
Cobham Gaisler and fentISS have confirmed that the now-funded De-RISC project is forging ahead with its efforts to built a RISC-V based space-qualified computing platform centred in Europe, in partnership with Barcelona Supercomputing Centre and Thales. “With the first RISC-V based, fully European platform for space, De-RISC will guarantee access to made-in-Europe technology for aerospace applications,” claims Paco Gomez Molinero, chief executive officer of fentISS and coordinator of the ...

lowRISC 101: Introduction to lowRISC at the RISC-V Summit

by lowRISC on lowRISC: Collaborative open silicon engineering
With the recent announcement of OpenTitan, we at lowRISC had many great conversations about the work we do to produce high-quality open source hardware and software. A great place to continue these discussions is the RISC-V Summit in San Jose, CA (Dec 10 - 12, 2019). lowRISC will showcase its work in the conference track and in the exhibit hall. At booth 101, lowRISC will showcase its recent work and our engineers will be around to answer your questions. Stop by if you have questions about ...

SiFive Unveils Learn Inventor Educational RISC-V Development Board

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneer SiFive has announced the SiFive Learn Inventor, a development board aimed at the education and maker markets which merges the popular BBC micro:bit design with its own HiFive1. Launched via crowdfunding in late 2016, though not shipping in volume until January 2017, the SiFive HiFive1 took its design inspiration from the Arduino Uno microcontroller development board but with a Freedom E310 RISC-V chip at its heart. The SiFive Learn Inventor takes a more recent revision of ...

Final Countdown to RISC-V Summit in San Jose

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
teaser image The RISC-V Summit in San Jose starts on Monday, December 9. There is still time to register for both the Summit itself and the all-members working day on December 9, but the window is closing soon. This Summit will bring together the principal movers and shakers in the hardware industry. This is not an event to miss.For more information and details on the event, please see the agenda page. If you are not yet registered, visit the registration page.See you at the Summit! The post Final ...

Think Silicon to Demonstrate its NEOX|V RISC-V GPGPU at the RISC-V Summit 2019

by Gareth Halfacree on FOSSi – AB Open
Think Silicon has announced the development of a general-purpose graphics processor (GPGPU) with 3D acceleration capabilities built on the free and open RISC-V instruction set architecture (ISA) – and claims it will be the first in the industry to demonstrate such a device working, at the RISC-V Summit later this month. “Building a GPGPU on RISC-V instruction set architecture is another significant milestone in the young history of Think Silicon,” says Think Silicon’s senior vice president ...

RISC-V Summit Member Day Schedule UPDATED

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
teaser image This is the schedule for Member Day on December 9, ongoing. Registration is required, as is RISC-V member status – see the Join page for details.UPDATE: Our apologies, the zoom links this morning were not working well. These are new dialup links for the meetings. I will keep this up to date in case anything changes, so be sure to check back prior to any particular meeting. 1pmISA Formal Model  https://zoom.us/j/9332682426Fast Interrupts  https://zoom.us/j/146488594Processor Trace  ...

CRU: RISC-V for Beginners, Sensors, and Browsers, MIPS Open Closes, and More

by Gareth Halfacree on FOSSi – AB Open
Bootlin’s Michael Opdenacker has published a guide to getting started with embedded Linux on RISC-V in just 40 minutes, as part of a presentation given during the Capitole du Libre 2019 event earlier this month. Building on a presentation first given at the Libre Software Meeting 2005, in which Opdenacker demonstrated how to get Linux 2.6 up and running on a QEMU-emulated Arm device in under 40 minutes, the new presentation was triggered by a range of changes – including the ...

Get started with OpenTitan

by Greg Chadwick on lowRISC: Collaborative open silicon engineering
Interested in trying out the recently announced OpenTitan? We’ve put together a video that goes through an overview of how the OpenTitan prototype system is put together and how to get up and running with our pre-built release (providing simulator binaries and pre-built FPGA images for the Nexys Video Artix-7 board). It follows the steps from the OpenTitan Quickstart Guide. You can find out more about OpenTitan from our announcement blog and the OpenTitan website.

Workshop on Open Source Design Automation (OSDA) 2020 Opens Call for Participation

by Gareth Halfacree on FOSSi – AB Open
The Workshop on Open Source Design Automation (OSDA), now on its second year, has announced a call for contributions with a deadline of the 12th of January 2020 – and is, as with the year before, taking place at the Conference on Design, Automation, and Test in Europe (DATE). “There is no doubt that proprietary EDA [Electronic Design Automation] tools are successful, mature, and are fundamental for hardware development,” write workshop organisers Clifford Wolf and Christian Kreig. “However, ...

OTA: LimeRFE Shipping Update, Signals Everywhere on the LimeSDR Mini, and More

by Gareth Halfacree on MyriadRF
The LimeRFE software-definable RF front-end has officially passed verification in its updated v1.0 revision form, with production of the backer boards on-track for a late-January shipping schedule. As detailed back in August, the LimeRFE board – which offers low-noise amplification, power amplification, and filtering under software control from the LimeSDR and LimeNET families of software defined radios – is entering into production as a slightly modified design. Compared to the prototype, ...

Bootlin’s Michael Opdenacker Gets You Started with Embedded Linux on RISC-V in Just 40 Minutes

by Gareth Halfacree on FOSSi – AB Open
Bootlin’s Michael Opdenacker has published a guide to getting started with embedded Linux on RISC-V in just 40 minutes, as part of a presentation given during the Capitole du Libre 2019 event earlier this month. Building on a presentation first given at the Libre Software Meeting 2005, in which Opdenacker demonstrated how to get Linux 2.6 up and running on a QEMU-emulated Arm device in under 40 minutes, the new presentation was triggered by a range of changes – including the ...

We Just Completed Five Energy-Filled Tech Symposiums and RISC-V Workshops Throughout the Middle East Region

by Aijaz Qaisar on SiFive
teaser image Our tour through the Middle East region included Istanbul, Amman, Cairo, Abu Dhabi and Dubai. This tour was dedicated to academia, and included presentations, tutorials and hands-on workshops. Attendees primarily consisted of PhD research scholars, professors and engineering students. It was humbling to see that the region’s universities have included the book, The RISC-V Reader: An Open Architecture Atlas, authored by SiFive Technical Adviser David Peterson and Co-Founder and Chief ...

Our SiFive Tech Symposiums in Pakistan Drew Over 2,500 Attendees!

by Shivaram Venkatesh Nellaiappan on SiFive
teaser image SiFive’s Tech Symposiums in Pakistan were a huge success, with the participation of more than 2,500 people from across the country. One of the symposiums was held at the NED University of Engineering and Technology in Karachi, and the other took place at the University of Engineering and Technology in Lahore. We are grateful to both of these universities for co-hosting these events with us, and to Lampro Mellon for partnering with us. All three were instrumental in making these symposiums ...

Wave Computing Shutters MIPS Open Programme with Immediate Effect

by Gareth Halfacree on FOSSi – AB Open
Wave Computing has officially shuttered its MIPS Open programme, providing “open use” to selected MIPS core IP and the underlying instruction set architecture, less than a year after the initiative was launched – and with zero advance warning. Wave Computing, which acquired the rights to the proprietary MIPS ISA and core IP from Imagination Technologies in mid-2018, announced the MIPS Open Initiative back in December last year. “Having spent years in the open source technology movement, I ...

BSC Opens the European Laboratory for Open Computer Architecture, LOCA

by Gareth Halfacree on FOSSi – AB Open
The Barcelona Supercomputer Centre (BSC) has announced the opening of the European Laboratory for Open Computer Architecture (LOCA), which aims to develop both energy-efficient and high-performance chips based on open instruction set architectures (ISAs). “LOCA will be a collaborative laboratory that welcomes companies, foundations and academic institutions that share the vision that it is necessary to create open architectures to guarantee transparency, competitiveness, and technological ...

El Correo Libre Issue 21

by Gareth Halfacree on LibreCores - Medium
teaser image ORConf 2019 Presentation Videos Now AvailableThose who were not able to attend ORConf 2019, or those who were but need a refresher on everything that happened, will be pleased to hear that videos for all 42 presentations at the event are now available on the FOSSi Foundation’s YouTube Channel. Presentations given at the event and captured for posterity include, but are most certainly not limited to, a look at open-source formal verification from Pepijn de Vos, an introduction to the ...

Observer Tacks RISC-V Cores to Sensors to Simplify Heterogeneous Aggregation

by Gareth Halfacree on FOSSi – AB Open
Olof Kindgren, director of the Free and Open Source Silicon Foundation (FOSSi Foundation), has released a tool designed to make multi-sensor aggregation on field-programmable gate arrays (FPGAs) simpler: the RISC-V-powered Observer. “Implementing the logic for sensor communication, post processing and format conversion directly in an FPGA can quickly become very time-consuming. This is a task much better suited for a CPU,” Kindgren explains of the project. “On an FPGA it’s no problem to add ...

Verilator - Verilator 4.022 Released

by Wilson Snyder on Veripool: News
Verilator 4.022 2019-11-10 Add --protect-lib, bug1490. [Todd Strader] Add cmake support, bug1363. [Patrick Stewart] Examples have been renamed. Add --protect-ids to obscure information in objects, bug1521. [Todd Strader] Add --trace-coverage. Add --xml-output. Support multithreading on Windows. [Patrick Stewart] Suppress 'command failed' on normal errors. Support some unpacked arrays in parameters, bug1315. [Marshal Qiao] Add interface port visibility in ...

The SiFive Tech Symposiums in Portland and Seattle are a Wrap

by Purvi Shenoy on SiFive
teaser image Our SiFive Tech Symposiums in Portland and Seattle were a big success, thanks in large part to our co-host, Mentor, a Siemens business; and our partner, Lauterbach, a leader in microprocessor development tools. Many leading OEMs were in attendance, such as Amazon, Facebook, Intel, Microsoft and Google There were presentations by the RISC-V Foundation, SiFive, Mentor and Lauterbach, as well as other ecosystem partners. We’d like to offer our thanks to the faculty and students at Portland ...

OTA: LimeNET Manufacturing Update, LimeSDR Mini External Reference Guide, and More

by Gareth Halfacree on MyriadRF
Manufacturing of the LimeNET Micro is underway, after initial volume production was delayed by selected components entering end-of-life (EOL) status. “A few of the parts we were planning to use went end-of-life just as we were in the process of setting up a volume production run,” explains Lime Micro’s Andrew Back of the delay. “The good news is that we’ve identified alternative parts and updated our design to accommodate them. “Doing so took us a little while, as we had to go through our ...

European Commission Publishes Final Open Source Beyond 2020 Agenda

by Gareth Halfacree on FOSSi – AB Open
The European Commission is to host the Open Source Beyond 2020 workshop on the future of open source hardware and software next week, featuring a panel on the advent of open source hardware and the Internet of Things chaired by the head of the Competitive Electronics Industry DG Connect A3 Unit Colette Maloney. “Open Source has become mainstream across all sectors of the software industry during the past 10 years,” the Commission writes of the event. “To a large extent, open software re-use ...

Announcing OpenTitan, the First Transparent Silicon Root of Trust

by lowRISC on lowRISC: Collaborative open silicon engineering
teaser image Today, we are excited to unveil the OpenTitan silicon root of trust (RoT) project, a new effort built using the successful collaborative engineering model created by lowRISC in partnership with Google and other commercial and academic partners. This effort sets a new bar for transparency in trusted silicon, and lowRISC is proud to serve as both steward and not-for-profit engineering contributor to OpenTitan, the world’s first open source silicon RoT. Silicon root of trust chips increase ...

lowRISC Collaborates with Industry Leaders to Create OpenTitan

by lowRISC on lowRISC: Collaborative open silicon engineering
Organisations aim to make the hardware root more transparent, trustworthy, and secure for everyone. CAMBRIDGE, England–(BUSINESS WIRE)–lowRISC C.I.C., the open source silicon and tools collaborative engineering company, today announced that it has partnered with ETH Zürich, Google, G+D Mobile Security, Nuvoton Technology and Western Digital in support of OpenTitan, an open source hardware root of trust (RoT) reference design and integration guidelines that enable chip producers and ...

Andy Hopper joins lowRISC CIC Board as Independent Chair

by lowRISC on lowRISC: Collaborative open silicon engineering
teaser image Today, we are delighted to announce that Professor Andy Hopper, CBE FRS FIET FREng, has joined the lowRISC Board of Directors as Independent Chair. “I’m delighted to be joining lowRISC CIC,” said Prof. Hopper, speaking today from Cambridge UK, “As digital systems pervade every aspect of our lives trust and transparency become crucial. An open source approach allows for public inspection of the principles and implementations being used. I believe the future of digital systems will be ...

RISC-V Hits the Browser Courtesy of Martin Strubel’s CI Docker Image

by Gareth Halfacree on FOSSi – AB Open
Martin Strubel has released a guide to running a RISC-V core directly in a browser – though admits that it’s unsurprisingly not quite as performant as if it were running in a native emulator or on dedicated hardware. “I though I’d share some open source approach to let a RISC-V spin in the cloud – a few 1000 times slower than reality, but still fast enough to run the ISA tests and – for fun – to talk to the SoC through a virtual UART,” Strubel writes in a post to the RISC-V hardware ...

CRU: Next-Gen Wishbone, FOSSi Events, and FOSSi Hits the Cloud

by Gareth Halfacree on FOSSi – AB Open
The maintainers of the Wishbone interconnect specification are calling for input on its future evolution, after converting the specification into an editor-friendly format for ease of participation. Offering eight, 16, 32, and 64 bit widths and originally created by the Silicore Corporation before being released under a permissive licence, the Wishbone bus is a popular choice for cross-core interconnections in free and open source silicon designs. Its maintainers, though, are looking to ...

OpenPiton+Ariane Reaches the Clouds via Amazon’s EC2 FPGAs

by Gareth Halfacree on FOSSi – AB Open
The free and open OpenPiton+Ariane heterogeneous research processor is now available on Amazon’s Elastic Compute Cloud (EC2) field-programmable gate arrays, providing an easy route to test it out without needing dedicated hardware. A partnership between the PULP Platform and the OpenPiton project released back in December last year, OpenPiton+Ariane combines the OpenSPARC and RISC-V cores to build what its creators call “the ideal permissive open-source RISC-V system that scales from ...

Bringing OpenPiton to Amazon EC2 F1 FPGAs

by Jonathan Balkind on OpenPiton Blog
teaser image OpenPiton release 13 (19-10-23-r13) is now available. The headline feature of this release is support for running OpenPiton+Ariane in the cloud via Amazon EC2 F1. Release 13 also offers other bug fixes and improvements that you can see on our GitHub repository. We now provide a step-by-step guide in the README of OpenPiton on GitHub which explains how to emulate OpenPiton+Ariane on Amazon EC2 F1 cloud FPGAs. You can make use of our existing release image to test software and firmware, or ...

OTA: Sending CSVs Over The Air, QRadioLink 0.8.2, In-Band Full-Duplex Breakthrough, and More

by Gareth Halfacree on MyriadRF
Salil Tembe has published a guide on using GNU Radio and a LimeSDR Mini to transmit a comma-separated value (CSV) text file over the airwaves. “We have seen the LimeSDR Mini several times on this blog,” Salil writes in the introduction to the piece. “So far, we have only seen how it can generate analogue modulation to transmit voice and what not. Being an SDR capable to transmit practically anything, we can even transmit binary data.” The project – which comes with downloadable GNU Radio ...

Incredibly Scalable High-Performance RISC-V Core IP

by James Prior on SiFive
teaser image Introducing the new SiFive U8-Series Core IP SiFive is pleased to introduce the SiFive U8-Series Core IP, an incredibly scalable high-performance microarchitecture for modern SoC designs. The SiFive U8-Series is the highest performance RISC-V ISA based Core IP available today, based on a superscalar out-of-order pipeline with configurable pipeline depth and issue queue width. SiFive U8-Series Core IP is designed for use in performance- and latency-sensitive markets, such as automotive, ...

SiFive Shield: An Open, Scalable Platform Architecture for Security

by James Prior on SiFive
teaser image Securing The RISC-V Revolution SiFive Shield is an open, scalable platform architecture designed to enable whole SoC security for RISC-V designs. The needs of modern SoC design dictate the need for a scalable solution for security, offering a low trusted computing base with clear root-of-trust and crucially, is auditable. Customization is also key, as a single offering fits all approach does not align to the needs of the next generation of domain specific processors now being ...

Introducing Greg & Tom

by lowRISC on lowRISC: Collaborative open silicon engineering
teaser image Greg Chadwick and Tom Roberts recently joined lowRISC’s growing engineering team. They’ve both taken some time to share a little about what they’re doing at lowRISC and what motivated them to join. Greg “It’s an exciting time to join the lowRISC team! Our Ibex core provides a solid foundation and clearly demonstrates the value of open source silicon, which I’m excited to be working on. My work so far has focused on the performance of Ibex; whilst it’s not ...

Wishbone Interconnect Maintainers Seek Input on Next-Generation Evolution

by Gareth Halfacree on FOSSi – AB Open
The maintainers of the Wishbone interconnect specification are calling for input on its future evolution, after converting the specification into an editor-friendly format for ease of participation. Offering eight, 16, 32, and 64 bit widths and originally created by the Silicore Corporation before being released under a permissive licence, the Wishbone bus is a popular choice for cross-core interconnections in free and open source silicon designs. Its maintainers, though, are looking to ...

FOSDEM 2020 RISC-V Devroom Opens Call for Participation

by Gareth Halfacree on FOSSi – AB Open
The organisers of the RISC-V Devroom at the FOSDEM 2020 conference, taking place in Brussels this coming February, have opened the call for talk proposals. “FOSDEM 2020 will take place on February 1-2, 2020 in Brussels, Belgium. There will be a half day RISC-V developer’s room on February 1st (Saturday),” writes Arun Thomas in a message to the RISC-V Foundation’s software mailing list. “The topic of the devroom encompasses the RISC-V ISA, open source RISC-V hardware (e.g. cores, SoCs, ...

CHIPS Alliance Growth Continues With New Members And Design Workshop This November | PR Newswire

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
SAN FRANCISCO, Oct. 15, 2019 /PRNewswire/ — CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced Codasip GmbH and Munich University of Applied Science have joined the CHIPS Alliance. In addition, on November 14–15, CHIPS Alliance will be joining the university for a workshop on open source design verification.CHIPS Alliance is a project hosted by the Linux Foundation to foster a collaborative environment to accelerate ...

The SiFive Tech Symposiums are Heading To Portland and Seattle This Month – See You There!

by Swamy Irrinki on SiFive
We’re confirming seats in Portland and Seattle for the Pacific Northwest leg of our worldwide 2019 SiFive Tech Symposiums. We are pleased to have Mentor, A Siemens Business as our co-host, and Lauterbach, a leader in microprocessor development tools, as our partner in both cities. The Portland symposium will take place Tuesday, October 22 at the Portland Community College. Our Seattle symposium will be on Wednesday, October 23 at thinkspace Seattle. All of the SiFive Tech Symposiums have ...

RISC-V Foundation Announces RISC-V Summit 2019 Agenda

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has announced the agenda for its second annual RISC-V summit, taking place this December in San Jose, California. “The RISC-V Foundation, in partnership with Informa’s Tech Division, is hosting its annual RISC-V Summit, a four-day conference featuring keynotes, smaller breakout sessions, tutorials, exhibitions and networking receptions, as well as member meetings to open the week’s events,” the Foundation explains. “Leading technology companies and research ...

NVDLA Deep Learning Inference Compiler is Now Open Source

by on SiFive
teaser image Designing new custom hardware accelerators for deep learning is clearly popular, but achieving state-of-the-art performance and efficiency with a new design is a complex and challenging problem. Two years ago, NVIDIA opened the source for the hardware design of the NVIDIA Deep Learning Accelerator (NVDLA) to help advance the adoption of efficient AI inferencing in custom hardware designs. The same NVDLA is shipped in the NVIDIA Jetson AGX Xavier Developer Kit, where it provides ...

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Last updated 18 January 2020 16:30 UTC