Planet LibreCores

RISC-V Gets an Early, Minimal Android 10 Port Courtesy of PLCT Lab

by Gareth Halfacree on FOSSi – AB Open
PLCT Lab, a group working on compilers, runtimes, and emulators, has announced a milestone for its effort to port the Android Open Source project to the free and open-source RISC-V instruction set architecture: a successful minimal boot, with step-by-step instructions for trying it out yourself. With increasing interest in using the RISC-V instruction set architecture for mobile-centric devices, a major hurdle is a lack of software support. It’s long been possible to boot mainstream Linux ...

A Comparison of Formal and Simulation for a Simple, Yet Non-Trivial Design - Part 1

by Tudor Timi on Verification Gentleman
teaser image I've talked a lot about constrained random verification on the blog, but now it's time to branch out to formal verification. As a fun first post on the topic, I thought we could do a comparative study. We can take a design and write two verification environments for it, one using formal verification and the other using simulation, based on UVM. Once we're done, it should be very interesting to be able to look at them side-by-side and to do an analysis.I thought long and hard about which one ...

Kactus2 website has moved

by Esko Pekkarinen on Kactus2: News
As part of the recent university merger, our previous website funbase.cs.tut.fi domain will be closed. The website have been moved to a new location at https://research.tuni.fi/system-on-chip/. The source code will continue to be hosted at https://github.com/kactus2/kactus2dev.

OTA: LimeSDR on the Traverse Ten64, LimeRFE Production Update, and More

by Gareth Halfacree on MyriadRF
Traverse Technologies has showcased the flexibility of its Ten64 eight-core Linux-based networking platform for wireless use, demonstrating its compatibility with the LimeSDR USB and GNU Radio. “There has been quite a bit of interest in using Ten64 for software-defined radio (SDR) applications,” the company explains, “so we have put together a simple demo using a LimeSDR to tune into an FM radio station and stream it to the internet.” Built as a Docker container, the project uses GNU Radio ...

SiFive Strengthens Foothold in Storage Applications for Data-Centric AI Computing

by James Prior on SiFive
teaser image SiFive RISC-V processors are powering flash drives in production as well as addressing emerging In-Storage Computing (ISC) needs In the current digital age, where data powers increasing levels of decision making, industrial control and automation, efficient data storage, movement, and processing become the focal point of technological innovations in silicon, system, and software. At SiFive, we have been designing and optimizing RISC-V based domain-specific solutions to address the ...

BBC Picks SiFive’s RISC-V-Powered HiFive Inventor for Doctor Who Coding Push

by Gareth Halfacree on FOSSi – AB Open
The BBC has announced a partnership with SiFive to bring RISC-V-powered development to kids around the world with the launch of the BBC Doctor Who HiFive Inventor educational development board and supporting coursework bundle. Announced late last year, the SiFive Learn Inventor is a hand-shaped educational development board inspired by the popular BBC micro:bit but powered by SiFive’s Freedom E310 processor – itself driven by the free and open-source RISC-V instruction set architecture ...

El Correo Libre Issue 33

by Gareth Halfacree on LibreCores - Medium
teaser image Matt Guthaus Showcases OpenRAM on SkyWater’s 130nm Process in FOSSi Dial-UpProfessor Matt Guthaus has offered an overview of OpenRAM, an open-source Python framework designed to handle the integration of static RAM (SRAM) into application-specific integrated circuit (ASIC) design, as part of the ongoing FOSSi Dial-Up video series. “I’ve been working on OpenRAM for actually quite a few years now,” Matt explained by way of introduction in the live video presentation, “and it’s turning into a ...

Fixing the ESD generator

by Fatsie on Chips4Makers.io
teaser image This is a continuation on my previous blog on first tests on the ESD generator. Problems After some more debugging the voltage multiplier of the ESD Generator has been made to work. Detailed simulation results of the problems can be found in this Jupyter notebook in the created sim folder in the ESD Generator source folder. Summary of the problems: Leakage problem reported on in the previous blog post is mainly caused by the 10MΩ input impedance on the oscilloscope input not the diode ...

OTA: New srsLTE, Lime Suite, LuaRadio, GQRX, SDR#, and More

by Gareth Halfacree on MyriadRF
The open-source srsLTE cellular communications suite has hit version 20.10, bringing new functionality including mobility functions and performance-enhancing PHY changes – and a range of bug-fixes, too. The srsLTE 20.10 release brings with it a new logging framework alongside initial NR PHY layer and stack components. The srsENB package receives Mobility – Intra eNB and S1 – functionality and RRC Re-establishment functionality, too, while the UE PHY layer is non-blocking and PHY ...

The Heart of RISC-V Development is Unmatched

by James Prior on SiFive
teaser image Creating a RISC-V PC Ecosystem for Linux application development Today, SiFive introduces the new HiFive platform for professional RISC-V developers, the HiFive Unmatched! The HiFive Unmatched enables developers to create the RISC-V-based software they need for RISC-V platforms. From real-time operating systems to custom Linux distributions, and the compilers, libraries, and applications that go with product design, developers can use the HiFive Unmatched to natively test and build RISC-V ...

SiFive VIU75 Accelerates Vector Math

by Abhishek Jadhav on FOSSi – AB Open
teaser image At the Linley Fall Conference 2020, SiFive Chief Architect and co-founder Krste Asanovic announced the RISC-V based VIU7 series. In that, the VIU75 CPU core is 64-bit, runs Linux, and supports “RV vector extension”. When it comes to RISC-V based core IP, SiFive has always dominated with new CPU IP with a huge portfolio. The RISC-V core VIU75 comes from the VI7 series and U cores. The VI7 series has a high-performance, 8-stage dual-issue in-order pipeline with an integrated vector unit, ...

A birthday present for lowRISC: We won an OpenUK Award!

by lowRISC on lowRISC: Collaborative open silicon engineering
teaser image On October 20th, lowRISC CIC won in the Open Hardware category at the 2020 OpenUK Awards, describing lowRISC as “the jewel in the crown of the UK’s open silicon companies”. The OpenUK awards promote “UK Leadership in Open Technology”, and are given out by OpenUK, a UK-based not-for-profit company which supports open source collaboration and open technologies within the United Kingdom. On receiving the award, lowRISC CTO, Alex Bradbury, said “We’re incredibly grateful to have been ...

The SiFive 20G1 Update for 7-Series Core IP

by Drew Barbier on SiFive
Faster, More Efficient SiFive 7-Series Core IP Today, we’re announcing the SiFive 20G1 6.0 update, which is focused on improving the 7-Series line of products. Our previous release, SiFive 20G1, was a comprehensive update that spanned from the 7-Series to the 2-Series, including U-, S-, and E-Cores. Similarly, the 20G1 6.0 update improves the performance, features, and functionality of SiFive 7-Series U-, S-, and E-Cores. Ever since the 7-Series introduction in 2018, SiFive has been able to ...

El Correo Libre Issue 32

by Gareth Halfacree on LibreCores - Medium
teaser image Antmicro Integrates Embench for Quick Core-to-Core Performance ComparisonsFree and open source silicon pioneer Antmicro has published a series of benchmark results designed to pit a selection of cores head-to-head in real-world workloads, using the Embench benchmark suite maintained by the FOSSi Foundation. “Embench, maintained by the FOSSi Foundation we proudly participate in, is an open source embedded benchmark test suite which aims to respond to the needs of modern embedded systems,” ...

How we used differential testing to rapidly find and fix missed optimisation opportunities in LLVM's RISC-V backend

by Luís Marques on lowRISC: Collaborative open silicon engineering
At this October 2020 LLVM Developers’ Meeting I presented a poster about how, with a surprisingly simple tool, we were able to rapidly identify, isolate, and fix a range of missed optimisation opportunities in LLVM’s RISC-V backend. The tool works by generating random C programs, compiling each program with both Clang and GCC (targeting RISC-V) and comparing the assembly generated by both compilers. If it estimates that Clang/LLVM generated worse code than GCC then it saves that case ...

First testing of and changes to ESD generator

by Fatsie on Chips4Makers.io
teaser image As reported in a previous blog post I am working on a small circuit to generate high voltages for some ESD testing. I now received the PCBs and the components for on the PCB and even did find some time to do the first testing of the design. As a reminder this is the schematic of the ESD generator: To do the first testing I just populated the transformator, the diode bridge and components C1, C13, D5 and D17. This can be seen in the next picture: It should allow to test if a voltage of ...

SHAKTI Announces Third Silicon Success with the Arduino-Compatible Moushik

by Gareth Halfacree on FOSSi – AB Open
The SHAKTI free and open source silicon project has reached another milestone with the boot up of the Moushik, an Arduino-compatible system-on-chip (SoC) and the group’s third successful silicon tape-out. The SHAKTI project first announced its success in booting Linux on a home-grown RISC-V based processor back in 2018, initially on a chip built by US semiconductor giant Intel on a 22nm process, then on a chip built natively in India on a 180nm node at the ISRO Semiconductor Laboratory in ...

OTA: High School RADAR, GSM Base Station on DragonOS, FM on the ISS, and More

by Gareth Halfacree on MyriadRF
Parkland High School student Victor Cai has presented work on a proof-of-concept short-range RADAR system, built around a LimeSDR Mini, at the GNU Radio Conference 2020 (GRCon20). Victor’s experimental system, presented with supporting paper during the virtual GRCon20 event, combines an off-the-shelf laptop running GNU Radio with a LimeSDR Mini software defined radio, a mixture of commercial and home-made antennas, and a simple experimental setup to prove that often-dismissed ...

The Incredible Opportunity For SiFive

by Patrick Little on SiFive
A note from SiFive President & CEO, Patrick Little I’m honored to join SiFive to lead the brilliant, hard-working team of innovators and engineers who are responsible for creating some of the most impactful architectures in the technology industry. Ten years ago, an inspired team of computer scientists set out to invent a better way for hardware and software to talk to each other, free of legacy overhead and unencumbered by complexity, bringing the RISC-V Instruction Set Architecture to ...

IBM Contributes Open-Source A2O POWER Core, Open-CE to the OpenPOWER Foundation

by Gareth Halfacree on FOSSi – AB Open
The OpenPOWER Foundation has announced two more IBM projects which have been moved to an open-source licence, following on the heels of opening the POWER instruction set architecture (ISA) itself. Announced this week at the OpenPOWER Summit 2020, IBM is contributing a the A2O out-of-order processor core with supporting FPGA environment and a deep-learning-focused project it calls the Open Cognitive Environment (Open-CE), aiming to improve accessibility of existing frameworks. “I’m excited ...

SiFive Announces FU740-Based RISC-V PC, Plans to Grow the RISC-V Ecosystem

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneer SiFive has announced its intention to encourage growth of the RISC-V developer ecosystem with the release of a ready-to-run off-the-shelf RISC-V-powered personal computer built on its FU740 processor – offering a turnkey alternative to the current raft of do-it-yourself options. The free and open-source RISC-V instruction set architecture (ISA) and the ecosystem which surrounds it is gathering momentum on a daily basis. From hobbyists and academics experimenting through to ...

Reverse-engineering the first FPGA chip, the XC2064

by DP on FPGA – Dangerous Prototypes
teaser image Ken has written an article on reverse engineering the first FPGA chip, the XC2064: The FPGA was invented by Ross Freeman1 who co-founded Xilinx2 in 1984 and introduced the first FPGA, the XC2064. 3 This FPGA is much simpler than modern FPGAs—it contains just 64 logic blocks, compared to thousands or millions in modern FPGAs—but it led to the current multi-billion-dollar FPGA industry. Because of its importance, the XC2064 is in the Chip Hall of Fame. I reverse-engineered Xilinx’s ...

GSoC Projects Successfully Completed

by Pirmin Vogel, Sam Elliott, and Greg Chadwick on lowRISC: Collaborative open silicon engineering
Time is ticking and summer is almost over already. With that, also our this years’ Google Summer of Code (GSoC) projects are coming to an end. A lot of open-source coding has been done, pull requests have been made, reviewed and merged. Experiments have been conducted, results were gathered, interpreted and presented. Bugs were found and fixed, and the resulting designs further improved. Both our students and mentors have been working hard and we are pleased to announce that both our two ...

El Correo Libre Issue 31

by Gareth Halfacree on LibreCores - Medium
teaser image FOSSi Dial-Up is a BlockbusterFOSSi Dial-Up has been running for three episodes now and it was a great joy and success. In this edition of ECL I want to quickly recap what has happened so far and where you can binge the previous three episode.In our kick-off Tim Ansell as the project lead of the Skywater open source PDK gave an overview of the project. The PDK is a major missing link in an open source silicon design flow, and this project is a thrilling milestone. If that was not enough for ...

RISC-V Vector Extension Intrinsic Support

by Chris Lattner on SiFive
The RISC-V Vector extension (RVV) enables processor cores based on the RISC-V instruction set architecture to process data arrays, alongside traditional scalar operations to accelerate the computation of single instruction streams on large data sets. The RISC-V International vector working group is composed of experts from industry and academia, to create a standard extension that can be ratified for general adoption among any who choose to adopt RVV. We’re incredibly pleased to announce ...

Randomness is Secure with SiFive Shield HCA

by James Prior on SiFive
Building a secure foundation using the concept of randomness seems, on the surface, counter-intuitive. As an aspect of entropy, randomness enables the generation of cryptographic methods to protect data, chips, and systems. By harnessing the nature of randomness as the basis of a secure system, it is possible to enhance the security of computer systems and protect vital information. In July, SiFive introduced the SiFive Shield hardware cryptographic accelerator (HCA), as part of the ...

Lattice Semiconductor Embraces Open Hardware, Launches “Community Sourced” Portal

by Gareth Halfacree on FOSSi – AB Open
Field-programmable gate array (FPGA) expert Lattice Semiconductor has embraced the ethos of the open hardware community, creating a portal which lists what the company describes as “community sourced” open hardware development boards and reference designs. “In addition to proprietary boards developed by Lattice and other partners there is a broad array of boards developed by the open source community,” Lattice notes on its freshly-launched portal. “In some cases just the designs are ...

OTA: New Lime Suite Release, 16km Barefoot TV Transmissions, and More

by Gareth Halfacree on MyriadRF
Lime Suite v20.07.1 has officially launched, bringing a range of improvements to the LimeSDR-focused software bundle – including a fix for a bug which was causing quick tests of LimeSDR Mini boards to fail. In its latest release, Lime Suite v20.07.1 repairs a recently-discovered bug which would manifest as intermittent failures when running the LimeQuickTest utility on LimeSDR Mini boards. While these failures would appear to suggest that the boards were themselves faulty, the cause was ...

OpenFive's Customizable Silicon-Focused Solutions

by Shafy Eltoukhy on SiFive
teaser image OpenFive is a solution-centric and processor agnostic custom silicon business unit dedicated to building optimized domain-specific SoCs Today, I am excited to announce the launch of OpenFive, a self-contained and autonomous custom silicon business unit of SiFive, Inc. OpenFive is solution-centric and uniquely positioned to design processor agnostic SoCs and deliver high-quality silicon. The demand for domain-specific silicon and workload-focused architecture is driven by several key ...

El Correo Libre Issue 30

by Gareth Halfacree on LibreCores - Medium
teaser image Brian Bailey: Open Source Verification “Leaves the Door Open to New Approaches”Brian Bailey, technology editor for electronic design automation (EDA) at Semiconductor Engineering, has penned a piece looking into exactly what is meant by “open-source verification” — and how it can leave the door open to novel approaches not previously considered by the industry. “Ask different people what open-source verification means and you will get a host of different answers,” Brian explains. “They ...

DIN SPEC 3105, Published Under an Open Licence, “Writes a New Chapter” for Open Hardware

by Gareth Halfacree on FOSSi – AB Open
The German Institute for Standardisation (Deutsches Institut für Normung, DIN) has published a formal specification, DIN SPEC 3105, for open source hardware documentation – and the specification itself is open, and the first to be published under a Creative Commons licence. Released as part of a pilot program which sees DIN working alongside open-source and open-hardware communities, DIN SPEC 3105 details requirements for technical documentation in open-source hardware projects. “The pilot ...

Lime Suite 20.07.1 Released

by Andrew Back on MyriadRF
A new release of the Lime Suite software, which provides drivers, utilities and APIs for the LimeSDR family of boards, has been made. The v20.07.1 release includes a number of improvements to the Lime Suite library, with perhaps the most notable being a configuration change for LimeSDR Mini boards, which addresses issues including intermittent failures when running LimeQuickTest. As such all LimeSDR Mini owners are strongly urged to upgrade. Other improvements include various fixes to the ...

EDeA Project Aims to Make Sharing, Using KiCad “Subcircuits” as Easy as Possible

by Gareth Halfacree on FOSSi – AB Open
KiCad users may soon be able to easily share, download, and assemble subcircuits into open-hardware projects thanks to a new initiative dubbed EdeA. “There is a growing Open Hardware movement, a diverse bunch of people with intimidating skill levels, and they are reimplementing the wheel over and over,” explains pseudonymous co-founder ln of the project. “What if it were easy to share those tricks, to reuse what we already made, tested, so we can build better, cheaper, or achieve more? What ...

OTA: Hijacking Hostile Drones, LiFi Dev Kits, Custom LimeSDR Chassis and More

by Gareth Halfacree on MyriadRF
Vilnius Gediminas Technical University student Ugnius Buržinskis has released a video demonstrating a drone hijacking system, designed to prevent unauthorised uncrewed aerial vehicles (UAVs) from entering a restricted area, powered by a LimeSDR Mini. Using the LimeSDR Mini, housed in a protective casing and connected to an off-the-shelf laptop running software based on the SoapySDR application programming interface (API), the system is designed to wrest control of an unauthorised drone ...

SiFive Core IP 20G1

by Drew Barbier on SiFive
teaser image SiFive's Best Processor Portfolio Is Here We’re pleased to announce a comprehensive update to SiFive’s RISC-V IP Portfolio with the SiFive 20G1 release. This release brings important enhancements and new capabilities to SiFive Core IP, the industry's broadest RISC-V IP Portfolio, ranging from the ultra-capable SiFive U7-Series to the extremely popular SiFive E2-Series, offering up to 2.8x more performance(1); up to 25% lower power(2); and up to 11% smaller area(3). For a deep dive into the ...

RISC-V International & Members at the 57th Annual Design Automation Conference!

by Jeffrey Osier-Mixon on Events – RISC-V International
teaser image     Members of RISC-V International will be delivering numerous presentations and hosting discussions and tutorials at the annual Design Automation Conference (DAC) 2020, taking place from Monday, July 20 through Friday, July 24, showcasing RISC-V’s incredible momentum since its inception ten years ago at the University of California, Berkeley. The presentations, discussions and tutorials will focus on new and exciting developments and implementations from the RISC-V community, spotlighting ...

Fix in Lime Suite for LimeSDR Mini loopback test failure

by Andrew Back on MyriadRF
We had a number of reports of LimeSDR Mini boards intermittently failing loopback tests that are run by the LimeQuickTest utility. Upon investigation, it turned out that the VCO bias current for LimeSDR Mini was being set lower than it was for other boards, which was resulting in this error and possibly other issues. This has now been fixed in Lime Suite and for the time being it is recommended to build from source using the master branch. A new release is planned for the end of July and at ...

Microchip Opens Orders for RISC-V-Powered, Linux-Capable PolarFire SoC Icicle Board

by Gareth Halfacree on FOSSi – AB Open
Microchip has opened orders for its PolarFire SoC Icicle development board, offering end-users the first access to its combined RISC-V and field-programmable gate array (FPGA) system-on-chip – and the ability to build a Linux-capable RISC-V system. Announced late last year, the PolarFire SoC combines Microchip’s PolarFire family of low-power FPGAs with a coherent CPU cluster comprised of four high-performance 64-bit RISC-V cores and a fifth low-power monitor core. Together, it’s possible to ...

El Correo Libre, Issue 29

by Gareth Halfacree on LibreCores - Medium
teaser image Cocotb Version 1.4.0 Brings Major ImprovementsCocotb, a community project held under the umbrella of the FOSSi Foundation, is proud to announce the release of its new version 1.4.0. Cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python.This release concludes a six month development period, similar to its predecessors in recent history. A major focus of this release was stability and ease of use.Writing testbench code is now more intuitive ...

ESD Generator: high voltage generator for ESD testing

by Fatsie on Chips4Makers.io
teaser image After tape-out of NLNet018TV I am now working on implementing the test procedures and gathering the equipment needed for executing the tests. For ESD testing high voltages with limited charges need to be generated. This high voltage charge is then applied over two pins on the test chip to see if the chip survives the event. This event mimics what happens when a charged person touches a chip. Standards exist for performing ESD tests together with expensive equipment that allows to perform ...

QuickLogic Launches QuickFeather Fully-Open FPGA Dev Board Crowdfunder

by Gareth Halfacree on FOSSi – AB Open
QuickLogic has officially launched the a crowdfunding campaign for the QuickFeather, a Feather-compatible fully-open microcontroller and field-programmable gate array (FPGA) development board – and AB Open is proud to be its first backer. The QuickFeather – named for its use of the Feather form factor, a gumstick variant designed for breadboard compatibility – is built around QuickLogic’s in-house EOS S3 system-on-chip. Created with low-power embedded work in mind, the EOS S3 includes an ...

Cocotb releases version 1.4.0 with major improvements

by FOSSi Foundation on FOSSi Foundation - News & Posts
The cocotb project is proud to announce the release of its new version 1.4.0. cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. Cocotb can be installed and updated from PyPi through pip: pip install --upgrade cocotb For full installation instructions refer to the documentation at https://docs.cocotb.org/en/v1.4.0/install.html. This release concluces a six month development period, similar to its predecessors in recent history. A ...

OpenPOWER Releases BlueGene/Q’s A2I POWER Core As Free and Open Source Silicon

by Gareth Halfacree on FOSSi – AB Open
The OpenPOWER Foundation has announced the release of another core design, A2I POWER, under permissive licensing – part of the Foundation’s move to offer an alternative to increasingly popular free and open source silicon efforts like RISC-V. The OpenPOWER Foundation moved to a permissive, open release approach back in August last year with the promise of opening the POWER ISA, OpenCAPI, and the Open Memory Interface (OMI). Since then, it has delivered on its promises – and is now adding ...

Produce your own physical chips. For free. In the Open.

by FOSSi Foundation on FOSSi Foundation - News & Posts
Did you ever dream about creating your own chip? I mean, a physical chip. One which you can hold in your hand, and which does exactly what you’ve designed it to do? Until today, there were two major road blocks: you had to get access to a process design kit (PDK) from a chip manufacturing house (a foundry), and you had to have enough money to actually pay for the manufacturing. These times are over. Today. Today, in a FOSSi Dial-Up talk, Tim Ansell of Google announced SkyWater PDK, the ...

Arrays, Dynamic Arrays, Queues: One List to Rule them All

by Matthew Ballance on Bits, Bytes, and Gates
Randomizable lists are, of course, very important in modeling more-complex stimulus, and I've been working to support these within PyVSC recently. Thus far, PyVSC has attempted to stay as close as possible to both the feature set and, to the extent possible, the look and feel of SystemVerilog features for modeling constraints and coverage.  With randomizable lists, unlike other features, I've

El Correo Libre Issue 28

by Philipp Wagner on LibreCores - Medium
teaser image This edition of El Correo Libre will be a bit shorter as our editor, Gareth Halfacree, is on well-deserved holiday. However, there are important announcements that you should be the first to learn about!This month we are starting our new online event series FOSSi Dial-Up. It will be a monthly event featuring distinctive speakers from the FOSSi Community. In an hour-long session you can learn about impressive projects every month, followed by a Q&A session.The premiere FOSSi Dial-Up will ...

FOSSi Foundation Takes Over Solderpad Hardware License Stewardship

by FOSSi Foundation on FOSSi Foundation - News & Posts
HALIFAX, England, 18th June 2020 - The Free and Open Source Silicon Foundation (FOSSi Foundation) is proud to announce that it has taken over stewardship of the Solderpad Hardware License (SHL), a popular permissive license for open hardware projects that was originally drafted by Andrew Katz, open source legal expert and partner at Moorcrofts LLP. Designed to extend the benefits of the Apache 2.0 open source software license to open hardware projects — including but not limited to free ...

FOSSi Dial-Up Launches with Big Bang: Production-ready Open Source PDK

by FOSSi Foundation on FOSSi Foundation - News & Posts
FOSSi Foundation launches a new event series named FOSSi Dial-up. It consists of monthly online events that features distinctive speakers from the FOSSi community. By dedicating one hour of presentation plus time for questions, it is set up to become the premier event for major announcements and focused in-depth technical content from all areas of the community. The series starts with a walk through the new project between Google and SkyWater Technology Foundry to provide a fully open ...

NLNet018TV: a fully automated test chip design

by Fatsie on Chips4Makers.io
I am working on a NGI0 NLNet funded project and I now did reach a first milestone in the project. I did tape-out a test chip which kept me busy for the last two months and is also the reason I neglected this blog the last months. The milestone is a step to the tape-out of a prototype of the libre-SOC project in the fourth quarter of this year. Description and source code In good open source fashion I did put all the source code in the NLNet018 TV tag on my SnowWhite git repository in the ...

RISC-V Global Forum

by Jeffrey Osier-Mixon on Events – RISC-V International
RISC-V is breaking down technical barriers and disrupting traditional microprocessor business models through global collaboration. The RISC-V Global Forum is our opportunity to engage across the community, from start-ups to multi-nationals, from students to luminaries, from deep technical talks to understanding industry momentum. Join us as a sponsor to showcase success and opportunity, as a speaker to share progress and perspective, and as an attendee to hear from industry thought leaders, ...

CRU: Ten Years of OSHUG, OpenHW Group Membership, RISC-V Trace, and More

by Gareth Halfacree on FOSSi – AB Open
Last month marks the tenth anniversary of the inaugural meeting of the Open Source Hardware User Group (OSHUG). AB Open’s Andrew Back recalls the founding of OSHUG: “The nascent open hardware movement had started to gather momentum and in December 2009, Nesta, the UK based charity and innovation foundation, hosted a one day event dedicated to the topic. This served as a pivotal moment for many of those of us who attended and one outcome of this being the formation of the Open Source ...

Andes Sponsors Webinar in Japan

by Jeffrey Osier-Mixon on Events – RISC-V International
Information: https://twitter.com/Andes_Tech/status/1265121233399504896 Register here: https://register.gotowebinar.com/register/3084145915944525582 The post Andes Sponsors Webinar in Japan appeared first on RISC-V International.

Andes Sponsors Webinar in Japan

by Jeffrey Osier-Mixon on Events – RISC-V International
Information: https://twitter.com/Andes_Tech/status/1265121233399504896Register here: https://register.gotowebinar.com/register/3084145915944525582 The post Andes Sponsors Webinar in Japan appeared first on RISC-V International.

AB Open Joins OpenHW Group to Help Grow The Open Hardware Ecosystem

by Gareth Halfacree on FOSSi – AB Open
AB Open is proud to announce its membership of OpenHW Group, a not-for-profit organisation founded to provide an infrastructure for open hardware development with a focus on free and open source silicon, tools, and related software. Founded in June 2019, OpenHW Group aims to encourage adoption of free and open source silicon technologies — including, but not limited to, core intellectual property (IP) provided under permissive licensing — by acting as a focal point for ecosystem ...

OTA: Kimera Video Transmission, GNU Radio for Android, QO-100 QSO, and More

by Gareth Halfacree on MyriadRF
Community member Luigi Cruz has published a tool which is capable of encoding any video source, complete with hardware acceleration, and transmitting it over the airwaves using a LimeSDR. “Kimera can capture any camera connected to your computer, hardware encode it with any codec available (e.g. HEVC, AVC, AV1), and transmit over TCP, UNIX Socket, or this GNU Radio Transport Layer,” Luigi writes of his latest software release. “On the receiver, it will decode and emulate a native ...

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Last updated 03 December 2020 19:00 UTC