Planet LibreCores

Retro-µC 2021 Test Tape-out

by Fatsie on Chips4Makers.io 27 November 2021 23:00 UTC

I found some time to work on the Retro micro-controller again and perform a test tape-out in TSMC 0.35um technology. I was also contacted by Matt Venn for an interview. We agreed to also discuss this tape-out during the interview. This relieved me from the (in my eyes) boring task of writing an extensive blog post on it. The interview is published on Matt Venn's Zero To ASIC Course YouTube channel. Just wanted to do a little additional expectation management. Due to the current chip squeeze ...

OTA: Delivery Updates, LimeSDR on a Phone, a New CubeSat, LoRa Moonbounce and More

by Gareth Halfacree on MyriadRF 26 November 2021 06:27 UTC

Lime Micro products, including the LimeSDR family, are still being impacted by global component shortages and supply chain disruption – but Lime’s Ebrahim Bushehri has detailed how the company is working to overcome the issues. “While we’ve placed our orders and hope the supply chain settles down soon, we’re not betting on it and are actively pursuing other avenues to resuming production,” Ebrahim explains. “For example, there is some hope of synthesizing a PLL in an FPGA and sourcing FPGAs ...

See Western Digital’s SweRV Core family at the 2021 RISC-V Summit

by Ted Marena on Blog – RISC-V International 18 November 2021 20:08 UTC

RISC-V has been a very popular choice for embedded processor designs. Western Digital’s existing SweRV Core family is among the highest performance, area optimized embedded RISC-V Cores available today. The openness of RISC-V enabled the SweRV Core EH2 to offer dual threaded capability. It was the first commercial RISC-V core and it has notched an impressive CoreMarks/Mhz score of 7.8 in dual threaded mode. At the RISC-V Summit on Dec 8, 2021 at 11am Zvonimir Bandic will unveil the new ...

Goodbye Blogger, Hello Static Site

by Tudor Timi on Verification Gentleman 14 November 2021 17:32 UTC

Announcement The Verification Gentleman Blog will be moving from Blogger.Why?While Blogger was a great platform to start on, especially considering the fact that it's 100% free, I feel that I've outgrown it.The interface is very arcane and it's very difficult to do any kind of customization. For example, setting up syntax highlighting required fiddling with a lot of things to get it working and even then the results aren't all that great. It's very easy to mess up the entire blog and not be ...

A Comparison of Formal and Simulation for a Simple, Yet Non-Trivial Design - Part 1

by Tudor Timi on Verification Gentleman 24 November 2020 23:11 UTC

I've talked a lot about constrained random verification on the blog, but now it's time to branch out to formal verification. As a fun first post on the topic, I thought we could do a comparative study. We can take a design and write two verification environments for it, one using formal verification and the other using simulation, based on UVM. Once we're done, it should be very interesting to be able to look at them side-by-side and to do an analysis.I thought long and hard about which one ...

Favor Composition Over Inheritance - Even for Constraints

by Tudor Timi on Verification Gentleman 29 March 2020 15:02 UTC

Simulation is currently the dominant functional verification technique, with constrained random verification the most widely used methodology. While producing random data is a big part of it, letting the solver blindly generate stimulus isn't going to be very efficient. Constraints are needed to guide the stimulus toward interesting scenarios.A good constrained random test suite contains a mixture of tests with varying degrees of randomness. This is achieved by progressively adding ...

Bigger Is Not Always Better: Builds Are Faster with Smaller Packages

by Tudor Timi on Verification Gentleman 09 February 2020 18:44 UTC

One trend over the past few years is that the projects I've been working on tend to get bigger and more complicated. Bigger projects come with new challenges. Among these are the fact that it's much more difficult to keep the entire project in one's head, the need to synchronize with more developers because team sizes grow, a higher risk of having to re-write code because of poorly understood requirements or because some requirements change, and many more.There's one thing, though, that ...

Testing SVA Properties and Sequences

by Tudor Timi on Verification Gentleman 25 June 2017 21:25 UTC

After a pretty long absence, it’s finally time to complete the series on unit testing interface UVCs. I meant to write this post in October/November 2016. While writing the code, I got bogged down by a simulator bug and tried to find an elegant work around, but failed. I got frustrated and shelved the work for a while. In the meantime I got caught up with technical reading and with taking online courses. I’ve also been pretty busy at work, putting in quite a bit of overtime, which left ...

Testing UVM Drivers, Part 2

by Tudor Timi on Verification Gentleman 15 August 2016 14:30 UTC

In the previous post we looked at how we can emulate sequencer/driver communication using a lightweight stub of uvm_sequencer. Let's also look at some more tips and tricks I've picked up while writing unit tests for drivers. To mix things up a bit, let's look at the AXI protocol. We're not going to implement a full featured driver; instead, we'll focus on the write channels: interface vgm_axi_interface(input bit ACLK, input bit ARESETn); logic [3:0] AWID; logic [31:0] AWADDR; logic [3:0] ...

Testing UVM Drivers

by Tudor Timi on Verification Gentleman 07 August 2016 16:06 UTC

It's that time again when I've started a new project at work. Since we're going to be using some new proprietary interfaces in this chip, this calls for some new UVCs. I wouldn't even consider developing a new UVC without setting up a unit testing environment for it first. Since this is a greenfield project, a lot of the specifications are volatile, meaning that the interface protocol can change at any moment. Having tests in place can help make sure that I don't miss anything. Even if the ...

A Quick Look at SVAUnit

by Tudor Timi on Verification Gentleman 24 July 2016 15:05 UTC

I've been writing more and more SystemVerilog assertions (SVAs) lately. I find that they are the best way to capture temporal requirements, allowing the rest of the (class-based) testbench to stay timing agnostic. Since assertions are a key part of the checking infrastructure we need to make sure that they're bulletproof. This means that we need to test them to make sure that they're doing what we expect them to do.The typical flow when writing an assertion is the following (for me, at ...

The Humble Beginnings of a SystemVerilog Reflection API, Part 3

by Tudor Timi on Verification Gentleman 01 June 2016 20:59 UTC

We've already looked at how to interrogate classes about what variables they have and how to set and get the values of these variables in different instances. Classes are much more than just data containers, though. They also contain methods that can operate on their variables. In this post we'll look at how we can handle tasks and functions inside our reflection API. Before we start, however, let's take a quick look at the two kinds of methods we can declare in SystemVerilog: tasks and ...

The Humble Beginnings of a SystemVerilog Reflection API, Part 2

by Tudor Timi on Verification Gentleman 20 May 2016 20:03 UTC

In the previous post we saw that it's possible to use the Verilog Programming Interface (VPI) to programmatically get information about classes. For example, we can "ask" a class what variables it has. We've wrapped the calls to the C interface in a nice SystemVerilog library by using the Direct Programming Interface (DPI). While being able to mine the code for information about its structure can prove very useful, what this gives use is merely introspection. True reflection requires that ...

The Humble Beginnings of a SystemVerilog Reflection API

by Tudor Timi on Verification Gentleman 10 April 2016 16:34 UTC

Reflection is a mechanism that allows "inspection of classes, interfaces, fields and methods at runtime without knowing the names of the interfaces, fields, methods at compile time. It also allows instantiation of new objects and invocation of methods". In e, using reflection together with define as compute macros allows us to do some really cool stuff. A major complaint about SystemVerilog is that it lacks reflection capabilities. These could be useful for writing super generic code,but ...

An Overview of UVM End-of-Test Mechanisms

by Tudor Timi on Verification Gentleman 25 March 2016 20:35 UTC

A lot traffic coming from Google to the blog is from searches about setting the UVM drain time. That's because one of my first posts was about how to set the drain time prior to going into the run phase. At the time of writing, this was the third most viewed post. End-of-test handling in UVM seems to be a topic a lot of people are interested in. In this post we’re going to look at different ways of implementing it. End-of-test relies on objections. Each component can raise objections during ...

Registering Abstract Classes with the UVM Factory

by Tudor Timi on Verification Gentleman 14 February 2016 17:18 UTC

Every now and again I stumble upon a situation where it's natural to use an abstract class. A typical example is when working with parameterized classes and wanting to swap parameterizations: virtual class some_abstract_component extends uvm_component; pure virtual function void do_stuff(); virtual task run_phase(uvm_phase phase); do_stuff(); endtaskendclassclass some_concrete_param_component #(type T = int) extends some_abstract_component; virtual function void do_stuff(); ...

Fun and Games with CRV: Einstein's Puzzle (Revisited)

by Tudor Timi on Verification Gentleman 09 December 2015 21:02 UTC

Two weeks ago, Aurelian from AMIQ published a post on how to solve the so-called Einstein's puzzle using e. At the end, he challenged us readers to try and improve on his solution. Not being one to shy away, I rolled up my sleeves and got to work.He started out by defining a struct to hold the information about a resident:<'struct resident { nationality : nationality_t; house_color : house_color_t; cigarette : cigarette_t; pet : pet_t; drink : drink_t;};'>He gave up on this idea after ...

Packages, Class Names and UVM

by Tudor Timi on Verification Gentleman 06 December 2015 18:17 UTC

Some time ago I wrote a post that challenged some of the established coding conventions of modern SystemVerilog. In particular, I expressed my displeasure with the fact that all training material from EDA companies, tutorial sites and other learning resources state that packages should always contain a "_pkg" suffix appended to the package name and that all identifiers in the package (class/function/constant names) should contain the package name as a prefix. I attribute this to the ...

Accessing Multiple Registers at Once

by Tudor Timi on Verification Gentleman 22 November 2015 23:32 UTC

As I already mentioned, I gave a talk at DVCon Europe this year on how to implement burst accesses to memories modeled using UVM_REG. The motivation for that was that the register package can already handle bus protocols that don't support burst operation, but it requires more user guidance for protocols that do support it. A question that came up afterwards on the conference floor was what the best way to handle burst accesses to multiple registers might be. I tried to sketch out an answer ...

El Correo Libre Issue 44

by Gareth Halfacree on LibreCores - Medium 09 November 2021 09:36 UTC

Cocotb 1.6.0 Provides Better HDL Datatypes, Improved Coroutine Scheduling, and MoreThe cocotb project — the COroutine based COsimulation TestBench — has announced the release of v1.6.0, which adds a range of improvements to the popular Python-based VHDL/Verilog RTL verification platform. “This release concludes a seven month development period,” says Philipp Wagner of the project’s development progress. “Instead of going directly to cocotb 2.0, we threw in another backwards-compatible ...

All Invited to the OpenTapeOut Open Source ASIC Design Conference This Weekend

by Gareth Halfacree on FOSSi – AB Open 05 November 2021 15:30 UTC

The free and open source silicon community, both established and simply interested, is invited to a new event this weekend: the OpenTapeOut Conference 2021, hosted by Zero to ASIC course creator Matt Venn. “We encourage all of you folks to join us at what we hope will be the start of a revolution! No matter who you are or where you are from, don’t care what you did, as long as you love ASICs [Application Specific Integrated Circuits] and electronics in general,” the event’s organisers ...

How the Imagination RVfpga: Understanding Computer Architecture course is giving engineering under-grads real-world skills | Robert Owen, Imagination Technologies

by RISC-V Community News on Blog – RISC-V International 05 November 2021 15:14 UTC

If you were to take a look through the academic materials now available about RISC-V you will find a wealth of information around SoC creation, including inventing special instructions and numerous implementation enhancements. But what about the vital “Start Here” materials – the foundation needed by teachers to bring the fundamentals of computer architecture to life? This content contains the relatively unglamorous beginnings of the education process. Every computer science, computer ...

Improving the OpenLane ASIC build flow with open source SystemVerilog support | Antmicro

by Antmicro on Blog – RISC-V International 04 November 2021 01:53 UTC

Open source toolchains are key to building collaborative ecosystems, welcoming to new approaches, opportunistic/focused innovations and niche use cases. The ASIC design domain, especially in the view of the rising tensions around manufacturing and supply chains, are in dire need of a software-driven innovation based on an open source approach. The fledgling open source hardware ecosystem has been energized by the success of RISC-V and is now being vastly expanded to cover the entire ASIC ...

How Alibaba is Porting RISC-V to the Android OS | Guoyin Chen, Alibaba

by RISC-V Community News on Blog – RISC-V International 02 November 2021 16:40 UTC

With the high performance Alibaba T-Head XuanTie processor coming to market, we believe it will benefit the RISC-V industry to port RISCV to the Android OS. Over the past year, Alibaba T-Head has spent tremendous effort porting Android 10 to the RISC-V instruction set architecture (ISA). Of course, the Android ecosystem is rather complicated. Though we are still far from being done, we have made good progress, especially on some of the key aspects such as Android NDK, Bionic, ART and ...

OTA: Bluetooth Tracking, Ethernet Sniffing, pySim Bug Fixes, and More

by Gareth Halfacree on MyriadRF 30 October 2021 06:21 UTC

Researchers from the University of California at San Diego (UC San Diego) have published a paper highlighting location-tracking attacks against mobile devices which leverage fingerprinting of Bluetooth Low Energy (BLE) physical layer attributes. “Mobile devices increasingly function as wireless tracking beacons. Using the Bluetooth Low Energy (BLE) protocol, mobile devices such as smartphones and smartwatches continuously transmit beacons to inform passive listeners about device locations ...

Automatic SystemVerilog linting in GitHub Actions with Verible | Antmicro

by Antmicro on Blog – RISC-V International 30 October 2021 01:56 UTC

With the recent advances in open source ASIC development tools such as Verible, it has become easier to automate tasks and boost developer productivity. The Verible linter is a static code analysis tool that has been helping us and our collaborators to spot and fix stylistic errors and bugs in SystemVerilog code. CI/CD for smaller backlog and better test reliability As part of our work within the newly established CHIPS Alliance SystemVerilog subgroup, Antmicro has made further steps to ...

RISC-V RV32I I-Type | Maven Silicon

by Maven Silicon on Blog – RISC-V International 28 October 2021 13:29 UTC

This video explains the RV32I I-Type instructions. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. The post RISC-V RV32I I-Type | Maven Silicon appeared first on RISC-V International.

Recap of the Fall 2021 CHIPS Alliance Workshop | Rob Mains, CHIPS Alliance

by Rob Mains on Blog – RISC-V International 26 October 2021 14:27 UTC

We recently held our fall 2021 CHIPS Alliance workshop with nearly 160 attendees present for informative seminars covering a range of topics including porting Android to RISC-V, open source ASIC design and FPGA tooling, and OmniXtend. In case you missed the talks, a replay is available on the CHIPS Alliance YouTube channel. During the seminar, we had eight exciting technical presentations, including: Porting Android to RISC-V – Guoyin Chen and Han Mao, Alibaba Practical Adoption of Open ...

Alibaba’s T-Head Releases Four RISC-V Cores Under a Permissive Licence

by Gareth Halfacree on FOSSi – AB Open 20 October 2021 15:12 UTC

Alibaba has released the source code for its XuanTie E902, E906, C906, and C910 RISC-V processor cores, promising to follow their release with additional development tools, software development kits, and customisations in the future. Designed by Alibaba’s T-Head semiconductor arm, the XuanTie C906 was launched as a low-power in-order core for the Internet of Things, finding a commercial home in Allwinner’s D1 system-on-chip. The C910 is a higher performance out-of-order design, still built ...

Cocotb 1.6.0 provides better HDL datatypes, improved coroutine scheduling, and much more

by FOSSi Foundation on FOSSi Foundation - News & Posts 20 October 2021 00:00 UTC

The cocotb project is proud to announce the immediate release of its new version 1.6.0. cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. Cocotb can be installed and updated from PyPi through pip: python3 -m pip install --upgrade cocotb For full installation instructions refer to the documentation at https://docs.cocotb.org/en/v1.6.0/install.html. This release concludes a seven month development period. Instead of going directly ...

De-RISC – The H2020 Project Which Will Create The First RISC-V Fully European Platform For Aerospace, Celebrates Its Second Anniversary | Ana Rísquez Navarro, De-RISC

by RISC-V Community News on Blog – RISC-V International 19 October 2021 21:25 UTC

The De-RISC Project celebrates its second year through the introduction of a market-ready hardware-software platform based on the RISC-V instruction set architecture (ISA), productizing a multi-core RISC-V system-on-chip and an efficient time and space partitioning hypervisor.   Valencia, October 18th 2021 – After two years of execution, the international team of researchers from the De-RISC project continue developing the first RISC-V fully European platform for aerospace. “I am proud of ...

ZAYA Now Offers Trusted Execution Environment For RISC-V | ZAYA

by RISC-V Community News on Blog – RISC-V International 13 October 2021 22:42 UTC

Cambridge, UK – October 06, 2021, ZAYA now offers Trusted Execution Environments for RISC-V Architecture. There are different security approaches for IoT Security, and one of the popular approaches is having a Trusted Execution Environment (TEE) on an IoT Device. A TEE shall collect all sensitive resources and operations and isolate itself from the rest of the system. In case of an attack, the malfunctioned operation cannot access the sensitive operations in the TEE so that the sensitive ...

El Correo Libre Issue 43

by Gareth Halfacree on LibreCores - Medium 12 October 2021 08:47 UTC

Guidelines for Sharing FPGA Designs PublishedHDL designs are conceptually at a crossroads between software and hardware. On the one hand, HDL is code. On the other hand, the ultimate object of that code is not to ‘run’ anywhere, but to configure FPGAs or to serve as a basis for the design and manufacture of an integrated circuit. Because of this hybrid nature, HDL designers have traditionally developed best practices coming from both the software and hardware worlds. It was customary to ...

RISC-V Mentorship: Formal Verification of SweRV EL2 Processor | Shashank V.M.

by RISC-V Community News on Blog – RISC-V International 07 October 2021 22:58 UTC

Background I was in the final year of my undergraduate degree in Electronics and Communication Engineering when I learnt out about the RISC-V Mentorship program from the RISC-V Careers page. Having a strong interest in Computer Architecture and Formal Verification, I was eager to contribute to open source hardware engineering projects to gain experience in this field. Mr. Matt Venn of Symbiotic EDA provided an academic licensed Symbiotic EDA tool to me at no cost, after I requested for this ...

Open-Source Hardware Will Deliver a “Plethora” of New Devices, Researchers Conclude

by Gareth Halfacree on FOSSi – AB Open 06 October 2021 13:03 UTC

Frank Hannig and Jürgen Teich, of the Friedrich-Alexander University Erlangen- Nürnberg, have penned their thoughts on open-source hardware in the latest issue of IEEE Computer – concluding it will “pave the way to a plethora of new fantastic electronic devices.” “One of the amazing things about open source is that it is not just about open source software (OSS) code only any longer,” says issue editor Dirk Riehl. “The open source movement has brought open collaboration and open licensing ...

How RISC-V and CHIPS Alliance are Driving a New Unified Memory Architecture Standard | CHIPS Alliance

by Ted Marena on Blog – RISC-V International 05 October 2021 17:04 UTC

RISC-V is so much more than just an ISA for processors. Because of the openness of RISC-V, we are seeing an increase in innovation around processing architectures. One such example is OmniXtend. It is based on the open cache coherent memory bus, Tilelink, which is often used to connect multiple RISC-V CPU cores in SoCs. OmniXtend takes this open standard one step further and allows the cache bus to work over an Ethernet fabric! The result is a new architecture where multiple devices can ...

Agenda for the RISC-V Summit 2021: Together We Are Shaping the Open Era of Computing

by Kim McMahon on Blog – RISC-V International 01 October 2021 19:50 UTC

The RISC-V Summit is the flagship event of the RISC-V community, bringing together people from around the world to show the power of open collaboration across industries. Join us virtually or in-person to hear from industry experts at leading companies including Andes Technology, NVIDIA, Siemens EDA, Western Digital, and more as they share their RISC-V technology advancements. The RISC-V Summit 2021 will be held from Monday, Dec. 6 to Wednesday, Dec. 8, virtually and in-person at the ...

OTA: The EC Praises MyriadRF, FutureSDR Gets its First Blocks, Counting Crowds Through Walls, and More

by Gareth Halfacree on MyriadRF 01 October 2021 10:02 UTC

MyriadRF has been highlighted by the European Commission as an exemplar of how open source software and hardware can provide what its report describes as a clear “public good. In a report into the impact of open source software and hardware on the European economy, the European Commission’s Directorate-General for Communications Networks, Content and Technology found that open source represented “a public good,” and that we are entering a new era where “digital businesses are built using ...

Maven Silicon organized a Panel Discussion on the topic “Hard-to-Hire VLSI Engineers”

by Maven Silicon on Blog – RISC-V International 28 September 2021 14:09 UTC

The semiconductor industry experts shared their perspectives on hiring and upskilling the VLSI engineers in this insightful panel discussion organized by Maven Silicon. In this panel discussion, Sivakumar P R, Founder and CEO, Maven Silicon, emphasizes the importance of learning processor concepts and explains why RISC-V processor, and how it helps the next generation of chip designers to deal with the systems for handling various things like CPU verification, SoC verification, virtual ...

Privileged Specification Version 1.12 Now Open to Public Review

by Stephano Cetola on Blog – RISC-V International 27 September 2021 23:20 UTC

We are delighted to announce that several specifications have been opened to public review. All of these specifications add functionality to the RISC-V Privileged Specification. Several important extensions are being reviewed including Version 1.0 of the Hypervisor (H) model, Enhance Physical Memory Protection (ePMP), and several virtual memory specifications. With 10 privileged specifications in total, we have broken this public review up into pieces for two reasons. First, we’d like to ...

Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas Software

by Kevin McDermott on Blog – RISC-V International 24 September 2021 14:40 UTC

One of the appealing things about open-source is that it invites modification to the underlying technology. In the case of the RISC-V instruction set architecture (ISA), this includes adding user-defined extensions to the processor core itself. Naturally, this level of extensibility has implications on the design flow, particularly if the core is going to be instantiated in silicon within an SoC or ASIC device.  Today, many products are largely software-defined and take advantage of OTA ...

…and out come SweRVolf | Olof Kindgren, Qamcom

by Olof Kindgren on Blog – RISC-V International 23 September 2021 02:38 UTC

One of the main FOSSi projects I’ve been running the last couple of years is SweRVolf, a FuseSoC-based reference platform for Western Digital’s family of RISC-V cores collectively called SweRV. I have written about SweRVolf before (e.g. here and here) so I won’t go too much into details other than noting that it was created to provide an easy way to get started with the SweRV cores for both software and hardware developers and be simple enough to grasp for aspiring engineers while still ...

RISC-V Launches the Open Hardware Diversity Alliance

by Kim McMahon on Announcements – RISC-V International 16 September 2021 13:52 UTC

Founded in Collaboration with the CHIPS Alliance, OpenPOWER Foundation, and Western Digital, the Alliance is Focused on Providing Support Programs, Learning Opportunities, and Mentoring for Women and Underrepresented Individuals in the Open Hardware Community   ZURICH – Sept. 16, 2021 – RISC-V International, a global open hardware standards organization, today announced the launch of the Open Hardware Diversity Alliance. The global Alliance, created ...

RISC-V Pioneer SiFive Opens its First UK Office, Announces Hiring Push

by Gareth Halfacree on FOSSi – AB Open 16 September 2021 10:02 UTC

RISC-V pioneer SiFive has opened its first office in the UK, and promises that staff there will enjoy “location flexibility” as the company looks to expand its presence and grow the RISC-V ecosystem. “I have exciting news to share,” Andrew Frame, formerly of Cambridge-based proprietary chip IP giant Arm, wrote in an announcement on LinkedIn. “As the very first UK employee of SiFive I’m pleased to announce that SiFive UK is here and we’re hiring.” Founded in 2015 by Krste Asanović, Yunsup ...

El Correo Libre Issue 42

by Gareth Halfacree on LibreCores - Medium 14 September 2021 05:43 UTC

Google Summer of Code (GSoC) 2021 was a Success!As summer comes to an end, we have also completed this year’s iteration of Google Summer of Code (GSoC). We at FOSSi Foundation are delighted to say that all of our students this summer successfully completed their projects. For multiple years now, FOSSi Foundation has acted as an umbrella organization for GSoC projects and this year we were particularly excited to have eleven students receiving mentorship from our community. All projects ...

...and out come SweRVolf

by Olof Kindgren on Tales from Beyond the Register Map 13 September 2021 16:49 UTC

 One of the main FOSSi projects I've been running the last couple of years is SweRVolf, a FuseSoC-based reference platform for Western Digital's family of RISC-V cores collectively called SweRV. I have written about SweRVolf before (e.g. here and here) so I won't go too much into details other than noting that it was created to provide an easy way to get started with the SweRV cores for both software and hardware developers and be simple enough to grasp for aspiring engineers while still ...

LAST CHANCE TO SUBMIT YOUR TALK TO THE 2021 RISC-V SUMMIT!

by RISC-V Community News on Blog – RISC-V International 09 September 2021 13:30 UTC

Time is running out! The Call for Papers is open until Friday, September 10 at 11:59 pm PST. (Yes – TOMORROW!) Don’t miss your opportunity to show off and share your contributions to the RISC-V ISA and ecosystem. The 2021 RISC-V Summit is a fully featured hybrid event so all speakers, attendees and sponsors have the opportunity to attend in-person or virtually. Make sure you’re part of the Open era of computing! ...

GSoC 2021 Was a Success!

by FOSSi Foundation on FOSSi Foundation - News & Posts 09 September 2021 00:00 UTC

As summer comes to an end, we have also completed this year’s iteration of Google Summer of Code (GSoC). We at FOSSi Foundation are delighted to say that all of our students this summer successfully completed their projects. For multiple years now, FOSSi Foundation has acted as an umbrella organization for GSoC projects and this year we were particularly excited to have eleven students receiving mentorship from our community. All projects were mentored by trusted community members, ...

Public Review Period Opens for Proposed RISC-V Scalar Cryptography Extensions

by Gareth Halfacree on FOSSi – AB Open 07 September 2021 14:08 UTC

The RISC-V Cryptography Extensions Task Group has opened a public review period on a raft of instruction set extensions, ahead of their planned adoption as official standards – including instructions for AES encryption and decryption and the SM3 hash and SM4 block cipher. “This specification has been developed by the RISC-V Cryptography Extensions Task Group under the governance of the Unprivileged and the Security Committees,” says Richard Newell, chair of the RISC-V Cryptography ...

European Commission Report Declares Open Source Software and Hardware to be a “Public Good”

by Gareth Halfacree on FOSSi – AB Open 06 September 2021 14:16 UTC

A team in the Future Networks arm of the European Commission has released a report on the impact of open source software and hardware on a series of areas of the European Union’s economy – and formally identifies it as a “public good.” “The objective of the study was to investigate and quantify the economic impact of OSS and OSH [Open Source Software and Open Source Hardware] on the European economy,” the study’s authors, working for the Directorate-General for Communications Networks, ...

RISC-V Cryptography Extensions Task Group Announces Public Review of the Scalar Cryptography Extensions

by Stephano Cetola on Blog – RISC-V International 03 September 2021 16:10 UTC

The Cryptography Extensions Task Group is delighted to announce the start of the public review period for the RISC-V Scalar Cryptography extensions. The RISC-V Scalar Cryptography extensions enable the acceleration of cryptographic workloads and add support for narrow 32 and 64-bit data paths. Additionally, these extensions dramatically lower the barrier to entry for secure and efficient accelerated cryptography in IoT and embedded devices. The proposed standard Scalar Cryptography ...

Google Summer of Code’21 at FOSSi Foundation: TensorCore Extension for Deep Learning | Nitin Mishra

by RISC-V Community News on Blog – RISC-V International 30 August 2021 17:28 UTC

Introduction This has been a great summer! I was fortunate enough to be accepted into the Google Summer Code(GSOC) program for the “TensorCore Extension for Deep Learning” project offered by the Free & Open Source Silicon(FOSSi) foundation under the supervision of Theodore Omtzigt with Steven Hoover and Ákos Hadnagy. And I’ve been able to reach most of the milestones that we set out to achieve. Read on to understand what this project is all about and how you can contribute to it! The link ...

OTA: SDR++ Hits v1.0.0, Bluetooth Hits 5.3, Elektro-L3 Goes LRIT, and More

by Gareth Halfacree on MyriadRF 27 August 2021 12:47 UTC

Alexandre Rouma’s SDR++ project, a cross-platform open-source package for software defined radio work with built-in support for LimeSDR-family hardware, has hit a milestone: the release of version 1.0.0. “For those who don’t know,” Alexandre explains, “SDR++ is a cross-platform (Windows, Linux, MacOS, BSD) and open-source general purpose receiver software meant to be simple and easy to use. It has advanced features like multi-vfo and uses a fully custom DSP making it very efficient.” We ...

Open source custom GitHub Actions runners with Google Cloud and Terraform | Antmicro

by Antmicro on Blog – RISC-V International 26 August 2021 19:26 UTC

As we continue our push for more software-driven hardware development as part of our work within CHIPS Alliance and RISC-V, we see an increasing need for scalable and flexible CI solutions that can be used with a mix of open source and proprietary components. By building on top of existing infrastructure such as GCP, GH Actions and Terraform, it’s possible to achieve noticeable performance gains, better traceability and runtime isolation for some of the advanced use cases we are helping our ...

Google Summer of Code’21 at FOSSI Foundation: M-extension Support for SERV | Zeeshan Rafique, RISC-V Ambassador

by RISC-V Community News on Blog – RISC-V International 23 August 2021 18:40 UTC

This project aims to design and integrate the integer “Multiplication and Division Unit (MDU)” with SERV core as a co-processor. The MDU will support all the instructions that are provided in “‘The RISC-V Instruction Set Manual. Volume I: Unprivileged ISA’ chapter 7, M-Standard Extension for Integer Multiplication and Division, Version 2.0”. This MDU is to be designed in a way that it would use most of the DSP resources on the targeted FPGA board. It would be generic and parameterized so ...

RISC-V RV32I R-Type | Maven Silicon

by Maven Silicon on Blog – RISC-V International 17 August 2021 13:00 UTC

This video explains the RV32I R-Type instructions. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. The post RISC-V RV32I R-Type | Maven Silicon appeared first on RISC-V International.

Announcing public review for RISC-V standard extensions Zfinx, Zdinx, Zhinx, and Zhinxmin

by Stephano Cetola on Blog – RISC-V International 10 August 2021 22:11 UTC

The RISC-V Zfinx Task Group is thrilled to announce the Zfinx extension (pronounced “z-f-in-x”) has entered the public review period. The Zfinx extension brings the much needed instructions for floating point in integer registers to the RISC-V ISA. The current public review period includes consideration of the the following Zfinx extensions: Zfinx – Single-precision floating point in integer registers Zdinx – Double-precision floating point in integer registers Zhinx – Half-precision ...

El Correo Libre Issue 41

by Gareth Halfacree on LibreCores - Medium 10 August 2021 08:54 UTC

FOSSi Foundation Welcomes Jonathan Balkind to the Board of DirectorsThe Free and Open Source Silicon Foundation is happy to announce today that Jonathan Balkind is joining the board of directors. Jonathan has been a trusted member of the FOSSi community for many years, where he has shown great skill in solving challenging technical problems, as well as teaching hardware design, and communicating the benefits of doing so openly. Jonathan is most well-known for his work on OpenPiton, an ...

StarFive open source single board hardware platform will be officially released by the end of Q3 2021

by Selina Zheng on Blog – RISC-V International 05 August 2021 17:50 UTC

At Starfive Technology, we have been committed to promoting the development of the global RISC-V open source software and hardware ecosystem since we were founded. Although the BeagleV-StarLight joint development board is no longer in mass production, we completely respect our partner’s decision and appreciate the contribution of all developers in the Beagle Board community. We look forward to collaborating again in the near future, and will continue to uphold our attitude in creating ...

seL4 Integrity Enforcement Proved for RISC-V

by Gernot Heiser on Blog – RISC-V International 03 August 2021 15:12 UTC

The seL4 Foundation and RISC-V International are pleased to announce that Ryan Barry from UNSW Sydney has completed the proof that the seL4 microkernel on the RISC-V architecture enforces the key security property of integrity. The proof shows that seL4 will only allow a thread to access an object or memory resource if the access is explicitly authorised by a capability. Specifically, user code cannot write to memory for which it does not hold a write capability (nor will the kernel perform ...