Planet LibreCores

Recap of the Fall 2021 CHIPS Alliance Workshop | Rob Mains, CHIPS Alliance

by Rob Mains on Blog – RISC-V International
We recently held our fall 2021 CHIPS Alliance workshop with nearly 160 attendees present for informative seminars covering a range of topics including porting Android to RISC-V, open source ASIC design and FPGA tooling, and OmniXtend. In case you missed the talks, a replay is available on the CHIPS Alliance YouTube channel. During the seminar, we had eight exciting technical presentations, including: Porting Android to RISC-V – Guoyin Chen and Han Mao, Alibaba Practical Adoption of Open ...

Alibaba’s T-Head Releases Four RISC-V Cores Under a Permissive Licence

by Gareth Halfacree on FOSSi – AB Open
Alibaba has released the source code for its XuanTie E902, E906, C906, and C910 RISC-V processor cores, promising to follow their release with additional development tools, software development kits, and customisations in the future. Designed by Alibaba’s T-Head semiconductor arm, the XuanTie C906 was launched as a low-power in-order core for the Internet of Things, finding a commercial home in Allwinner’s D1 system-on-chip. The C910 is a higher performance out-of-order design, still built ...

Cocotb 1.6.0 provides better HDL datatypes, improved coroutine scheduling, and much more

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image The cocotb project is proud to announce the immediate release of its new version 1.6.0. cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. Cocotb can be installed and updated from PyPi through pip: python3 -m pip install --upgrade cocotb For full installation instructions refer to the documentation at https://docs.cocotb.org/en/v1.6.0/install.html. This release concludes a seven month development period. Instead of going directly ...

De-RISC – The H2020 Project Which Will Create The First RISC-V Fully European Platform For Aerospace, Celebrates Its Second Anniversary | Ana Rísquez Navarro, De-RISC

by RISC-V Community News on Blog – RISC-V International
teaser image The De-RISC Project celebrates its second year through the introduction of a market-ready hardware-software platform based on the RISC-V instruction set architecture (ISA), productizing a multi-core RISC-V system-on-chip and an efficient time and space partitioning hypervisor.   Valencia, October 18th 2021 – After two years of execution, the international team of researchers from the De-RISC project continue developing the first RISC-V fully European platform for aerospace. “I am proud of ...

ZAYA Now Offers Trusted Execution Environment For RISC-V | ZAYA

by RISC-V Community News on Blog – RISC-V International
teaser image Cambridge, UK – October 06, 2021, ZAYA now offers Trusted Execution Environments for RISC-V Architecture. There are different security approaches for IoT Security, and one of the popular approaches is having a Trusted Execution Environment (TEE) on an IoT Device. A TEE shall collect all sensitive resources and operations and isolate itself from the rest of the system. In case of an attack, the malfunctioned operation cannot access the sensitive operations in the TEE so that the sensitive ...

El Correo Libre Issue 43

by Gareth Halfacree on LibreCores - Medium
teaser image Guidelines for Sharing FPGA Designs PublishedHDL designs are conceptually at a crossroads between software and hardware. On the one hand, HDL is code. On the other hand, the ultimate object of that code is not to ‘run’ anywhere, but to configure FPGAs or to serve as a basis for the design and manufacture of an integrated circuit. Because of this hybrid nature, HDL designers have traditionally developed best practices coming from both the software and hardware worlds. It was customary to ...

RISC-V Mentorship: Formal Verification of SweRV EL2 Processor | Shashank V.M.

by RISC-V Community News on Blog – RISC-V International
teaser image Background I was in the final year of my undergraduate degree in Electronics and Communication Engineering when I learnt out about the RISC-V Mentorship program from the RISC-V Careers page. Having a strong interest in Computer Architecture and Formal Verification, I was eager to contribute to open source hardware engineering projects to gain experience in this field. Mr. Matt Venn of Symbiotic EDA provided an academic licensed Symbiotic EDA tool to me at no cost, after I requested for this ...

Open-Source Hardware Will Deliver a “Plethora” of New Devices, Researchers Conclude

by Gareth Halfacree on FOSSi – AB Open
Frank Hannig and Jürgen Teich, of the Friedrich-Alexander University Erlangen- Nürnberg, have penned their thoughts on open-source hardware in the latest issue of IEEE Computer – concluding it will “pave the way to a plethora of new fantastic electronic devices.” “One of the amazing things about open source is that it is not just about open source software (OSS) code only any longer,” says issue editor Dirk Riehl. “The open source movement has brought open collaboration and open licensing ...

How RISC-V and CHIPS Alliance are Driving a New Unified Memory Architecture Standard | CHIPS Alliance

by Ted Marena on Blog – RISC-V International
teaser image RISC-V is so much more than just an ISA for processors. Because of the openness of RISC-V, we are seeing an increase in innovation around processing architectures. One such example is OmniXtend. It is based on the open cache coherent memory bus, Tilelink, which is often used to connect multiple RISC-V CPU cores in SoCs. OmniXtend takes this open standard one step further and allows the cache bus to work over an Ethernet fabric! The result is a new architecture where multiple devices can ...

Agenda for the RISC-V Summit 2021: Together We Are Shaping the Open Era of Computing

by Kim McMahon on Blog – RISC-V International
The RISC-V Summit is the flagship event of the RISC-V community, bringing together people from around the world to show the power of open collaboration across industries. Join us virtually or in-person to hear from industry experts at leading companies including Andes Technology, NVIDIA, Siemens EDA, Western Digital, and more as they share their RISC-V technology advancements. The RISC-V Summit 2021 will be held from Monday, Dec. 6 to Wednesday, Dec. 8, virtually and in-person at the ...

OTA: The EC Praises MyriadRF, FutureSDR Gets its First Blocks, Counting Crowds Through Walls, and More

by Gareth Halfacree on MyriadRF
MyriadRF has been highlighted by the European Commission as an exemplar of how open source software and hardware can provide what its report describes as a clear “public good. In a report into the impact of open source software and hardware on the European economy, the European Commission’s Directorate-General for Communications Networks, Content and Technology found that open source represented “a public good,” and that we are entering a new era where “digital businesses are built using ...

Maven Silicon organized a Panel Discussion on the topic “Hard-to-Hire VLSI Engineers”

by Maven Silicon on Blog – RISC-V International
teaser image The semiconductor industry experts shared their perspectives on hiring and upskilling the VLSI engineers in this insightful panel discussion organized by Maven Silicon. In this panel discussion, Sivakumar P R, Founder and CEO, Maven Silicon, emphasizes the importance of learning processor concepts and explains why RISC-V processor, and how it helps the next generation of chip designers to deal with the systems for handling various things like CPU verification, SoC verification, virtual ...

Privileged Specification Version 1.12 Now Open to Public Review

by Stephano Cetola on Blog – RISC-V International
We are delighted to announce that several specifications have been opened to public review. All of these specifications add functionality to the RISC-V Privileged Specification. Several important extensions are being reviewed including Version 1.0 of the Hypervisor (H) model, Enhance Physical Memory Protection (ePMP), and several virtual memory specifications. With 10 privileged specifications in total, we have broken this public review up into pieces for two reasons. First, we’d like to ...

Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas Software

by Kevin McDermott on Blog – RISC-V International
teaser image One of the appealing things about open-source is that it invites modification to the underlying technology. In the case of the RISC-V instruction set architecture (ISA), this includes adding user-defined extensions to the processor core itself. Naturally, this level of extensibility has implications on the design flow, particularly if the core is going to be instantiated in silicon within an SoC or ASIC device.  Today, many products are largely software-defined and take advantage of OTA ...

…and out come SweRVolf | Olof Kindgren, Qamcom

by Olof Kindgren on Blog – RISC-V International
teaser image One of the main FOSSi projects I’ve been running the last couple of years is SweRVolf, a FuseSoC-based reference platform for Western Digital’s family of RISC-V cores collectively called SweRV. I have written about SweRVolf before (e.g. here and here) so I won’t go too much into details other than noting that it was created to provide an easy way to get started with the SweRV cores for both software and hardware developers and be simple enough to grasp for aspiring engineers while still ...

RISC-V Launches the Open Hardware Diversity Alliance

by Kim McMahon on Announcements – RISC-V International
Founded in Collaboration with the CHIPS Alliance, OpenPOWER Foundation, and Western Digital, the Alliance is Focused on Providing Support Programs, Learning Opportunities, and Mentoring for Women and Underrepresented Individuals in the Open Hardware Community   ZURICH – Sept. 16, 2021 – RISC-V International, a global open hardware standards organization, today announced the launch of the Open Hardware Diversity Alliance. The global Alliance, created ...

RISC-V Pioneer SiFive Opens its First UK Office, Announces Hiring Push

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneer SiFive has opened its first office in the UK, and promises that staff there will enjoy “location flexibility” as the company looks to expand its presence and grow the RISC-V ecosystem. “I have exciting news to share,” Andrew Frame, formerly of Cambridge-based proprietary chip IP giant Arm, wrote in an announcement on LinkedIn. “As the very first UK employee of SiFive I’m pleased to announce that SiFive UK is here and we’re hiring.” Founded in 2015 by Krste Asanović, Yunsup ...

El Correo Libre Issue 42

by Gareth Halfacree on LibreCores - Medium
teaser image Google Summer of Code (GSoC) 2021 was a Success!As summer comes to an end, we have also completed this year’s iteration of Google Summer of Code (GSoC). We at FOSSi Foundation are delighted to say that all of our students this summer successfully completed their projects. For multiple years now, FOSSi Foundation has acted as an umbrella organization for GSoC projects and this year we were particularly excited to have eleven students receiving mentorship from our community. All projects ...

...and out come SweRVolf

by Olof Kindgren on Tales from Beyond the Register Map
teaser image  One of the main FOSSi projects I've been running the last couple of years is SweRVolf, a FuseSoC-based reference platform for Western Digital's family of RISC-V cores collectively called SweRV. I have written about SweRVolf before (e.g. here and here) so I won't go too much into details other than noting that it was created to provide an easy way to get started with the SweRV cores for both software and hardware developers and be simple enough to grasp for aspiring engineers while still ...

LAST CHANCE TO SUBMIT YOUR TALK TO THE 2021 RISC-V SUMMIT!

by RISC-V Community News on Blog – RISC-V International
teaser image Time is running out! The Call for Papers is open until Friday, September 10 at 11:59 pm PST. (Yes – TOMORROW!) Don’t miss your opportunity to show off and share your contributions to the RISC-V ISA and ecosystem. The 2021 RISC-V Summit is a fully featured hybrid event so all speakers, attendees and sponsors have the opportunity to attend in-person or virtually. Make sure you’re part of the Open era of computing! ...

GSoC 2021 Was a Success!

by FOSSi Foundation on FOSSi Foundation - News & Posts
As summer comes to an end, we have also completed this year’s iteration of Google Summer of Code (GSoC). We at FOSSi Foundation are delighted to say that all of our students this summer successfully completed their projects. For multiple years now, FOSSi Foundation has acted as an umbrella organization for GSoC projects and this year we were particularly excited to have eleven students receiving mentorship from our community. All projects were mentored by trusted community members, ...

Public Review Period Opens for Proposed RISC-V Scalar Cryptography Extensions

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Cryptography Extensions Task Group has opened a public review period on a raft of instruction set extensions, ahead of their planned adoption as official standards – including instructions for AES encryption and decryption and the SM3 hash and SM4 block cipher. “This specification has been developed by the RISC-V Cryptography Extensions Task Group under the governance of the Unprivileged and the Security Committees,” says Richard Newell, chair of the RISC-V Cryptography ...

European Commission Report Declares Open Source Software and Hardware to be a “Public Good”

by Gareth Halfacree on FOSSi – AB Open
A team in the Future Networks arm of the European Commission has released a report on the impact of open source software and hardware on a series of areas of the European Union’s economy – and formally identifies it as a “public good.” “The objective of the study was to investigate and quantify the economic impact of OSS and OSH [Open Source Software and Open Source Hardware] on the European economy,” the study’s authors, working for the Directorate-General for Communications Networks, ...

RISC-V Cryptography Extensions Task Group Announces Public Review of the Scalar Cryptography Extensions

by Stephano Cetola on Blog – RISC-V International
The Cryptography Extensions Task Group is delighted to announce the start of the public review period for the RISC-V Scalar Cryptography extensions. The RISC-V Scalar Cryptography extensions enable the acceleration of cryptographic workloads and add support for narrow 32 and 64-bit data paths. Additionally, these extensions dramatically lower the barrier to entry for secure and efficient accelerated cryptography in IoT and embedded devices. The proposed standard Scalar Cryptography ...

Google Summer of Code’21 at FOSSi Foundation: TensorCore Extension for Deep Learning | Nitin Mishra

by RISC-V Community News on Blog – RISC-V International
teaser image Introduction This has been a great summer! I was fortunate enough to be accepted into the Google Summer Code(GSOC) program for the “TensorCore Extension for Deep Learning” project offered by the Free & Open Source Silicon(FOSSi) foundation under the supervision of Theodore Omtzigt with Steven Hoover and Ákos Hadnagy. And I’ve been able to reach most of the milestones that we set out to achieve. Read on to understand what this project is all about and how you can contribute to it! The link ...

OTA: SDR++ Hits v1.0.0, Bluetooth Hits 5.3, Elektro-L3 Goes LRIT, and More

by Gareth Halfacree on MyriadRF
Alexandre Rouma’s SDR++ project, a cross-platform open-source package for software defined radio work with built-in support for LimeSDR-family hardware, has hit a milestone: the release of version 1.0.0. “For those who don’t know,” Alexandre explains, “SDR++ is a cross-platform (Windows, Linux, MacOS, BSD) and open-source general purpose receiver software meant to be simple and easy to use. It has advanced features like multi-vfo and uses a fully custom DSP making it very efficient.” We ...

Open source custom GitHub Actions runners with Google Cloud and Terraform | Antmicro

by Antmicro on Blog – RISC-V International
teaser image As we continue our push for more software-driven hardware development as part of our work within CHIPS Alliance and RISC-V, we see an increasing need for scalable and flexible CI solutions that can be used with a mix of open source and proprietary components. By building on top of existing infrastructure such as GCP, GH Actions and Terraform, it’s possible to achieve noticeable performance gains, better traceability and runtime isolation for some of the advanced use cases we are helping our ...

Google Summer of Code’21 at FOSSI Foundation: M-extension Support for SERV | Zeeshan Rafique, RISC-V Ambassador

by RISC-V Community News on Blog – RISC-V International
teaser image This project aims to design and integrate the integer “Multiplication and Division Unit (MDU)” with SERV core as a co-processor. The MDU will support all the instructions that are provided in “‘The RISC-V Instruction Set Manual. Volume I: Unprivileged ISA’ chapter 7, M-Standard Extension for Integer Multiplication and Division, Version 2.0”. This MDU is to be designed in a way that it would use most of the DSP resources on the targeted FPGA board. It would be generic and parameterized so ...

RISC-V RV32I R-Type | Maven Silicon

by Maven Silicon on Blog – RISC-V International
This video explains the RV32I R-Type instructions. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. The post RISC-V RV32I R-Type | Maven Silicon appeared first on RISC-V International.

Announcing public review for RISC-V standard extensions Zfinx, Zdinx, Zhinx, and Zhinxmin

by Stephano Cetola on Blog – RISC-V International
The RISC-V Zfinx Task Group is thrilled to announce the Zfinx extension (pronounced “z-f-in-x”) has entered the public review period. The Zfinx extension brings the much needed instructions for floating point in integer registers to the RISC-V ISA. The current public review period includes consideration of the the following Zfinx extensions: Zfinx – Single-precision floating point in integer registers Zdinx – Double-precision floating point in integer registers Zhinx – Half-precision ...

El Correo Libre Issue 41

by Gareth Halfacree on LibreCores - Medium
teaser image FOSSi Foundation Welcomes Jonathan Balkind to the Board of DirectorsThe Free and Open Source Silicon Foundation is happy to announce today that Jonathan Balkind is joining the board of directors. Jonathan has been a trusted member of the FOSSi community for many years, where he has shown great skill in solving challenging technical problems, as well as teaching hardware design, and communicating the benefits of doing so openly. Jonathan is most well-known for his work on OpenPiton, an ...

StarFive open source single board hardware platform will be officially released by the end of Q3 2021

by Selina Zheng on Blog – RISC-V International
At Starfive Technology, we have been committed to promoting the development of the global RISC-V open source software and hardware ecosystem since we were founded. Although the BeagleV-StarLight joint development board is no longer in mass production, we completely respect our partner’s decision and appreciate the contribution of all developers in the Beagle Board community. We look forward to collaborating again in the near future, and will continue to uphold our attitude in creating ...

seL4 Integrity Enforcement Proved for RISC-V

by Gernot Heiser on Blog – RISC-V International
teaser image The seL4 Foundation and RISC-V International are pleased to announce that Ryan Barry from UNSW Sydney has completed the proof that the seL4 microkernel on the RISC-V architecture enforces the key security property of integrity. The proof shows that seL4 will only allow a thread to access an object or memory resource if the access is explicitly authorised by a capability. Specifically, user code cannot write to memory for which it does not hold a write capability (nor will the kernel perform ...

“中国信芯” 再迈一步,万向区块链携生态伙伴举办RISC-V区块链行业工作组首次公开活动

by Wanxiang Blockchain on Blog – RISC-V International
teaser image (点击这里查看原文) 由上海科技大学和中国科学院软件研究所联合主办,中国RISC-V产业联盟(CRVIC)、中国开放指令生态联盟(CRVA)、CNRV社区协办的第一届「RISC-V中国峰会」于日前盛大开幕。6月24日,万向区块链作为RISC-V 区块链行业工作组(Blockchain SIG)的发起单位,携手上下游生态企业在上海科技大学(张江校区)举办“区块链+RISC-V”专场论坛及研讨会。   RISC-V区块链行业工作组于今年2月由万向区块链携手摩联科技、跃昉科技、赛昉科技、SiFive共同发起成立,致力于通过研究探索芯片和区块链技术的整合构筑“中国信芯”(Chinese ...

OTA: New LimeNET Gets AMD Ryzen Power, uSDR Launched, Open RAN Competition, and More

by Gareth Halfacree on MyriadRF
Lime Microsystems has announced a new version of its LimeSDR-powered LimeNET 5G-capable software-defined radio-network-in-a-box – now featuring a 16-core high-performance AMD Ryzen processor. “We are excited to collaborate with Lime Microsystems and the LimeNET ecosystem,” said AMD’s senior director of applications engineering Kun-Yip Liu of the project, “to enable innovative and high-performance 5G edge services running on AMD Ryzen and embedded processors.” “LimeNET powered by AMD leading ...

The 2021 RISC-V Summit Will Demonstrate Adoptions and Technical Advances This December in San Francisco

by Kim McMahon on Announcements – RISC-V International
ZURICH and SAN FRANCISCO – July 28, 2021 – RISC-V International announced the 2021 RISC-V Summit that will bring together the open hardware community for three days of deep technical talks, industry updates, networking, and more. The RISC-V Summit will be held at Moscone West in San Francisco from December 6-8, 2021, and will feature hybrid in-person and virtual activities to connect with a global audience. “Every year the RISC-V Summit draws larger crowds who gather with other RISC-V ...

Wavious Releases a RISC-V LPDDR4x/5 PHY as an Apache-Licensed Open-Source Project

by Gareth Halfacree on FOSSi – AB Open
Wavious, a fabless semiconductor company which offers a platform based on mix-and-match “chiplets,” has launched a RISC-V-powered open-source LPDDR4x/5 PHY – under the permissive Apache 2.0 licence. “We are strong believers in open-source hardware and software,” the company said in its announcement, “and Wavious is dedicated to making significant contributions to the open source community. Open-source HW [hardware] and chiplets are both necessary to remove barriers to entry and to drive ...

Life in a Formal Verification Lane | Shivani Shah

by Shivani Shah on Blog – RISC-V International
teaser image This summer, I got the opportunity to work as a Formal Verification Intern with Axiomise for six weeks. I’m a keen designer and love working in design and architecture. Although, I’ve not started my professional career yet, I have done most of my projects as a designer in my undergraduate and postgraduate studies. Having said that, I was always curious to know – how do we test that the design works? How is verification done in the industry? I had a prior design experience in building ...

What You Need to Know About Verilator Open Source Tooling | Rob Mains, CHIPS Alliance

by Rob Mains on Blog – RISC-V International
Verilator is a high performance, open source functional simulator that has gained tremendous popularity in its usage and adoption in the verification of chip design. The ASIC development community has widely embraced Verilator as an effective, often even superior alternative to proprietary solutions, and it is now the standard approach in RISC-V CPU design as the community has worked to provide Verilator simulation capabilities out of the box. CHIPS Alliance and RISC-V leaders Antmicro and ...

A Free RISC-V CPU Core Builder – Democratizing CPUs | Steve Hoover, Redwood EDA

by Steve Hoover on Blog – RISC-V International
teaser image There are now over a hundred RISC-V CPU cores listed in the RISC-V Exchange! Amazing. If you need a RISC-V CPU core, you’ll likely be able to find one that suits your needs… if you evaluate a hundred CPU cores to find it. Or, now, you can configure exactly the core you need, and have it built in seconds, for free! WARP-V is the most flexible RISC-V CPU core available, and recently, Indiana University student, Adam Ratzman, created an online configurator for WARP-V. If you need a ...

El Correo Libre Issue 40

by Gareth Halfacree on LibreCores - Medium
teaser image Google Summer of Code (GSoC) Class of 2021The FOSSi Foundation is happy to introduce our Google Summer of Code Class of 2021 projects. This year we are grateful that we have been granted eleven slots by Google to support projects and students. We are thankful for all mentors who volunteered to supervise students, and we’re looking forward to a great summer working together on Free and Open Source Silicon projects.Virtual FPGA Lab (Bala Dhinesh)Mentored by Kunal Ghosh, Ákos Hadnagy, and ...

FOSSi Foundation welcomes Jonathan Balkind on the board of directors

by FOSSi Foundation on FOSSi Foundation - News & Posts
The Free and Open Source Silicon Foundation is happy to announce today that Jonathan Balkind is joining the board of directors. Jonathan has been a trusted member of the FOSSi community for many years, where he has shown great skill in solving challenging technical problems, as well as teaching hardware design, and communicating the benefits of doing so openly. Jonathan is most well-known for his work on OpenPiton, an open source research processor which can be scaled up to multiple ...

RISC-V RV32I Assembly – Multiplication | Maven Silicon

by Maven Silicon on Blog – RISC-V International
This video shows how we can implement the Multiplication using add and shift RV32I instructions. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc.   To know more, explore our RISC-V courses. The post RISC-V RV32I Assembly – Multiplication | Maven Silicon appeared first on RISC-V International.

The Importance of Increasing Diversity in the Open Source Community

by Kim McMahon on Blog – RISC-V International
It’s no secret that the past twenty years has seen remarkable progress in technology innovation.  Smartphones opened up a whole new ecosystem of applications and possibilities, cars have become more connected and safer, and there are now RISC-V based software systems created to work in space! We’ve truly created a world that is unlike anything we’ve ever seen. As globalization promotes the exchange of ideas across borders, we’re continuing to reap the benefits of collaboration in our highly ...

NeuralScale: Industry Leading General Purpose Programmable NPU Architecture based on RISC-V

by Mark Zhan on Blog – RISC-V International
teaser image AI and its diverse applications have seen significant increasing demand for AI computing in clouds over the last few years. Typical AI-enabled services include image and speech recognition, natural language processing, medical diagnosis, visual search, and personalized recommendations. AI computing in clouds includes two distinct workloads: training and inference. AI inference is reported to constitute more than 95% of AI computing workloads in clouds.  Meanwhile, we have seen significant ...

A Process Independent Power Optimised Register File Architecture

by Tony Stansfield on Blog – RISC-V International
teaser image Overview This white paper describes how low-power memory technology, originally designed for large, high density, SRAMs has been enhanced and adapted to deliver low-power, low-voltage register files. Introduction There is a large, and growing, class of applications for which power is a critical factor, sometimes as a result of a desire to add increased functionality to already power-constrained devices, and in some cases where on-chip SRAM gives the most power efficient implementations. For ...

Wanxiang Blockchain Organized the First Public Activity of RISC-V Blockchain SIG with Partners

by Wanxiang Blockchain on Blog – RISC-V International
teaser image On June 24, during the RISC-V World Conference China 2021 hosted by ShanghaiTech University, Institute of Software Chinese Academy of Sciences, CRVIC, CRVA and CNRV, Wanxiang Blockchain, as one of the initiators of RISC-V Blockchain Special Interest Group (SIG), organized a Blockchain + RISC-V Forum and Workshop. The RISC-V Blockchain SIG, jointly established in February 2021 by Wanxiang Blockchain, ...

OTA: OpenBSC Setup Scripts, 80MSPS from a LimeSDR Mini, a Satellite Hunt, and More

by Gareth Halfacree on MyriadRF
Community member Bastien Baranoff has shared scripts for getting a Raspberry Pi system running Ubuntu Server up-and-running as an open cellular base station with Osmocom’s OpenBSC and a LimeSDR. Designed for Raspberry Pi systems running Canonical’s free and open source Ubuntu Server Linux distribution, Bastien’s scripts begin by installing the necessary software for turning a LimeSDR software-defined radio into a cellular base station. The first script automates the installation of ...

Version 3.9.0 released

by Esko Pekkarinen on Kactus2: News
New PythonAPI for accessing Kactus2 data+ New interfaces for IP-XACT data read and modify+ Generator runs for selected generators e.g. Verilog New Python console in graphical user interface+ Run interactive scripts+ View command history+ Save and run script files Kactus2 editors adapted to new interfaces+ Ports+ Parameters+ Fields+ Field resets+ Registers+ Address block+ Memory maps+ Files+ File sets+ Component instantiations+ Port maps+ Port abstractions+ Bus interfaces Added ...

GSoC Class of 2021

by FOSSi Foundation on FOSSi Foundation - News & Posts
The FOSSi Foundation is happy to introduce our Google Summer of Code Class of 2021 projects. This year we are grateful that we have been granted eleven slots by Google to support projects and students. We are thankful for all mentors who volunteered to supervise students, and we’re looking forward to a great summer working together on Free and Open Source Silicon projects. These projects are our “GSoC Class of 2021”. Please give our students a warm welcome! Virtual FPGA Lab (Bala ...

RISC: Open Hardware

by David Patterson on Blog – RISC-V International
Peggy and David Patterson, pardee professor of computer science, Emeritus, University of California at Berkeley, talk about RISC and how it brings openness to hardware design. He says in the beginning ease of use was the top priority with technology, and now we are paying the price with security. They also discuss: Why testing can reveal the presence of bugs but can’t reveal the absence of bugs. How RISC lets someone do security themselves. How to inspire the next ...

The Heart of SiFive is Performance, Intelligence, & Essential

by Patrick Little on SiFive
teaser image Introducing the new era of SiFive Performance for RISC-V When I joined SiFive last year, I found a dedicated team working on great technology with a vision to do no less than to change the world. As I talked to our customers and partners, it was clear that while we had satisfied users, the industry expected and desired greater things from SiFive. The message was loud and clear that SiFive needed to push the boundaries of what’s possible to bring high value, differentiated products to ...

Embedded Programming and IoT – Memory Management Criticality!

by Tan Rahman on Blog – RISC-V International
teaser image There are two types of IoT devices: high-end devices and low-end devices. The operating systems that are used for high-end devices include fully functional ones like Windows, Linux or Android. For example, Amazon’s echo device uses Fire OS based on Android whilst Samsung smartwatches use Tizen based on Linux. These devices are wired for power or have batteries that are regularly charged. However, low-end devices have a very small amount of memory and work with a low amount of energy often ...

RISC-V QEMU Part 1: Privileged ISA v1.10, HiFive1 and VirtIO

by Michael Clark on SiFive
This post covers recent development in RISC-V QEMU, the open source machine emulator and virtualizer. We’ve been playing a game of catch-up with the hardware folks so that we can match the capabilities of the Freedom U500 SDK. We’re not quite there yet, but we’ve made some important improvements that will allow for a more usable emulator. First, some background on software emulation of Instruction Set Architectures. There are several forms of emulators and they fall broadly into these ...

All Aboard, Part 10: How to Contribute to the RISC-V Software Ecosystem

by Palmer Dabbelt on SiFive
We recently announced the HiFive Unleashed, a development board for Freedom U540-C000, the world's first Linux-capable RISC-V ASIC. The announcement of this board roughly lined up with the first upstream releases of Linux and glibc that contain RISC-V support. As a result, our news has driven a lot of interest from the open source software community -- that was really the whole point of announcing the board in the first place, so in that sense it's working out very well. This new wave of ...

SiFive’s Approach to Embedding Intelligence Everywhere

by Tom Simon on SiFive
teaser image Published by SemiWiki. Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made over many years. RISC-V was conceived with a clean well-thought-out architecture and designed for expansion that would not create inconsistencies. Because it is open source, there is a rich set of ...

The SiFive 20G1 Update for 7-Series Core IP

by Drew Barbier on SiFive
Faster, More Efficient SiFive 7-Series Core IP Today, we’re announcing the SiFive 20G1 6.0 update, which is focused on improving the 7-Series line of products. Our previous release, SiFive 20G1, was a comprehensive update that spanned from the 7-Series to the 2-Series, including U-, S-, and E-Cores. Similarly, the 20G1 6.0 update improves the performance, features, and functionality of SiFive 7-Series U-, S-, and E-Cores. Ever since the 7-Series introduction in 2018, SiFive has been able to ...

All Aboard, Part 2: Relocations in ELF Toolchains

by Palmer Dabbelt on SiFive
Our first stop on our exploration of the RISC-V toolchain will be an overview of ELF relocations and how they are used by the RISC-V toolchain. We'll shy away from discussing linker relaxations and their impact on performance for a follow-up blog post so this doesn't get too long. The example has been carefully constructed to be unrelaxable as to avoid confusion. Additionally, we're only going to discuss the relocations used by statically linked executables, avoid discussing position ...

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part I

by Camille Kokozaki on SiFive
teaser image SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing, Calista Redmond was just appointed the new CEO of the RISC-V Foundation). He shared a slide showing the growing RISC-V ecosystem from tools vendors, to IP/semi chip ...

All Aboard, Part 1: The -march, -mabi, and -mtune arguments to RISC-V Compilers

by Palmer Dabbelt on SiFive
Before we can board the RISC-V train, we'll have to take a stop at the metaphorical ticket office: our machine-specific GCC command-line arguments. These arguments all begin with -m, and are all specific to the RISC-V architecture port. In general, we've tried to match existing conventions for these arguments, but like pretty much everything else there are enough quirks to warrant a blog post. This blog discusses the arguments most fundamental to the RISC-V ISA: the -march, -mabi, ...

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Last updated 27 October 2021 03:01 UTC