Planet LibreCores

CRU: RISC-V Momentum, Carbon Nanotubes, Fire, ICE, and More

by Gareth Halfacree on FOSSi – AB Open
RISC-V Foundation chief executive officer Calista Redmond has written of increasing momentum for RISC-V, as the semiconductor industry begins to shift away from proprietary closed-source core. “Interest in RISC-V has been gaining steam with commercial implementations and adoption rapidly growing. It has been incredible to witness how RISC-V has fostered industry-wide collaboration to solve tomorrow’s design needs, including some of the toughest challenges like security,” Redmond writes in ...

RISC-V: Fast Start In Two Days | Harry Schubert, Elektronik

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
With training for professionals in RISC-V, Elektronik will introduce interested parties to the RISC-V instruction set architecture and the 32-bit and 64-bit RISC-V cores of the PULP platform. The trainers are experts from ETH Zurich and from Greenwaves Technologies.article: https://www.elektroniknet.de/elektronik/halbleiter/schnelleinstieg-in-zwei-tagen-169312.html The post RISC-V: Fast Start In Two Days | Harry Schubert, Elektronik appeared first on RISC-V Foundation.

OpenPower Foundation, IBM Release Fire and ICE OMI Reference Implementations

by Gareth Halfacree on FOSSi – AB Open
IBM has made good on its commitment, through the OpenPOWER Foundation, to release an Open Memory Interface (OMI) under a permissive licence, with the first reference designs for its Fire OMI host and ICE two-port DDR4 OMI device hitting GitHub this month. The OpenPOWER Foundation made the surprising announcement that it was shifting the POWER instruction set architecture (ISA) to an an open model back in August, partnering with the Linux Foundation to release POWER under a permissive ...

Israel is Evolving as a High-Tech Hub, and RISC-V is Playing a Vital Role

by Aijaz Qaisar on SiFive
teaser image Israel, and specifically the city of Tel Aviv, is said to have one of the highest densities of startups per capita in the world. At our SiFive Tech Symposium, we heard from some of the brightest minds residing at the epicenter of this high-tech hub. They shared their visions for the industry as well as their contributions to the semiconductor ecosystem via RISC-V based solutions. This is the second year in a row that we’ve hosted the SiFive Tech Symposium is Israel. With our partners, ...

Intrinsic ID Security Summit

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
teaser image The Intrinsic ID Security Summit on October 7 will include Hex Five founder and CEO Cesare Galati. Register today to hear expert speakers and network with security professionals.For more information, see the event site. The post Intrinsic ID Security Summit appeared first on RISC-V Foundation.

Security in the Age of RISC-V: Bay Area Meetup Oct 1

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
Rambus will host a security session related to RISC-V on October 1, 2019.Agenda 6:00-6:45 Networking Reception 6:45-7:00 Microchip – Rich Newell or Ted Speers (Secure RISC-V SoC FPGA) 7:00-7:15 Draper 7:15-7:30 QuickLogic 7:30-7:45 Rambus – Helena Handschuh (RISC-V & Security Overview) 7:45-8:00 Riscure 8:00-8:15 Foundries.io 8:15 Q & AFor more information, see the meetup page. Hope to see you there! The post Security in the Age of RISC-V: Bay Area Meetup Oct 1 appeared first on RISC-V ...

RISC-V Week in Paris, October 1-3

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
After the first 1st RISC-V Meeting on academic opportunities held in Grenoble in October 2018, the second edition will take place in Paris on October 1st and 2nd 2019. They are open to the academic and industrial worlds and they will address several important topics: The impact of the arrival of open-source on the design of systems on a chip (SoC), embedded systems or cyber-physics (CPS). Legal and strategic intellectual property (IP) issues, ranging from public management of hardware open ...

Antmicro Releases FastVDMA Open-Source Resource-Light DMA Controller

by Gareth Halfacree on FOSSi – AB Open
Antmicro has announced the release of FastVDMA, an open-source direct memory access (DMA) controller designed to improve the freedom of FPGA-based free and open source silicon projects. “One of the main motivations leading to the design of an open source DMA controller was the lack of portable open source alternatives to proprietary controllers provided by FPGA vendors,” the company explains in its announcement. “This situation leads to a reduction in the reusability of DMA-based designs ...

OTA: Active Cooling Cases, QRadioLink 0.8.0, GNSS Observation, and More

by Gareth Halfacree on MyriadRF
LimeSDR Mini and LimeSDR USB owners seeking additional cooling should take a look at the Hacker Gadgets Lime Active Cooling (AC) Case, heading to Crowd Supply next month. Designed to provide both a protective enclosure and active, rather than the more usual passive, cooling, the Hacker Gadgets Lime AC Case connects heat sources on the LimeSDR Mini or LimeSDR USB to an aluminium chassis. For those who value silence, the fan can be disabled or removed entirely. “We have finished the design ...

Calista Redmond Points to Growing Momentum for FOSSi, RISC-V

by Gareth Halfacree on FOSSi – AB Open
RISC-V Foundation chief executive officer Calista Redmond has written of increasing momentum for RISC-V, as the semiconductor industry begins to shift away from proprietary closed-source core. “Interest in RISC-V has been gaining steam with commercial implementations and adoption rapidly growing. It has been incredible to witness how RISC-V has fostered industry-wide collaboration to solve tomorrow’s design needs, including some of the toughest challenges like security,” Redmond writes in ...

El Correo Libre Issue 19

by Gareth Halfacree on LibreCores - Medium
teaser image Google Summer of Code Students Complete Their Welcomed ContributionsWhat an exciting summer! We at FOSSi Foundation are happy to announce that all of our Google Summer of Code (GSoC) students this year successfully completed their projects. For multiple years now, FOSSi Foundation has acted as umbrella organisation for multiple GSoC projects. All projects were mentored by trusted community members, and we’re extremely happy how well the projects went! We owe a big thank you to all students ...

FOSSi Foundation Details Google Summer of Code 2019 Project Wins

by Gareth Halfacree on FOSSi – AB Open
The Free and Open Source Silicon (FOSSi) Foundation has announced the end of its participation in the 2019 Google Summer of Code programme, with seven students contributing to projects under the Foundation’s umbrella mentorship. Run by Google each year as a means of matching students with mentors already in the industry, the Google Summer of Code 2019 saw the FOSSi Foundation act as an umbrella organisation pairing students interested in the free and open source silicon movement with ...

Collaboration, Inspiration and Progressive RISC-V Based Innovation in India and Bangladesh is Increasing at a Steady Pace

by Aijaz Qaisar on SiFive
teaser image Our SiFive Tech Symposiums and Workshops in India and Bangladesh were a huge success, and an inspirational endeavor as well. We hosted events in six cities total, including symposiums in Noida/Delhi, Pune, Bangalore and Hyderabad, and workshops in Chennai and Bangladesh’s capital city of Dhaka. Attendance was at capacity in all locations, and was over capacity in Pune and Bangalore. Highlights From India Our co-hosts in India – Western Digital, Microchip and IIT Madras – delivered powerful ...

OpenPiton RISC-V Tutorial at MICRO 2019

by Jonathan Balkind on OpenPiton Blog
teaser image We are excited to announce our new OpenPiton RISC-V tutorial at MICRO 2019! Now is your chance to get hands-on with the RISC-V hardware research platform, including learning to use OpenPiton on Amazon AWS F1. The tutorial is in conjunction with MICRO 2019 in Columbus, Ohio. It is a half-day tutorial on Saturday afternoon, October 12th. Interested attendees can register here and enjoy the early registration discount until September 6th. The tutorial is a hands-on session which will first ...

RISC-V Training in Munich

by Jeffrey Osier-Mixon on Events – RISC-V Foundation
ETH Zurich announces a RISC-V training session with Florian Zaruba, ETH, on 16-17 October, 2019 in ETH’s publishing house in Munich. Register now for the 2-day intensive training with top-class speakers from ETH Zurich and Greenwaves!The training addresses the practical implementation of processor cores with RISC-V instruction sets using the “PULP Platform” of ETH Zurich as an example. The focus is on the two cores “RI5CY” and “Ariane” – both marketed as CORE-V via the OpenHW Group – as ...

Nvidia Turns to RISC-V for RC18 Research Chip IO Core

by Gareth Halfacree on FOSSi – AB Open
High-performance computing company Nvidia has detailed another of its products to use the open RISC-V instruction set architecture (ISA), this time as an input/output core in an inference accelerator part it calls RC18. Developed by the company last year and unveiled in detail during the Hot Chips conference, RC18 is a high-performance accelerator for deep-learning inference workloads boasting 128 trillion operations per second in an energy-efficient 13.5W design. It is build around 16 ...

GSoC 2019

by FOSSi Foundation on FOSSi Foundation - News & Posts
What an exciting summer! We at FOSSi Foundation are happy to announce that all of our Google Summer of Code (GSoC) students this year successfully completed their projects. For multiple years now, FOSSi Foundation acted as umbrella organization for multiple GSoC projects. All projects were mentored by trusted community members, and we’re extremely happy how well the projects went! We owe a big thank you to all students and mentors, thanks to you, the free and open source hardware ecosystem ...

GSoC Report: 64 bit global pointers in RV32 based GP-GPU

by FOSSi Foundation on FOSSi Foundation - News & Posts
This is a guest post by Reshabh Sharma, who worked this summer on a Google Summer of Code (GSoC) project under the umbrella of the FOSSi Foundation. RISC-V will change the world. Prof Taylor’s Bespoke Silicon Group is contributing by developing a GP-GPU based on RISC-V 32 bit ISA (RV32), after the huge success of their Open-Source RISC-V Tiered Accelerator Fabric SoC, Celerity which holds the world record for RISC-V performance; 500B RISC-V instructions per second, beating prior records by ...

OTA: Field Report Contest Complete, Apply for an SDR Satcom Dev Kit, and More

by Gareth Halfacree on MyriadRF
The Field Report Contest is now complete, and we have a winner – named in a live drawing at Crowd Supply’s headquarters earlier this month. Designed to highlight the amazing projects the community has built around the LimeSDR family of software defined radios, the Field Report competition saw some strong entries. Daniel Estévez wrote about his miniature ground station for QO-100 communication, Godfrey Laswai detailed his experiments with rural Digital Audio Broadcasting (DAB), Andrin Doll ...

Verilator - Verilator 4.018 Released

by Wilson Snyder on Veripool: News
Verilator 4.018 2019-08-29 When showing an error, show source code and offer suggestions of replacements. When showing an error, show the instance location, bug1305. [Todd Strader] Add --rr, bug1481. [Todd Strader] Change MULTITOP to warning to help linting, see manual. Add XSim support to driver.pl, bug1493. [Todd Strader] Show included-from filenames in warnings, bug1439. [Todd Strader] Fix elaboration time errors, bug1429. [Udi Finkelstein] Fix not reporting some ...

MIT Unveils World’s First RISC-V Carbon Nanotube Processor, RV16XNano

by Gareth Halfacree on FOSSi – AB Open
Researchers from the Massachusetts Institute of Technology (MIT), working with Analog Devices, have announced the production and execution of the world’s first 16-bit programmable processor built around carbon nanotube field-effect transistors (CNFETs) – and they’ve implemented the open RISC-V instruction set architecture (ISA) on it. One of a range of materials under investigation for the post-silicon era of semiconductors, in order to keep up with the observation turned target by Intel ...

DARPA Takes RISC-V SSITH Voting Machine Prototype to DEF CON 2019

by Gareth Halfacree on FOSSi – AB Open
The US Defence Advanced Research Projects Agency (DARPA) has unveiled the first prototype of its System Security Integrated Through Hardware and Firmware (SSITH) platform for future electronic voting machines, based on an in-house RISC-V processor. Announced back in 2017, the SSITH programme sees researchers working on securing future computing systems against attack with novel hardware and software, in particular new processor designs based on the open RISC-V instruction set architecture ...

Ibex: Code with Confidence

by LowRISC on lowRISC on lowRISC
teaser image Ibex, our small RISC-V core, is constantly changing. Roughly 50 percent of the RTL was refactored recently! We added features, tests, and cleaned the code up. We and our collaborators were able to make these changes (mostly) without breaking Ibex because we invested in testing: earlier this year we added UVM-based verification to the tree, and we run these tests after every change. We run static code analysis to catch common programming bugs. We run software on Ibex to see if it actually ...

CRU: LoRaWAN World Records, SweRVolf SoC, OpenPower, and More

by Gareth Halfacree on FOSSi – AB Open
The Things Network, the community-driven LoRaWAN project, has announced a world record successful transmission distance from the Servet project: 476 miles, or 766 kilometres. Designed for low power yet wide area use, LoRaWAN is the technology behind community-driven wide-area networking project The Things Network – the largest open LoRaWAN network in the world, operating in over 100 countries. The Servet project, meanwhile, is a citizen science initiative focused on experimentation through ...

GigaDevice Unveils Low-Cost GD32V RISC-V Microcontroller

by Gareth Halfacree on FOSSi – AB Open
GigaDevice, a company which has previously concentrated on microcontrollers built around the proprietary Arm instruction set architecture (ISA), has released a new part based on the open RISC-V ISA: GD32V. First spotted by RISC-V pioneer Sipeed late yesterday, the GigaDevice GD32V is based on the Nucleisys N20x RISC-V core, itself a commercialised variant of the LicheeTang E203 RV core, running at 108MHz with 8KB to 16KB of SRAM and 16KB to 128KB of flash memory. Each model is based on 3.3V ...

GSoC Project Report: Continuous Integration for Hardware Projects on LibreCores CI

by FOSSi Foundation on FOSSi Foundation - News & Posts
Librecores provides a platform to share projects and ideas, in the area of free and open-source digital hardware design. Librecores CI is a service to provide CI for hardware projects hosted on Librecores to improve user experience and reliability. This summer, I worked on developing continuous integration pipeline for hardware projects such as OpenRISC, a family of free and open-source processor implementations on the RISC architecture I worked from May to August 2019. In this project I ...

RISC-V Day Tokyo Agenda

by Catherine Lockwood on Events – RISC-V Foundation
The RISC-V Association (RVA), an interim community formed by employees from RISC-V Foundation members, is hosting the RISC-V Day Tokyo on Sept. 30, 2019 at the Hitachi Baba Hall in Kokobunji, Tokyo from 9 a.m. – 8 p.m. JST. During the event, the speakers will cover a variety of topics such as lowering the barrier to silicon, edge server security, open source CPU and subsystem, open source EDA tools, and IoT server infrastructure. They will also discuss the future of RISC-V and its solutions ...

IBM, OpenPOWER Foundation Make POWER ISA Open At Last

by Gareth Halfacree on FOSSi – AB Open
IBM’s OpenPOWER Foundation, set up to build the POWER architecture ecosystem, has made a milestone announcement: it is to make the POWER instruction set architecture, along with key hardware designs and supporting technologies, available under an open source licence. Announced along with the news that the OpenPOWER Foundation is to join the Linux Foundation, the release of the POWER instruction set architecture under an open licensing model marks a major boon for the free and open source ...

QEMU 4.1.0 Extends RISC-V Open ISA Support

by Gareth Halfacree on FOSSi – AB Open
The open-source QEMU machine emulator and virtualiser has received enhanced support for the open RISC-V instruction set architecture (ISA) in its 4.1.0 release. Following on from the 4.0.0 release back in April, QEMU 4.1.0 brings a range of improvements to its support for the open RISC-V ISA. Chief among these are the definition of a new “spike” machine, the release of which officially deprecates older machines. Other improvements include the first support for the RISC-V Privileged ...

Researchers Publish Roadmap for RISC-V Opportunities in Space Tech

by Gareth Halfacree on FOSSi – AB Open
Researchers at the Delft University of Technology have published a roadmap which seeks to maximise the potential of the open RISC-V instruction set architecture (ISA) for space applications across the full range of requirements from low-power microcontrollers up to high-end payload processors for artificial intelligence applications. “This paper proposes a roadmap to address present and future needs in space systems with RISC-V processors,” Stefano Di Mascio, Alessandra Menicucci, Eberhard ...

OTA: SDR Satcom Launch, LimeRFE 1.0, OreSat Field Report, and More

by Gareth Halfacree on MyriadRF
MyriadRF has stretched to the stars this week with the official launch of the SDR Satcom initiative, a collaboration between Lime Microsystems and the European Space Agency (ESA) Designed to help lower the barrier to entry in the satellite communications industry, SDR Satcom combines the low-cost high-performance LimeSDR Mini software defined radio with a Snap-powered software ecosystem dedicated to satellite communication packages and supporting tools. Launched yesterday, the SDR Satcom ...

El Correo Libre Issue 18

by Gareth Halfacree on LibreCores - Medium
teaser image LibreCores Refreshed while ORConf 2019 Speakers ConfirmedFree and open source is all about sharing and reuse. Sharing ideas, sharing algorithms, and most importantly, sharing code. Sharing code requires two things: someone who publishes it, and someone who uses it — along with a connection between the two. This connection is provided by LibreCores, the project repository site maintained by the FOSSi Foundation. LibreCores enables developers to showcase their digital hardware projects, and ...

CHIPS Alliance Launches FuseSoC-Based SweRVolf System on Chip Design

by Gareth Halfacree on FOSSi – AB Open
CHIPS Alliance has launched a system-on-chip (SoC), built using Western Digital’s open-source SweRV Core and the FuseSoC build toolset, dubbed SweRVolf A collaboration between FuseSoC creator and maintainer Olof Kindgren, Western Digital Director of Next Gen Platforms Tech Zvonimir Bandic, outgoing chief technology officer Martin Fink, and CHIPS Alliance, SweRVolf is a functional system-on-chip (SoC) design built around WD’s open-source SweRV EH1 RISC-V core. The design also builds on ...

Andes Technology Points to Explosive RISC-V Growth

by Gareth Halfacree on FOSSi – AB Open
Andes Technology has announced explosive demand for its proprietary processor cores based on the open RISC-V instruction set architecture (ISA), highlighting the growing demand for alternatives to x86, Arm, MIPS, and other proprietary ISAs. Born from the University of California at Berkeley in 2010, the open RISC-V instruction set architecture (ISA) is as permissive as it gets: The licence under which the ISA is made available has no requirement that derivative products be made open-source ...

Dhrystone Performance Tuning on the Freedom Platform

by Fu-Ching Yang on SiFive
teaser image For consumers of low-end processors, the Dhrystone benchmark can be a valuable tool for estimating performance. Due to the nature of the Dhrystone benchmark, high-end Application Processor performance is incompletely represented by a Dhrystone score. For processor providers a Dhrystone score is a commonly used metric for instruction throughput comparison in early stage evaluation. To fairly compare Dhrystone scores, the test conditions must be published. To that end SiFive offers two ...

OTA: Lower-Cost LimeRFE, WSPR Experiments, LoRaWAN World Records, and More

by Gareth Halfacree on MyriadRF
The LimeRFE crowdfunding campaign has a new, lower-cost option: the same programmable software-defined front-end board but without the components needed to operate in cellular bands, as an alternative for radio amateurs. “We’ve had some enquiries as to whether it would be possible to make a reduced cost version of LimeRFE that doesn’t have support for cellular bands,” explains Lime Microsystems’ Andrew Back. “In response to which we’re pleased to announce that we’ll be making 50 boards in ...

Alibaba Unveils High-Performance 16-Core 2.5GHz RISC-V Chip Design

by Gareth Halfacree on FOSSi – AB Open
Alibaba, via the Pingtouge (T-Head) division of its DAMO Academy, has announced what it claims is the world’s most powerful processor based on the open RISC-V instruction set architecture (ISA): a 16-core 2.5GHz design built on a 12nm process node, dubbed the CoreXuanTie910 or XT910. “The breakthrough is more than a mere performance enhancement of RISC-V processors. It means more IoT areas that require high-performance computing such as 5G, AI, networking, gateway, self-driving automobile, ...

SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops

by Swamy Irrinki on SiFive
Last year we hosted several SiFive Tech Symposiums in India to help promulgate the RISC-V ecosystem in the region. The enthusiastic reception from those in industry as well as students and faculty at India's most esteemed universities was inspiring. This July and August, we're bringing the SiFive Tech Symposium back to India, and also visiting Bangladesh. Our goal remains to foster the RISC-V ecosystem and to help prepare university students for entry into a workforce where RISC-V is ...

CRU: RISC-V Soft-Core Contest, Wuthering Bytes Programme, Plan 9 for Raspberry Pi, and More

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation, in partnership with Microchip Technology and Thales, has announced its second soft-core CPU competition – time time focusing on security. Following on from its first soft-core CPU contest late last year, the RISC-V Foundation has announced its second. Where the first focused on performance and smart use of available resources, though, the second has a very different focus: security. “With the proliferation of connected devices, security is one of the key challenges in ...

chisel 3.1.8

by Jim Lawson on Chisel
We’ve recently (7/8/2019) published Chisel v3.1.8 and compatible updates to chisel-testers v1.2.10 and dsptools v1.1.9. This release of the tool set consists of an API addition to support compatibility with the upcoming 3.2 release. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is welcome.

PULP Platform Tapes Out Urania Heterogeneous RISC-V ASIC

by Gareth Halfacree on FOSSi – AB Open
The Parallel Ultra-Low Power (PULP) Platform project has announced tape-out of Urania, an implementation of its bigPULP design which combines one Ariane core with two quad-core RISC-V clusters. Announced back in February last year, Ariane is a 64-bit application-class RISC-V core design, created as a joint effort between ETH Zurich and the University of Bologna. RI5CY, meanwhile, is a 32-bit RISC-V core design popularised by the PULPissimo microcontroller platform. Now, the pair have been ...

Microchip Shows Off Rad-Hardened RISC-V for Low-Cost Satellites

by Gareth Halfacree on FOSSi – AB Open
Microchip’s Dorian Johnson has penned a piece on the open RISC-V instruction set architecture (ISA)’s ascent into space, courtesy of radiation-hardened implementations from his company. “Using the new open RISC-V architecture, the FPGA circuitry can operate advantageously close to a remote measurement source,” Johnson explains in the piece for Elektroniikkalehti. “It enables autonomous data collection, condition monitoring, and load control at the payload source, thus freeing up resources ...

RISC-V Foundation Announces Agenda for “Getting Started with RISC-V” Roadshow in EMEA

by Mark Sinclair on Events – RISC-V Foundation
teaser image  The roadshow will feature live demonstrations and presentations from RISC-V Foundation members, includes free admissionWHAT: The RISC-V Foundation has announced the agenda for its “Getting Started with RISC-V” events across Europe and the Middle East.WHERE: Tel Aviv, Israel; Munich, Germany; Berlin, Germany; Tallinn, Estonia; Paris, France; London, United Kingdom.WHEN: Monday, Sept. 16 to Thursday, Sept. 26, 2019DETAILS: The RISC-V Foundation, in collaboration with the Linux Foundation, is ...

Pepijn de Vos’ 74-Series Project Goes Straight from VHDL to PCB

by Gareth Halfacree on FOSSi – AB Open
Engineer Pepijn de Vos has released the source code and video demonstration for a five-chip 74-series logic gate ‘breathing LED circuit’ – without ever having had to manually design the printed circuit board. “I had been keeping an eye on Yosys, the open source HDL synthesis tool, which can apparently do ASIC by giving it a liberty file that specifies the logic cells your foundry supports,” de Vos explains. “Meanwhile I also toyed with the idea of making a 7400 series computer, and I ...

Six more weeks of Ibex development - what's new?

by LowRISC on lowRISC on lowRISC
teaser image In the past months, we have invested considerable effort in improving our RISC-V core Ibex. This 2-stage, in-order, 32-bit microcontroller-class CPU core was contributed to us by ETH Zürich in December 2018, with activity really ramping up since May. Having been taped out multiple times (as zero-riscy) in a mix of academic and industry projects, it came to us as a relatively mature code base. Despite this, we have continued to invest in improving its design and maintainability. Changes ...

OTA: LimeRFE Schematics, LimeNET Micro Fan Control, Signals and Bits Podcast, and More

by Gareth Halfacree on MyriadRF
Schematics for the LimeRFE software-definable front-end module for LimeSDR and LimeNET devices have been released, as part of Lime Microsystems’ pledge that it will be fully open hardware. “We’ve had a number of requests to share the LimeRFE schematic diagrams, and we’re pleased to report that they are now available on our new LimeRFE hardware design repository,” writes Andrew Back in a Crowd Supply campaign update announcing availability of the preliminary schematics. “As with all MyriadRF ...

OpenPiton’s JuxtaPiton Processor to get Open-Source i486 Core

by Gareth Halfacree on FOSSi – AB Open
Kunal Gulati, working with the OpenPiton Project’s Jonathan Balkind and Katie Lim under the Free and Open Source Silicon Foundation (FOSSi) Google Summer of Code, has announced a project to expand the JuxtaPiton heterogeneous research processor with a third core: ao486. Announced back in November 2018, JuxtaPiton is the merging of the SPARC v9-based OpenPiton with Clifford Wolf’s PicoRV32 RISC-V core in a single open-source research processor design. “When implemented on FPGA, JuxtaPiton ...

The Design Revolution in APAC and Australia

by Aijaz Qaisar on SiFive
teaser image Highlights From the SiFive Tech Symposiums In its endeavor to educate the tech world about the benefits of the RISC-V ISA, SiFive just completed its APAC and Australia series of tech symposiums. Throughout the month of June, symposiums were held in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney. The audience included academia, the business industry, and many RISC-V ecosystem partners. On average, in all seven cities, 60% of the audience came from the tech industry and 40% belonged to ...

RISC-V Foundation Launches Security-Focused Soft-Core CPU Contest

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation, in partnership with Microchip Technology and Thales, has announced its second soft-core CPU competition – time time focusing on security. Following on from its first soft-core CPU contest late last year, the RISC-V Foundation has announced its second. Where the first focused on performance and smart use of available resources, though, the second has a very different focus: security. “With the proliferation of connected devices, security is one of the key challenges in ...

Large-scale RISC-V LLVM testing with Buildroot

by LowRISC on lowRISC on lowRISC
A few years ago lowRISC started developing a new LLVM backend targeting RISC-V. Rather than copying and modifying an existing backend, in an ad hoc fashion, we started from scratch and proceeded systematically. This approach proved successful in producing a high-quality codebase. We recently announced on the llvm-dev mailing list that the backend is now reaching stability and could be promoted from its current status of experimental to an official target. This post explains how our testing ...

The RISC-V LLVM backend in Clang/LLVM 9.0

by LowRISC on lowRISC on lowRISC
On Monday I proposed promoting the upstream RISC-V LLVM backend from “experimental” to “official” for the LLVM 9.0 release. Responses so far are extremely positive, and we’re working to ensure this is a smooth process. This means that from 9.0, the RISC-V backend will be built by default for LLVM, making it usable out of the box for standard LLVM/Clang builds. As well as being more convenient for end users, this also makes it significantly easier for e.g. Rust/Julia/Swift and other ...

El Correo Libre Issue 17

by Gareth Halfacree on LibreCores - Medium
teaser image ORCONF 2019 Three-Month Countdown BeginsIt’s that time of year again. Following on from the FOSSi Foundation’s Latch-Up and WOSH events, ORConf is now less than three months away and if you haven’t heard, we’re hosting it in beautiful Bordeaux, France over the weekend of September 27th to the 29th.ORConf is now in its eight year of bringing the open source silicon community together for a weekend of presentations, ideas, and discussions. We hope many of our fine past attendees will make the ...

Introducing Sam

by LowRISC on lowRISC on lowRISC
teaser image On June 1st, Sam Elliott followed Laura and Pirmin in becoming lowRISC’s newest employee. A few weeks into his new role, he shares why he joined lowRISC and what he’s been doing since he started. “I joined lowRISC CIC as a Compiler Developer, working on the RISC-V LLVM backend, and so far I’m enjoying working on the team! Prior to lowRISC, I worked as a compilers and programming languages researcher at the University of Washington, where I completed my Masters degree. “I worked for ...

OTA: LimeRFE, LimeNET CrowdCell Crowdfunding, Field Reports, and More

by Gareth Halfacree on MyriadRF
The crowdfunding campaign for the LimeRFE, a software-definable front-end module designed for use with LimeSDR hardware, has blown past its funding goal – with over a month left on the clock. Designed to be used with LimeSDR and LimeNET hardware, the LimeRFE is an open-hardware design with open-source software and adds multi-band power amplification (PA) and low-noise amplification (LNA) alongside filtering. Programmable using the Arduino IDE, the LimeRFE is customisable and suitable for ...

Three New Core Series Now Available in SiFive Core Designer

by Amy Lindburg on SiFive
teaser image SiFive Core Designer (SCD) unlocks new possibilities by enabling engineers to explore the architectural design space of a CPU. With our Software-as-a Service (SaaS) application, customers can create and customize RISC-V core IP -- from their laptops. Working within a Core Series (a “class” of Core paired with a specific microarchitecture) customers can rapidly create a range of cores at different design points, run software applications on FPGA bitstreams, simulate with RTL, and ultimately ...

ORConf 2019 Announcement

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image It’s that time of year again. Following on from the FOSSi Foundation’s Latch-Up and WOSH events, ORConf is now less than 3 months away and if you haven’t heard, we’re hosting it in beautiful Bordeaux, France over the weekend of September 27 to 29. ORConf is in its 8th year of bringing the open source silicon community together for a weekend of presentations, ideas and discussions. We hope many of our fine past attendees will make the trip to France to join us again for what should be ...

When Hardware Roadmaps Look Like Software Roadmaps

by Drew Barbier on SiFive
The traditional cadence for microarchitecture updates is usually tied to process technology nodes or ground-up redesigns. The SiFive Core IP portfolio offers scalable microarchitectures from efficient application multi-core processors capable of running Linux, to tiny, power-sipping cores suitable for the most area constrained design points. The SiFive quarterly update program delivers key improvements, new features, and more capabilities to SiFive Core IP in a measured, methodical way. ...

Silicon At The Speed of Software

by James Prior on SiFive
The Information age transformed the world, fueled by silicon chips that became more powerful and more cost-effective every 18 months. The thinking of silicon design was led by engineers in the pursuit of faster, smaller transistors. As the Experience Age transcends the Information Age, the law underneath the technology changes from what’s possible, to what’s needed. Now, the ability to create purpose-built processors – secure, fast, efficient, and cost-effective – is the defining ...

Freedom in Software and in the Metal

by Drew Barbier on SiFive
With the move to a quarterly release program (see: Silicon At Speed Of Software), SiFive is innovating in the hardware space at an unprecedented pace. In the SiFive Core Designer update and the Core IP update we learned about new features being added to SiFive Core IP and the ability to quickly access those features via SiFive Core Designer, SiFive's Software-as-a Service (SaaS) application. We have also been hard at work making sure that our software enablement is just as configurable, and ...

What's happing in the open silicon ecosystem around you? Planet LibreCores helps you to get the latest news from all corners of the community by aggregating blog posts.

All content here is unfiltered and uncensored, and represents the views of the post authors. Individual posts are owned by their authors; please see the original source for licensing information.

Subscribe to Planet LibreCores

In addition to reading the posts here, you can subscribe to Planet LibreCores in your favorite feed reader.

Planet Librecores Atom feed

Or get the subscription list through FOAF or OPML.

Last updated 23 September 2019 09:00 UTC