Planet LibreCores

Introduction To SiFive Vector Processors

by Andy Frame on SiFive
teaser image After describing the current 2022 broad SiFive Performance, Intelligence, and Essential Processor Product portfolio, this webinar introduction to the SiFive vector processors begins by identifying some of the challenges that exist for system designers and subsequent evolving application trends. Click here to watch the full webinar: The semiconductor market is constantly looking to simplify design cycles while striving for more portability and re-use, broader extensibility, and increasing ...

Version 3.10.0 released

by Esko Pekkarinen on Kactus2: News
PythonAPI improvements:+ Bus interfaces and port maps are now accessible through the API Python console changed to proper text editor in graphical user interface+ More convenient editing and running of script files GUI improvements:+ Port map tree view changed back to table format for better readability and performance+ Editor title font size increased for bettter navigation+ Library and component editor trees now automatically expand children until branch is found making navigation ...

Democratizing Chiplet-Based Processor Design | Ventana Micro Systems

by RISC-V Community News on Blog Archives - RISC-V International
teaser image By Bob Wheeler, Principal Analyst, The Linley Group Chiplet-based designs promise reduced development costs and faster time to market, but they’ve  been exclusive to large chip vendors. Now, the industry is building an ecosystem intended to enable designs combining third-party chiplets that employ different process nodes. At the same  time, RISC-V is enabling greater CPU innovation through its open-source model. These trends  create an opportunity for a RISC-V chiplet vendor. Ventana Micro ...

RISC-V Vector Processing is Taking Off | SiFive

by RISC-V Community News on Blog Archives - RISC-V International
teaser image The RISC-V Vector Extension (RVV) Version 1.0 was ratified by RISC-V International in 2021. Since this public debut, there has been growing excitement about vector processing across a wide spectrum of applications since vectors promise to solve multiple current industry design and development challenges.  Licensable IP is already commercially available today and more solutions are expected in the marketplace soon as the robust RISC-V ecosystem embraces the advantages of RISC-V vector ...

GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves Technologies

by RISC-V Community News on Blog Archives - RISC-V International
teaser image Located in the micro-and nano-electronics hotspot of Grenoble, GreenWaves is a fabless semiconductor startup that designs and brings to market advanced ultra-low-power AI and DSP processors for energy-constrained applications. Our first product GAP8, one of the first commercially available RISC-V AI processors, has been in production for more than a year. It is uniquely optimised to execute a large spectrum of image and audio algorithms including convolution neural network inference and ...

Overtake the Competition in Automotive Design with RISC-V Innovations | Codasip

by RISC-V Community News on Blog Archives - RISC-V International
teaser image In conversation with Jamie Broome, Codasip VP of Automotive   Jamie Broome recently joined Codasip as VP Automotive with more than 20 years of semiconductor and automotive experience, after being responsible for Imagination Technologies’ automotive strategy. In this interview, he shares the exciting opportunities ahead for RISC-V, the changing landscape of compute, and how the automotive industry is adapting to the explosion of user technology and the oncoming challenges from connected and ...

RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V International

by RISC-V Community News on Announcements Archives - RISC-V International
Efficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline As Development Extends Into Vertical Applications.   Nuremberg, Germany – June 21, 2022 – RISC-V International, the global open-design standards pioneer, announced its first four specification and extension approvals of 2022 – Efficient Trace for RISC-V (E-Trace), RISC-V ...

Renode 1.13 for improved machine learning and pre-silicon development | Antmicro

by RISC-V Community News on Blog Archives - RISC-V International
teaser image After a longer while, we are excited to announce that the next release of Renode is here. Since the previous release we’ve been busy working with many customers and partners, including Google, Microchip and Betrusted, on various use cases, all of which led to numerous improvements, as well as new features, that are now available in our simulation framework. Fow a while now Renode has been seeing adoption not only in IoT and product development, but increasingly in new silicon development ...

Thermal (IR) Imaging Pipeline (ISP) Core on PolarFire® SoC FPGA SoM | Microchip

by RISC-V Community News on Blog Archives - RISC-V International
teaser image Our Mi-V partner, Digital Core Technologies (DCT), has developed a thermal Imaging Pipeline on PolarFire® SoC FPGA. The thermal Image Signal Processor (ISP) is an extremely low power and yet, powerful alternative for the thermal imaging available in other architectures. This can be tuned for various applications like Security/Surveillance, Medical imaging, Industrial Monitoring, Gas detections and others. The Pipeline is built to run on DCT’s SoM, CMSV_A1_PF254_AX. This SoM carries the ...

First Analog/Mixed Signal Project Results

by Fatsie on Chips4Makers.io
teaser image In a previous professional life I have been working on radiation hardened SRAM compiler design amongst other things. There I used Cadence Virtuoso for analog circuit development. It is one of the proprietary reference analog design platforms. As a hobby I was also doing open source software development enjoying the big potential development acceleration that can be seen through open source community based development. As an open source proponent I also longed for a world where analog blocks ...

XuanTie C906 Tops MLPerf Tiny v0.7 Benchmark | MengChang, Alibaba Cloud

by RISC-V Community News on Blog Archives - RISC-V International
teaser image XuanTie C906 is a processor developed by Alibaba Cloud based on the RISC-V instruction set architecture. It has attained top marks in the most recent findings from MLPerf Tiny v0.7, an AI benchmark focusing on IoT devices. The performance of XuanTie C906 excelled in all four core categories: Visual Wake Words (VWW), Image Classifications (IC), Keyword Spotting (KWS), and Anomaly Detection (AD). About MLPerf Tiny MLPerf Tiny Inference is a benchmark developed by MLCommons. It is designed to ...

El Correo Libre Issue 51

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image Google Launches Resource Portal for Building Open Silicon Google, as part of its partnership with Efabless and Skywater Technologies on the Open MPW program which allows free and open source silicon projects to submit chip designs for physical fabrication at no cost, has launched a new resource portal aimed at getting people started designing their own chips. “Since November 2020, when Skywater Technologies announced their partnership with Google to open source their Process Design Kit ...

PyVSC: Working with Coverage Data

by Matthew Ballance on Bits, Bytes, and Gates
I’ve been investing some time in documentation updates this weekend, after a couple of PyVSC users pointed out some under-described aspects of the PyVSC coverage flow. Given that these areas were under-documented in the past, it seemed a good opportunity to highlight what can be done with functional coverage data once it is sampled by a PyVSC covergroup.So, we’ve described some functional

LibreCellular Project Update

by Andrew Back on MyriadRF
teaser image Since the project was announced last year we’ve suffered a number of setbacks due to circumstances outside of our control. For example, the company we planned to use for customised rack mount enclosures exited the market due to pandemic related issues. However, we are pleased to report that we are now making good progress and a long overdue update follows. Design Changes We have made a number of improvements to the CI hardware platform design and the largest being a change from each ...

Why MIPS is Betting Big on RISC-V: Q&A with RISC-V International and MIPS | MIPS

by RISC-V Community News on Blog Archives - RISC-V International
MIPS recently announced that the company is pivoting to RISC-V and introduced its first MIPS products based on RISC-V, targeting automotive, 5G and wireless networking, data center and storage, and high-performance embedded applications. This is huge news for the industry as MIPS is one of the pioneers of RISC architecture. RISC-V International CEO Calista Redmond chatted with MIPS CEO Desi Banatao to get some insight into MIPS’ RISC-V strategy, the company’s plans to contribute to the ...

RISC-V Summit China 2022 Call for Talks is Now Open

by RISC-V Community News on Blog Archives - RISC-V International
The RISC-V Summit China 2022 will showcase the continued rapid expansion of the RISC-V ecosystem, with both commercial offerings and exciting open-source developments. The event will take place Aug 24 – Aug 26, 2022 (Shanghai Timezone) and will be virtual/online but may have local meetups and watching parties. RISC-V International, ShanghaiTech University and Institute of Software, Chinese Academy of Sciences will hold the second annual RISC-V Summit China online from Aug 24 to 26, 2022. ...

lowRISC Acquires NewAE Technology, Adding Advanced Security Analysis Tools to the OpenTitan Platform

by lowRISC on lowRISC: Collaborative open silicon engineering
lowRISC C.I.C., the open source organization dedicated to bringing secure collaborative innovation to silicon development, today announced the acquisition of NewAE Technology, Inc., a privately-held designer and manufacturer of broadly accessible silicon security analysis tools. The acquisition brings added momentum to lowRISC, whose OpenTitan project – a collaboration between lowRISC, Google, Western Digital, Seagate and other commercial and academic partners – has created the first ...

OTA: Stratospheric LimeSDRs, Automated Transcriptions, LimeSDR Mini 2 Launch, and More

by Gareth Halfacree on MyriadRF
The LimeSDR-powered Portsdown digital TV transmitter project has been featured in the latest issue of The MagPi Magazine, showcasing how low-cost software-defined radio is being used by the British Amateur Television Club (BATC). “Now Dave [Crump, chair of the BATC] has completed Portsdown 4, using the more powerful Raspberry Pi 4 Model B [and] a Raspberry Pi 7-inch touchscreen and strong case have made a complete travel-ready unit suitable for outdoor transmission,” PJ Evans writes of the ...

Introduction To The SiFive Intelligence X280

by Andy Frame on SiFive
teaser image SiFive is the market leader in RISC-V Vector processors with the flagship SiFive vector processor, the SiFive Intelligence X280, leading the charge as a clear favorite with customers, with solutions being designed into a broad range of applications ranging from computer vision, mobile ISP, Edge AI, to datacenter AI. The X280 is gaining significant market traction due to a number of factors, including: Design Flexibility Power and performance efficiency Portability Ease of ...

SiFive - The Market Leader In RISC-V Vectors

by Andy Frame on SiFive
teaser image SiFive is the market leader in RISC-V Vector processors and has gained significant market traction, with solutions being designed into a broad range of applications ranging from computer vision, mobile ISP, Edge AI, to datacenter AI. As SiFive vector processors become the go-to workhorse processor for modern workloads, they are being chosen for stand-alone and companion processor designs in both large and small systems. As a growing list of customers use our designs, they feed back to us ...

10 Important Things To Know About SiFive Vectors

by Andy Frame on SiFive
teaser image A great way to get to know more about popular SiFive vector processors, which are compatible with the RISC-V Vector (RVV) version 1.0 specification 1.) The RISC-V Vector (RVV) ISA was ratified at version 1.0 by RISC-V International in December of 2021 but it’s fair to say it’s been a big part of the SiFive and RISC-V journey and was being contemplated by the original inventors of RISC-V, namely Krste Asanovic, Andrew Waterman and Yunsup Lee, right from the beginning of the inception of ...

The Investment Heard Around The World

by Chris Jones on SiFive
teaser image The RISC-V revolution continues to advance as the technology industry embraces open computing to address semiconductor design and business challenges Last week saw momentous announcements, with Intel Foundry Services (IFS) enabling RISC-V alongside other processor architectures as part of Intel’s dedication to an open ecosystem and to help make IFS become one of the world’s leading foundries. By joining RISC-V International and investing significant money and resources in the open ...

Beginners Guide To RISC-V Vector Processing

by on SiFive
teaser image The RISC-V Vector Extension (RVV) was ratified at Version 1.0 by RISC-V International in 2021. SiFive is the market leader in RISC-V Vector processors releasing the first licensable IP incorporating this version, the SiFive® Intelligence™ X280 and the SiFive Performance™ P270 Processors, to customers in mid-2021. The X280 processor is a 64-bit RISC-V, Linux capable, RISC-V Vector processor offering best-in-class high performance and efficiency targeting AI and ML workloads. The X280 ...

Simplifying the Vehicle to Anything (V2X) Journey: Porting of Jamaica VM on PolarFire® SoC Icicle Kit | Leah Iris, Microchip

by RISC-V Community News on Blog Archives - RISC-V International
teaser image Industries like manufacturing and automotive are facing the challenges of getting access to device-wide data, analyzing useful data and combining and processing data in the vehicle or on the edge device and in the cloud. Access to operational data from the edge device will revolutionize device maintenance. Our joint solution with aicas allows you to access and analyze millions of data in vehicles and edge devices. aicas and Microchip Develop Joint Cloud-to-Edge Solution to Access Deep ...

MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability | MIPS

by RISC-V Community News on Blog Archives - RISC-V International
teaser image MIPS previews the first IP solutions in the eVocore product lineup: P8700 and I8500 multiprocessors. SAN JOSE, Calif., May 10, 2022 /PRNewswire/ — MIPS, a leading developer of highly scalable RISC processor IP, announces its entrance to the RISC-V market, previewing the first products in its eVocore product lineup. The new eVocore P8700 and I8500 multiprocessor IP cores are the first MIPS products based on the RISC-V open instruction set architecture (ISA) standard. ...

El Correo Libre Issue 50

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image RISC-V Architecture Profiles v0.6 Published “For Discussion Only” The first formal releases of the RISC-V Profiles specification, v0.5 and v0.6, have been published - but its authors warn that it is “for discussion only,” and “is likely to change substantially” between now and official standardisation. “RISC-V was designed to provide a highly modular and extensible instruction set, and includes a large and growing set of standard extensions,” the authors of the RISC-V Profiles ...

OTA: LiteX SoC on the LimeSDR Mini 2.0, DMR on the LimeNET Micro, M17 on LimeSDR, and More

by Gareth Halfacree on MyriadRF
The team at Enjoy Digital has been testing out the upcoming LimeSDR Mini 2.0, and has already turned it into a self-contained computer through the porting of the open-source LiteX system-on-chip to the on-board FPGA — using a fully-open toolchain. Announced last month, the LimeSDR Mini 2.0 is designed to replace the existing LimeSDR Mini design – primarily as a means of working around ongoing shortages in the original model’s FPGA, but handily providing an opportunity increase the resources ...

E4 Computer Engineering joins RISC-V International | E4 Computer Engineering

by RISC-V Community News on Blog Archives - RISC-V International
The company aims to promote the development and application of the RISC-V open standard in ecosystems for HPC applications.   Scandiano (RE), May 3rd 2022 – E4 Computer Engineering (E4) has officially joined RISC-V International (RISC-V), which promotes the development of an ISA (Instruction set architecture) based on open source principles. E4 thus joins companies such as Google, NVIDIA, Qualcomm, IBM and Samsung, among the numerous members of RISC-V and will contribute to the development ...

RISC-V Open Era of Computing – A Conversation with Calista Redmond and Mr. Sivakumar P R , Founder and CEO of Maven Silicon | Maven Silicon

by Maven Silicon on Blog Archives - RISC-V International
India’s top VLSI Training Services company Maven Silicon, a RISC-V Global Training Partner, conducted an insightful discussion with the industry experts Ms. Calista Redmond, CEO, RISC-V International and Mr. Sivakumar P R, CEO, Maven Silicon, on the topic “RISC-V Open Era of Computing”. To introduce RISC-V, it is a free and open ISA, enabling processor, hardware, and software innovations through open collaboration. Maven Silicon’s vision is to produce highly skilled VLSI engineers and help ...

Join us in the classroom! Put RISC-V into your Computer Architecture course using RVfpga! | Robert C.W. Owen, Imagination Technologies

by RISC-V Community News on Blog Archives - RISC-V International
teaser image Dear Professors and Friends, Online is convenient and it has saved us during the pandemic, but you can’t beat in-person class!  That immersive feeling of hands-on and the shared mission with colleagues all trying to master the same subject We are at the start of a global series of workshops to “train the teachers” how to use RISC-V in computer architecture courses and the design of systems on chip (SoCs). We are starting in the USA, then in Europe and then across Asia. Our RVfpga partners, ...

Alibaba Cloud Tops MLPerf Tiny v0.7 Benchmark | Alibaba Cloud

by RISC-V Community News on Blog Archives - RISC-V International
teaser image Alibaba Cloud’s Xuantie C906 processor attained firsts in the most recent findings from MLPerf Tiny v0.7, an AI benchmark focusing on IOT devices. The Xuantie C906’s performance excelled in all four core categories – visual wake words, image classifications, keyword spotting, and anomaly detection. The Xuantie C906 is Alibaba’s custom-built processor based on the RISC-V instruction-set architecture. Xuantie C906’s remarkable performance marks a milestone that showcases the potential of the ...

Xuantie IOMMU from T-Head for RISC-V | Chong Ren, Alibaba Cloud

by RISC-V Community News on Blog Archives - RISC-V International
The recent development of the RISC-V IOMMU effort has attracted substantial attention from the RISC-V community. Xuantie IOMMU from T-Head Semiconductors of Alibaba Group, holding one of the five independent proposals, features a design that is in sync with the current IOMMU Task Group’s charter. An Input / Output Memory Management Unit (IOMMU), analogous to the Memory Management Unit (MMU) in a CPU, is used to regulate the access to main memory by peripheral devices in a computer system. ...

El Correo Libre Issue 49

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image VeriGPU is a Permissively-Licensed ML GPU Core, “Loosely Based” on RISC-V Machine learning researcher Hugh Perkins is working on a project to create an open-source graphics processing unit (GPU), with a view to being able to produce a physical chip suitable for acceleration of machine-learning workloads. “I don’t actually intend to tape this out myself,” Hugh explains, “but I intend to do what I can to verify somehow that tape-out would work OK, timings OK, etc.” The VeriGPU - short for ...

Apply Now For GSoC 2022!

by FOSSi Foundation on FOSSi Foundation - News & Posts
We have once again been selected as a mentor organisation for Google Summer of Code (GSoC) 2022. Google Summer of Code is an excellent program for new open-source contributors to receive a stipend (generously provided by Google) to contribute to open source projects in the FOSSi community. As an organisation, we encompass a variety of community projects in the space of open source silicon design, EDA tools, and the surrounding ecosystem. For those previously familiar with the program, ...

Mi-V Ecosystem Partner Solutions | Leah Iris, Microchip

by RISC-V Community News on Blog Archives - RISC-V International
teaser image The Mi-V RISC-V ecosystem is a continuously expanding, comprehensive suite of tools and design resources developed by Microchip and numerous third parties to fully support RISC-V designs. The Mi-V ecosystem aims to increase adoption of the RISC-V Instruction Set Architecture (ISA) and Microchip’s PolarFire® SoC FPGA and RISC-V soft CPU portfolio. System on Modules (SoMs) Available as Ready-to-Use PolarFire® FPGA Building Blocks ARIES Embedded is one of our Mi-V ecosystem partners. Using ...

XuanTie VirtualZone: RISC-V-based Security Extensions | Xuan Jian, Alibaba Cloud

by RISC-V Community News on Blog Archives - RISC-V International
teaser image Introduction Among many new things in the 21st century, internet and IoT have been one of the most significant human advancements. As fast-paced and accelerating as they evolve, needs for the number of connected devices are increasing substantially as a result. The “Internet of Everything” has become the new future global networks. While the explosive growth of mobile platform usage have enabled successful business transactions, various concerns of security breach arise inevitably. Most ...

TbLink-RPC: Simplifying the Multi-Language Testbench

by Matthew Ballance on Bits, Bytes, and Gates
SystemVerilog/UVM is, by far, the most widely-used language and methodology for block and subsystem-level verification environments today. The simplicity of that statement overlooks the fact that it’s often very common to have other bits of non-SystemVerilog code connected. Maybe it’s some C/C++ code that implements a reference algorithm used by the scoreboard. Maybe it’s an instruction-set

Efabless’ CLEAR, a Fully-Open RISC-V ASIC Built on chipIgnite, Nears its Goal with Days to Go

by Gareth Halfacree on FOSSi Archives - AB Open
CLEAR, a fully-open development board built around a RISC-V embedded-FPGA application-specific integrated circuit (ASIC) designed by Efabless as a showcase of what its chipIgnite platform can offer, is entering the last days of its crowdfunding campaign with just a handful of boards left to reach its goal. “CLEAR is an open source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it,” Efabless ...

OTA: LimeSDR Mini 2.0, Project CAMARA, a Commercial LimeNET Base Station Call, and More

by Gareth Halfacree on MyriadRF
Lime Microsystems has announced the LimeSDR Mini 2.0, an upgraded version of the smallest member of the LimeSDR range featuring a considerably improved field-programmable gate array (FPGA) – boosting its flexibility. Since its launch in 2017, the LimeSDR Mini – a single-channel full-duplex software defined radio built on the same Lime Micro LMS7002M as the LimeSDR USB – has found a home in a wealth of projects not requiring dual-channel operation. Ongoing supply chain issues, however, have ...

RISC-V RV32I JALR Instruction | Maven Silicon

by Maven Silicon on Blog Archives - RISC-V International
This video explains the RV32I JALR instruction. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. Watch the full video.  The post RISC-V RV32I JALR Instruction | Maven Silicon appeared first on RISC-V International.

Ten Reasons to use SiliconCompiler – Including SPDX Provenance Support

by Gareth Halfacree on FOSSi Archives - AB Open
Zero ASIC’s chief executive Andreas Olofsson has called for “all chip designers” to try out the open-source SiliconCompiler build system, showcasing his top ten reasons for giving it a go – including a provenance feature which supports the Software Package Data Exchange (SPDX) standard. “We have been working hard on our open source SiliconCompiler build system for a year now and it’s coming together really nicely,” says Olofsson. “I have been doing chip design and CAD development since 1998 ...

El Correo Libre Issue 48

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image CHIPS Alliance Forms F4PGA Workgroup for Open-Source FPGA Tooling The CHIPS Alliance has announced the formation of the FOSS Flow For FPGA Workgroup, also known as F4PGA, through which it aims to drive open-source tooling, intellectual properties, and research efforts focused on field-programmable gate arrays (FPGAs). “FPGAs are essential for a wide variety of low-latency compute use cases, from telecoms to space applications and beyond. This new F4PGA toolchain will enable a ...

OTA: ADS-B Tracking at the Terminal, Open RAN Silicon, Beginner’s Guides, and More

by Gareth Halfacree on MyriadRF
Developer Wayne Campbell has released version 0.5.1 of rsadsb, a Rust-based ADS-B aircraft tracking system with a text-mode user interface — bringing with it its first support for LimeSDR devices. “Release v0.5.0 of rsadsb is now released,” Wayne writes of the launch. “Use any SDR supported by SoapySDR. If any HackRF or LimeSDR users want to try my software, MR welcome with gain values!” Rsadsb is a a collection of utilities, written in Rust and released under an open-source licence, ...

OpenRISC support added to GLIBC 2.35

by OpenRISC Community on OpenRISC
We would like to announce that GLIBC 2.35 released in February 2022 has support for OpenRISC. Read more about GLIBC toolchain support support over on our software page.

FOSSi Explosion 2021 | Olof Kindgren, FOSSi Foundation and Qamcom

by Olof Kindgren on Blog Archives - RISC-V International
teaser image Do you know what just happened? 2021 just happened. Most years has its ups and downs, but when it comes to 2021 it seems like the prevalent feeling was that everyone just wanted it to be over. And now it is over, except for all those retrospectives. So, with the risk of opening up some old wounds I would like to take a look at what happened last year in my corner of the free and open source silicon world. In the 2020 retrospective I wrote about a couple of big milestones, like the first ...

FOSSi Explosion 2021

by Olof Kindgren on Tales from Beyond the Register Map
teaser image  Do you know what just happened? 2021 just happened. Most years has its ups and downs, but when it comes to 2021 it seems like the prevalent feeling was that everyone just wanted it to be over. And now it is over, except for all those damn retrospectives. So, with the risk of opening up some old wounds I would like to take a look at what happened last year in my corner of the free and open source silicon world.In the 2020 retrospective I wrote about a couple of big milestones, like the ...

El Correo Libre Issue 47

by Gareth Halfacree on LibreCores - Medium
teaser image Cocotb Refresh Finally Explains how to Best Place a Coconut Tree on a DeskCocotb, the Python-based coroutine cosimulation test bench hardware verification framework, has unveiled a fully-overhauled website — together with its first-ever official logo. The new website, available now at www.cocotb.org, provides an entry point for users and not-yet-users of cocotb alike, featuring content like a three-point quick-start guide, a list of key benefits of cocotb, and a section offering a look at ...

RISC-V is Ready for Great Challenges

by Chris Jones on SiFive
teaser image SiFive joins the Intel Foundry Services IP Alliance program to broadly enable innovative new computing platforms In 2021, SiFive evolved our industry-leading RISC-V portfolio of processor IP into three families, each with a focused purpose. The SiFive Essential™, SiFive Performance™, and SiFive Intelligence™ families leverage the expertise of our company founders who created RISC-V and our talented engineers to build products that will address the entire semiconductor industry, from ...

Intel Corporation Makes Deep Investment in RISC-V Community to Accelerate Innovation in Open Computing

by Kim McMahon on Announcements Archives - RISC-V International
RISC-V welcomes Intel to the Board of Directors to collaborate on RISC-V IP and contribute engineering expertise to accelerate RISC-V software development ZURICH – February 7, 2022 – RISC-V International, the global open hardware standards organization, today announced that Intel Corporation, creating world-changing technology that enables global progress and enriches lives, has joined RISC-V International at the Premier membership level. This move ...

RISC-V RV32I J-Type | Maven Silicon

by Maven Silicon on Blog Archives - RISC-V International
This video explains the RV32I J-Type instructions.  RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. The post RISC-V RV32I J-Type | Maven Silicon appeared first on RISC-V International.

Semico Research’s New Report Predicts There Will Be 25 Billion RISC-V-Based AI SoCs By 2027 | Rich Wawrzyniak, Semico Research Corporation

by RISC-V Community News on Blog Archives - RISC-V International
teaser image Research underscores current RISC-V architecture momentum, emphasizing impressive growth in consumer, enterprise and communication markets   RISC-V is leading the open era of computing across consumer and enterprise markets. In Semico Research’s latest report focusing particularly on artificial intelligence (AI) implementations, “Analyzing the RISC-V CPU Market for SIP, SoCs, AI and Design Starts” (CC330-21), the firm predicts that current investment in the RISC-V architecture will continue ...

Open source FPGA platform for Rowhammer security testing in the data center | Antmicro

by Antmicro on Blog Archives - RISC-V International
teaser image Our work together with Google and the world’s research community on detecting and mitigating the Rowhammer problem in DRAM memories has been proving that the challenge is far from being solved and a lot of systems are still vulnerable. The DDR Rowhammer testing framework that we developed together with an open hardware LPDDR4 DRAM tester board has been used to detect new attack methods such as Half-Double and Blacksmith and all data seems to suggest this more such methods will be discovered ...

OTA: X-Band Beams Images from Space, SDR-based Malware Detection, srsRAN Tutorial, and More

by Gareth Halfacree on MyriadRF
Arved Viehweger is among a growing number of LimeSDR users turning their attention to X-Band satellite communications – receiving impressive high-resolution imagery from Russia’s ARKTIKA-M1 satellite. Launched in February 2021 as the first in the ARKTIKA constellation and serving as an Arctic monitoring system, ARKTIKA-M1 transmits at the lower end of the X-Band – out of range of most affordable software-defined radio systems, but receivable with a suitable downconverter capable of shifting ...

Alibaba Cloud Opens Up IoT Technology Development Platform | Wang Cindy, Alibaba Cloud

by RISC-V Community News on Blog Archives - RISC-V International
Alibaba Cloud, the digital technology and intelligence backbone of Alibaba Group, announced it has opened the source code of Yun on Chip (YoC), its proprietary full-stack technology development platform for IoT devices. This initiative follows the company open-sourcing the XuanTie IP core series – the custom-built processors based on RISC-V instruction-set architecture – in October this year.   “This announcement is further proof of our continuous support for the RISC-V software ecosystem ...

Documenting SystemVerilog with Sphinx

by Matthew Ballance on Bits, Bytes, and Gates
I've been digging into a project over the last few months whose value proposition is to simplify the process of connecting simulation-like environments and things like reference models, testbench languages, etc. I'll write more (likely much more) about this project in the future. This post, however, is about documentation and, specifically, documentation for SystemVerilog code.As you can imagine,

Google Research Releases Circuit Training, an Open-Source Framework for Automated Chip Floorplanning

by Gareth Halfacree on FOSSi Archives - AB Open
Google Research has released the source code for a chip floor-plan generate based on deep reinforcement learning – after publishing a paper demonstrating how effective the approach could be in April last year. “Chip floorplanning is the engineering task of designing the physical layout of a computer chip,” the research team explained in the abstract to their paper. “Despite five decades of research, chip floorplanning has defied automation, requiring months of intense effort by physical ...

The Rapid Rise of RISC‑V

by Jack Kang on SiFive
teaser image SiFive is aiming high with bold new technology for performance-driven applications SiFive transformed in 2021 and grew from leading RISC-V for embedded products into performance-demanding markets, creating real choice in the semiconductor processor IP market. Now, the SiFive portfolio features three distinct, market-focused product families, based on market requirements ranging from high-performance applications, machine learning and artificial intelligence processing, to embedded real-time ...

RISC-V RV32I S-Type | Maven Silicon

by Maven Silicon on Blog Archives - RISC-V International
This video explains the RV32I S-Type instructions.  RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. C-V RV32I S-Type | Maven Silicon The post RISC-V RV32I S-Type | Maven Silicon appeared first on RISC-V International.

El Correo Libre Issue 46

by Gareth Halfacree on LibreCores - Medium
teaser image Incredible Hack Implements a CPU in a Modular Analogue SynthBuilding a CPU out of discrete digital logic is a right-of-passage for many in the world of free and open source silicon and open hardware, but engineer Kate F. has gone a step further — building a functional CPU using an analogue modular synth. “I’m using VCV Rack. It’s software simulation for Eurorack modular synthesisers, either in conjunction with, or in place of hardware modules,” Kate explains of the project. “You know the ...

Edalize 0.3.0

by Olof Kindgren on Tales from Beyond the Register Map
teaser image  Looks like it's time for a new Edalize release. During this development cycle, most of the work has been done under the hood with creating a new internal architecture and refactoring many of the backends. Most of those efforts will bear fruit longer term, but we can already today see the initial work on the flow API, that has been planned for at least two years. We also welcome a new backend for Lattice Nexus devices and some miscellaneous feature additions and bug fixes. Read on for the ...

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Last updated 26 June 2022 13:30 UTC