Planet LibreCores

MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability | MIPS

by RISC-V Community News on Blog Archives - RISC-V International
teaser image MIPS previews the first IP solutions in the eVocore product lineup: P8700 and I8500 multiprocessors. SAN JOSE, Calif., May 10, 2022 /PRNewswire/ — MIPS, a leading developer of highly scalable RISC processor IP, announces its entrance to the RISC-V market, previewing the first products in its eVocore product lineup. The new eVocore P8700 and I8500 multiprocessor IP cores are the first MIPS products based on the RISC-V open instruction set architecture (ISA) standard. ...

El Correo Libre Issue 50

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image RISC-V Architecture Profiles v0.6 Published “For Discussion Only” The first formal releases of the RISC-V Profiles specification, v0.5 and v0.6, have been published - but its authors warn that it is “for discussion only,” and “is likely to change substantially” between now and official standardisation. “RISC-V was designed to provide a highly modular and extensible instruction set, and includes a large and growing set of standard extensions,” the authors of the RISC-V Profiles ...

OTA: LiteX SoC on the LimeSDR Mini 2.0, DMR on the LimeNET Micro, M17 on LimeSDR, and More

by Gareth Halfacree on MyriadRF
The team at Enjoy Digital has been testing out the upcoming LimeSDR Mini 2.0, and has already turned it into a self-contained computer through the porting of the open-source LiteX system-on-chip to the on-board FPGA — using a fully-open toolchain. Announced last month, the LimeSDR Mini 2.0 is designed to replace the existing LimeSDR Mini design – primarily as a means of working around ongoing shortages in the original model’s FPGA, but handily providing an opportunity increase the resources ...

E4 Computer Engineering joins RISC-V International | E4 Computer Engineering

by RISC-V Community News on Blog Archives - RISC-V International
The company aims to promote the development and application of the RISC-V open standard in ecosystems for HPC applications.   Scandiano (RE), May 3rd 2022 – E4 Computer Engineering (E4) has officially joined RISC-V International (RISC-V), which promotes the development of an ISA (Instruction set architecture) based on open source principles. E4 thus joins companies such as Google, NVIDIA, Qualcomm, IBM and Samsung, among the numerous members of RISC-V and will contribute to the development ...

RISC-V Open Era of Computing – A Conversation with Calista Redmond and Mr. Sivakumar P R , Founder and CEO of Maven Silicon | Maven Silicon

by Maven Silicon on Blog Archives - RISC-V International
India’s top VLSI Training Services company Maven Silicon, a RISC-V Global Training Partner, conducted an insightful discussion with the industry experts Ms. Calista Redmond, CEO, RISC-V International and Mr. Sivakumar P R, CEO, Maven Silicon, on the topic “RISC-V Open Era of Computing”. To introduce RISC-V, it is a free and open ISA, enabling processor, hardware, and software innovations through open collaboration. Maven Silicon’s vision is to produce highly skilled VLSI engineers and help ...

Join us in the classroom! Put RISC-V into your Computer Architecture course using RVfpga! | Robert C.W. Owen, Imagination Technologies

by RISC-V Community News on Blog Archives - RISC-V International
teaser image Dear Professors and Friends, Online is convenient and it has saved us during the pandemic, but you can’t beat in-person class!  That immersive feeling of hands-on and the shared mission with colleagues all trying to master the same subject We are at the start of a global series of workshops to “train the teachers” how to use RISC-V in computer architecture courses and the design of systems on chip (SoCs). We are starting in the USA, then in Europe and then across Asia. Our RVfpga partners, ...

Alibaba Cloud Tops MLPerf Tiny v0.7 Benchmark | Alibaba Cloud

by RISC-V Community News on Blog Archives - RISC-V International
teaser image Alibaba Cloud’s Xuantie C906 processor attained firsts in the most recent findings from MLPerf Tiny v0.7, an AI benchmark focusing on IOT devices. The Xuantie C906’s performance excelled in all four core categories – visual wake words, image classifications, keyword spotting, and anomaly detection. The Xuantie C906 is Alibaba’s custom-built processor based on the RISC-V instruction-set architecture. Xuantie C906’s remarkable performance marks a milestone that showcases the potential of the ...

Xuantie IOMMU from T-Head for RISC-V | Chong Ren, Alibaba Cloud

by RISC-V Community News on Blog Archives - RISC-V International
The recent development of the RISC-V IOMMU effort has attracted substantial attention from the RISC-V community. Xuantie IOMMU from T-Head Semiconductors of Alibaba Group, holding one of the five independent proposals, features a design that is in sync with the current IOMMU Task Group’s charter. An Input / Output Memory Management Unit (IOMMU), analogous to the Memory Management Unit (MMU) in a CPU, is used to regulate the access to main memory by peripheral devices in a computer system. ...

El Correo Libre Issue 49

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image VeriGPU is a Permissively-Licensed ML GPU Core, “Loosely Based” on RISC-V Machine learning researcher Hugh Perkins is working on a project to create an open-source graphics processing unit (GPU), with a view to being able to produce a physical chip suitable for acceleration of machine-learning workloads. “I don’t actually intend to tape this out myself,” Hugh explains, “but I intend to do what I can to verify somehow that tape-out would work OK, timings OK, etc.” The VeriGPU - short for ...

Apply Now For GSoC 2022!

by FOSSi Foundation on FOSSi Foundation - News & Posts
We have once again been selected as a mentor organisation for Google Summer of Code (GSoC) 2022. Google Summer of Code is an excellent program for new open-source contributors to receive a stipend (generously provided by Google) to contribute to open source projects in the FOSSi community. As an organisation, we encompass a variety of community projects in the space of open source silicon design, EDA tools, and the surrounding ecosystem. For those previously familiar with the program, ...

Mi-V Ecosystem Partner Solutions | Leah Iris, Microchip

by RISC-V Community News on Blog Archives - RISC-V International
teaser image The Mi-V RISC-V ecosystem is a continuously expanding, comprehensive suite of tools and design resources developed by Microchip and numerous third parties to fully support RISC-V designs. The Mi-V ecosystem aims to increase adoption of the RISC-V Instruction Set Architecture (ISA) and Microchip’s PolarFire® SoC FPGA and RISC-V soft CPU portfolio. System on Modules (SoMs) Available as Ready-to-Use PolarFire® FPGA Building Blocks ARIES Embedded is one of our Mi-V ecosystem partners. Using ...

XuanTie VirtualZone: RISC-V-based Security Extensions | Xuan Jian, Alibaba Cloud

by RISC-V Community News on Blog Archives - RISC-V International
teaser image Introduction Among many new things in the 21st century, internet and IoT have been one of the most significant human advancements. As fast-paced and accelerating as they evolve, needs for the number of connected devices are increasing substantially as a result. The “Internet of Everything” has become the new future global networks. While the explosive growth of mobile platform usage have enabled successful business transactions, various concerns of security breach arise inevitably. Most ...

TbLink-RPC: Simplifying the Multi-Language Testbench

by Matthew Ballance on Bits, Bytes, and Gates
SystemVerilog/UVM is, by far, the most widely-used language and methodology for block and subsystem-level verification environments today. The simplicity of that statement overlooks the fact that it’s often very common to have other bits of non-SystemVerilog code connected. Maybe it’s some C/C++ code that implements a reference algorithm used by the scoreboard. Maybe it’s an instruction-set

Efabless’ CLEAR, a Fully-Open RISC-V ASIC Built on chipIgnite, Nears its Goal with Days to Go

by Gareth Halfacree on FOSSi Archives - AB Open
CLEAR, a fully-open development board built around a RISC-V embedded-FPGA application-specific integrated circuit (ASIC) designed by Efabless as a showcase of what its chipIgnite platform can offer, is entering the last days of its crowdfunding campaign with just a handful of boards left to reach its goal. “CLEAR is an open source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it,” Efabless ...

OTA: LimeSDR Mini 2.0, Project CAMARA, a Commercial LimeNET Base Station Call, and More

by Gareth Halfacree on MyriadRF
Lime Microsystems has announced the LimeSDR Mini 2.0, an upgraded version of the smallest member of the LimeSDR range featuring a considerably improved field-programmable gate array (FPGA) – boosting its flexibility. Since its launch in 2017, the LimeSDR Mini – a single-channel full-duplex software defined radio built on the same Lime Micro LMS7002M as the LimeSDR USB – has found a home in a wealth of projects not requiring dual-channel operation. Ongoing supply chain issues, however, have ...

RISC-V RV32I JALR Instruction | Maven Silicon

by Maven Silicon on Blog Archives - RISC-V International
This video explains the RV32I JALR instruction. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. Watch the full video.  The post RISC-V RV32I JALR Instruction | Maven Silicon appeared first on RISC-V International.

Ten Reasons to use SiliconCompiler – Including SPDX Provenance Support

by Gareth Halfacree on FOSSi Archives - AB Open
Zero ASIC’s chief executive Andreas Olofsson has called for “all chip designers” to try out the open-source SiliconCompiler build system, showcasing his top ten reasons for giving it a go – including a provenance feature which supports the Software Package Data Exchange (SPDX) standard. “We have been working hard on our open source SiliconCompiler build system for a year now and it’s coming together really nicely,” says Olofsson. “I have been doing chip design and CAD development since 1998 ...

El Correo Libre Issue 48

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image CHIPS Alliance Forms F4PGA Workgroup for Open-Source FPGA Tooling The CHIPS Alliance has announced the formation of the FOSS Flow For FPGA Workgroup, also known as F4PGA, through which it aims to drive open-source tooling, intellectual properties, and research efforts focused on field-programmable gate arrays (FPGAs). “FPGAs are essential for a wide variety of low-latency compute use cases, from telecoms to space applications and beyond. This new F4PGA toolchain will enable a ...

OTA: ADS-B Tracking at the Terminal, Open RAN Silicon, Beginner’s Guides, and More

by Gareth Halfacree on MyriadRF
Developer Wayne Campbell has released version 0.5.1 of rsadsb, a Rust-based ADS-B aircraft tracking system with a text-mode user interface — bringing with it its first support for LimeSDR devices. “Release v0.5.0 of rsadsb is now released,” Wayne writes of the launch. “Use any SDR supported by SoapySDR. If any HackRF or LimeSDR users want to try my software, MR welcome with gain values!” Rsadsb is a a collection of utilities, written in Rust and released under an open-source licence, ...

OpenRISC support added to GLIBC 2.35

by OpenRISC Community on OpenRISC
We would like to announce that GLIBC 2.35 released in February 2022 has support for OpenRISC. Read more about GLIBC toolchain support support over on our software page.

FOSSi Explosion 2021 | Olof Kindgren, FOSSi Foundation and Qamcom

by Olof Kindgren on Blog Archives - RISC-V International
teaser image Do you know what just happened? 2021 just happened. Most years has its ups and downs, but when it comes to 2021 it seems like the prevalent feeling was that everyone just wanted it to be over. And now it is over, except for all those retrospectives. So, with the risk of opening up some old wounds I would like to take a look at what happened last year in my corner of the free and open source silicon world. In the 2020 retrospective I wrote about a couple of big milestones, like the first ...

The Investment Heard Around The World

by Chris Jones on SiFive
teaser image The RISC-V revolution continues to advance as the technology industry embraces open computing to address semiconductor design and business challenges Last week saw momentous announcements, with Intel Foundry Services (IFS) enabling RISC-V alongside other processor architectures as part of Intel’s dedication to an open ecosystem and to help make IFS become one of the world’s leading foundries. By joining RISC-V International and investing significant money and resources in the open ...

FOSSi Explosion 2021

by Olof Kindgren on Tales from Beyond the Register Map
teaser image  Do you know what just happened? 2021 just happened. Most years has its ups and downs, but when it comes to 2021 it seems like the prevalent feeling was that everyone just wanted it to be over. And now it is over, except for all those damn retrospectives. So, with the risk of opening up some old wounds I would like to take a look at what happened last year in my corner of the free and open source silicon world.In the 2020 retrospective I wrote about a couple of big milestones, like the ...

El Correo Libre Issue 47

by Gareth Halfacree on LibreCores - Medium
teaser image Cocotb Refresh Finally Explains how to Best Place a Coconut Tree on a DeskCocotb, the Python-based coroutine cosimulation test bench hardware verification framework, has unveiled a fully-overhauled website — together with its first-ever official logo. The new website, available now at www.cocotb.org, provides an entry point for users and not-yet-users of cocotb alike, featuring content like a three-point quick-start guide, a list of key benefits of cocotb, and a section offering a look at ...

RISC-V is Ready for Great Challenges

by Chris Jones on SiFive
teaser image SiFive joins the Intel Foundry Services IP Alliance program to broadly enable innovative new computing platforms In 2021, SiFive evolved our industry-leading RISC-V portfolio of processor IP into three families, each with a focused purpose. The SiFive Essential™, SiFive Performance™, and SiFive Intelligence™ families leverage the expertise of our company founders who created RISC-V and our talented engineers to build products that will address the entire semiconductor industry, from ...

Intel Corporation Makes Deep Investment in RISC-V Community to Accelerate Innovation in Open Computing

by Kim McMahon on Announcements Archives - RISC-V International
RISC-V welcomes Intel to the Board of Directors to collaborate on RISC-V IP and contribute engineering expertise to accelerate RISC-V software development ZURICH – February 7, 2022 – RISC-V International, the global open hardware standards organization, today announced that Intel Corporation, creating world-changing technology that enables global progress and enriches lives, has joined RISC-V International at the Premier membership level. This move ...

RISC-V RV32I J-Type | Maven Silicon

by Maven Silicon on Blog Archives - RISC-V International
This video explains the RV32I J-Type instructions.  RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. The post RISC-V RV32I J-Type | Maven Silicon appeared first on RISC-V International.

Semico Research’s New Report Predicts There Will Be 25 Billion RISC-V-Based AI SoCs By 2027 | Rich Wawrzyniak, Semico Research Corporation

by RISC-V Community News on Blog Archives - RISC-V International
teaser image Research underscores current RISC-V architecture momentum, emphasizing impressive growth in consumer, enterprise and communication markets   RISC-V is leading the open era of computing across consumer and enterprise markets. In Semico Research’s latest report focusing particularly on artificial intelligence (AI) implementations, “Analyzing the RISC-V CPU Market for SIP, SoCs, AI and Design Starts” (CC330-21), the firm predicts that current investment in the RISC-V architecture will continue ...

Open source FPGA platform for Rowhammer security testing in the data center | Antmicro

by Antmicro on Blog Archives - RISC-V International
teaser image Our work together with Google and the world’s research community on detecting and mitigating the Rowhammer problem in DRAM memories has been proving that the challenge is far from being solved and a lot of systems are still vulnerable. The DDR Rowhammer testing framework that we developed together with an open hardware LPDDR4 DRAM tester board has been used to detect new attack methods such as Half-Double and Blacksmith and all data seems to suggest this more such methods will be discovered ...

OTA: X-Band Beams Images from Space, SDR-based Malware Detection, srsRAN Tutorial, and More

by Gareth Halfacree on MyriadRF
Arved Viehweger is among a growing number of LimeSDR users turning their attention to X-Band satellite communications – receiving impressive high-resolution imagery from Russia’s ARKTIKA-M1 satellite. Launched in February 2021 as the first in the ARKTIKA constellation and serving as an Arctic monitoring system, ARKTIKA-M1 transmits at the lower end of the X-Band – out of range of most affordable software-defined radio systems, but receivable with a suitable downconverter capable of shifting ...

Alibaba Cloud Opens Up IoT Technology Development Platform | Wang Cindy, Alibaba Cloud

by RISC-V Community News on Blog Archives - RISC-V International
Alibaba Cloud, the digital technology and intelligence backbone of Alibaba Group, announced it has opened the source code of Yun on Chip (YoC), its proprietary full-stack technology development platform for IoT devices. This initiative follows the company open-sourcing the XuanTie IP core series – the custom-built processors based on RISC-V instruction-set architecture – in October this year.   “This announcement is further proof of our continuous support for the RISC-V software ecosystem ...

Documenting SystemVerilog with Sphinx

by Matthew Ballance on Bits, Bytes, and Gates
I've been digging into a project over the last few months whose value proposition is to simplify the process of connecting simulation-like environments and things like reference models, testbench languages, etc. I'll write more (likely much more) about this project in the future. This post, however, is about documentation and, specifically, documentation for SystemVerilog code.As you can imagine,

Google Research Releases Circuit Training, an Open-Source Framework for Automated Chip Floorplanning

by Gareth Halfacree on FOSSi Archives - AB Open
Google Research has released the source code for a chip floor-plan generate based on deep reinforcement learning – after publishing a paper demonstrating how effective the approach could be in April last year. “Chip floorplanning is the engineering task of designing the physical layout of a computer chip,” the research team explained in the abstract to their paper. “Despite five decades of research, chip floorplanning has defied automation, requiring months of intense effort by physical ...

The Rapid Rise of RISC‑V

by Jack Kang on SiFive
teaser image SiFive is aiming high with bold new technology for performance-driven applications SiFive transformed in 2021 and grew from leading RISC-V for embedded products into performance-demanding markets, creating real choice in the semiconductor processor IP market. Now, the SiFive portfolio features three distinct, market-focused product families, based on market requirements ranging from high-performance applications, machine learning and artificial intelligence processing, to embedded real-time ...

RISC-V RV32I S-Type | Maven Silicon

by Maven Silicon on Blog Archives - RISC-V International
This video explains the RV32I S-Type instructions.  RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses. C-V RV32I S-Type | Maven Silicon The post RISC-V RV32I S-Type | Maven Silicon appeared first on RISC-V International.

El Correo Libre Issue 46

by Gareth Halfacree on LibreCores - Medium
teaser image Incredible Hack Implements a CPU in a Modular Analogue SynthBuilding a CPU out of discrete digital logic is a right-of-passage for many in the world of free and open source silicon and open hardware, but engineer Kate F. has gone a step further — building a functional CPU using an analogue modular synth. “I’m using VCV Rack. It’s software simulation for Eurorack modular synthesisers, either in conjunction with, or in place of hardware modules,” Kate explains of the project. “You know the ...

Edalize 0.3.0

by Olof Kindgren on Tales from Beyond the Register Map
teaser image  Looks like it's time for a new Edalize release. During this development cycle, most of the work has been done under the hood with creating a new internal architecture and refactoring many of the backends. Most of those efforts will bear fruit longer term, but we can already today see the initial work on the flow API, that has been planned for at least two years. We also welcome a new backend for Lattice Nexus devices and some miscellaneous feature additions and bug fixes. Read on for the ...

Edge AI on Low-Footprint RISC-V | Alexander Stanitzki, Fraunhofer IMS

by RISC-V Community News on Blog Archives - RISC-V International
teaser image The integration of AI algorithms on end devices (“Edge AI”, “AI of Things”, TinyML,..)  is conquering the domain of resource constrained microcontrollers and cost-efficient ASIC designs. AI can improve the performance of basic sensors, helps to achieve light-weight object recognition and tracking in optical detectors and can be useful for HMI functions such as handwriting recognition. RISC-V makes it possible to quickly develop new hardware architectures to support these applications even ...

OTA: LimeSDR’s Part in the UK’s Open RAN Plans, an Open-Source ARDF Controller, a “Widowmaker” Radio, and More

by Gareth Halfacree on MyriadRF
The UK government has announced a target of carrying 35 per cent of all cellular traffic over open radio access networks (open RANs) by 2030, alongside the planned retirement of 2G and 3G cellular – and LimeSDR technology has been selected for two key test-bed projects. “The mobile network operators have confirmed that they do not intend to offer 2G and 3G mobile networks past 2033 at the latest,” the Department for Digital, Culture, Media, and Sport (DCMS) said in a statement on the ...

When You Reach The Summit, Keep Climbing

by Andy Frame on SiFive
teaser image The RISC-V Summit 2021 highlighted to the world that the future of RISC-V has no limits! 2021 has been an outstanding year for SiFive, and the biggest in its history, starting with the introduction of the AI/ML focused SiFive Intelligence™ and high performance SiFive Performance™ series of processors and culminating with the announcement of the SiFive Performance P650 and latest SiFive 21G3 release as part of the RISC-V Summit 2021. Specifications In parallel, RISC-V International has ...

El Correo Libre Issue 45

by Gareth Halfacree on LibreCores - Medium
teaser image Test Bench Environment cocotb Gets Bug-Fix 1.6.1 ReleaseOctober’s release of cocotb 1.6.0, the at-the-time latest version of the popular coroutine-based cosimulation test bench environment for VHDL and Verilog RTL, brought with it a wealth of improvements and new features — and one annoying regression bug, which has now been resolved in version 1.6.1. Released earlier this month, cocotb 1.6.1 has all the same features as 1.6.0 — including the new C-to-Python PYGPI_ENTRY_POINT, the ...

Our New Partnership with Rambus and the DesignShare Economy

by Jack Kang on SiFive
teaser image As we continue to expand our product offerings to better serve the rapidly growing RISC-V and SiFive community, we are always looking to work with companies (big and small) who share our vision. On Monday, we proudly announced that we will form a new partnership with Rambus, a leader in the digital security, semiconductor and IP industries, to help us take the next step in democratizing access to custom silicon. Through the partnership, we will be able to offer Rambus’ cryptography ...

All Aboard, Part 4: The RISC-V Code Models

by Palmer Dabbelt on SiFive
teaser image The RISC-V ISA was designed to be both simple and modular. In order to achieve these design goals, RISC-V minimizes one of the largest costs in implementing complex ISAs: addressing modes. Addressing modes are expensive both in small designs (due to decode cost) and large designs (due to implicit dependencies). RISC-V only has three addressing modes: PC-relative, via the auipc, jal and br* instructions. Register-offset, via the jalr, addi and all memory instructions. Absolute, via the lui ...

Interrupts on the SiFive E2 Series

by Drew Barbier on SiFive
teaser image Last week SiFive launched the new E2 Series RISC-V Core IP. The E2 Series represents SiFive’s smallest, most efficient Core IP Series and is targeted specifically for embedded microcontroller designs. One of the reasons it is great for microcontroller applications is because of its extremely small area footprint, just 0.023mm2 in 28nm for the entire E20 Standard Core! Another reason it's great for the embedded market is its configurability. The E2 Series can be configured even smaller than ...

The DesignShare Ecosystem Expands Its Catalog of IP to include eMemory’s Logic NVM

by Jack Kang on SiFive
teaser image It’s been a fantastic few months for us with new initiatives and industry recognitions, and we’re excited to share more great news. Earlier this month, we welcomed eMemory, the IP provider of logic-based, non-volatile memory (Logic NVM), as the latest company to join the DesignShare movement! If you missed our previous blog post, DesignShare is a concept that opens a new range of applications and gives any company, inventor or maker the ability to harness the power of custom silicon. The ...

What’s new in AI & ML from SiFive

by Patrick Little on SiFive
teaser image Introducing the SiFive Intelligence X280 This week has been an exciting one for our team at SiFive, with a number of key announcements that are beginning to allow us to publicly share our strategy for the exponentially growing AI/ML market. While we are only scratching the surface of the impact AI/ML will have on our industry and our lives, it’s clear that the workloads, algorithms, and requirements are going to be constantly evolving and improving for the foreseeable future. These changing ...

Dover Microsystems Brings Real-Time Chip Security to SiFive’s DesignShare

by Shafy Eltoukhy on SiFive
teaser image Boy have we been busy. Over the last few months, our DesignShare ecosystem has continued to expand, and, this week, we were excited to welcome Dover Microsystems into the program. Through DesignShare, developers now have access to Dover Microsystems’ CoreGuard Silicon IP, which enables processors to defend themselves in real-time from all network-based attacks. CoreGuard prevents illegal instructions from executing before any damage can be done. Its security rules define the difference ...

Intel Capital Investment Boosts Vision for the Future

by Naveed Sherwani on SiFive
teaser image We’re very happy to announce that Intel Capital participated in our recent Series C funding round. The investment was revealed at the Intel Capital Global Summit earlier today. Now, you may be thinking, “$50.6 million provides immense potential for SiFive – so now what?” For those of you who aren’t familiar with what SiFive is all about, we aim to leverage the body of software and tools available from the open-source community under the guidance of the RISC-V Foundation with the intention ...

All Aboard, Part 11: RISC-V Hackathon, Presented by SiFive

by Palmer Dabbelt on SiFive
teaser image Date: Monday, March 12 – Wednesday, March 14 Time: 10:30am Monday – 1:00pm Wednesday Location: Embedded Linux Conference, Hilton Portland Downtown, Skyline II, Floor 23 UPDATE 2 (3/7/2018) We’ve doubled the cash prize to $2,000 for each challenge! Plus we’ve added a “coolest demo” category, with the same prize package as the other challenges (a HiFive Unleashed board plus the $2,000). You can register for the Hackathon here. UPDATE (3/7/2018) We've seen a lot of interest in the RISC-V ...

Last Week in RISC-V: Sept 7, 2018

by Palmer Dabbelt on SiFive
teaser image This is the last version of "Last Week in RISC-V" that I plan on sending to the various mailing lists, as we'll be posting the rest of them on SiFive's Blog. I didn't get any contributions, but I also haven't gotten through my email yet -- sorry if I missed anything that's been sent it, but I'm not too far behind so I should have everything read from this week by the end of next week. Linux 4.19-rc3 On Tuesday I tagged my pull request for Linux 4.19-rc3, which contains what I hope to be ...

The DesignShare Ecosystem Grows with the Addition of UltraSoC’s Embedded Analytics IP

by Jack Kang on SiFive
teaser image It’s been a busy summer for us. Our days have been filled with many prospect, customer and partner meetings with teams looking to leverage RISC-V in their roadmap. Last week, we announced the outcome of one of those meetings: UltraSoC, a provider of on-chip monitoring and analytics IP, is the latest company to join the DesignShare movement. If you missed our previous blog post, 'Our New Partnership with Rambus and the DesignShare Economy,' Designshare is a concept that enables an entirely ...

Analog Bits Clocks into the DesignShare Ecosystem

by Jack Kang on SiFive
teaser image Our DesignShare family is growing, and we’re thrilled to announce that Analog Bits, the industry’s leading provider of low-power mixed-signal IP solutions, is now a part of the ecosystem. System designers will have access to Analog Bits’ precision clocking macros such as PLLs and SERDES IP available for the SiFive Freedom platforms through DesignShare. Analog Bits has become an important supplier of differentiated IP embedded in SoC devices and has been instrumental in spawning the mobile ...

A Core By Any Other Name...

by Jack Kang on SiFive
teaser image With all apologies to Shakespeare, would a core by any other name still hit the sweet spot in the market for those looking for cost-effective custom silicon? Based on feedback from some friendly chaps in the industry, today we are announcing a new naming scheme for our products. We’ve updated our product names to reflect that we build and provide IP for RISC-V cores--and not any other ISA. To ease the transition, we’ve kept part numbers – like the U54-MC unveiled last week at the Linley ...

All Aboard, Part 9: Paging and the MMU in the RISC-V Linux Kernel

by Palmer Dabbelt on SiFive
teaser image This entry will cover the RISC-V port of Linux's memory management subsystem. Since the vast majority of the memory management code in Linux is architecture-independent, the vast majority of our memory management code handles interfacing with our MMU, defining our page table format, and interfacing with drivers that have memory allocation constraints. I will refrain from discussing the RISC-V memory model in this blog, both because it isn't yet finished and because it's complicated ...

A Look Back: 7th RISC-V Workshop

by Allen Leibovitch on SiFive
teaser image A new year brings new opportunities. Before we dive into 2018, we wanted to take some time to reflect on some of the excitement we experienced over the last couple of months. At the 7th RISC-V Workshop, we had the honor of partnering with some of the industry’s leading companies and announced the following at the workshop: An extended partnership with Microsemi: Microsemi and SiFive formed a strategic partnership to create and market a development board based on SiFive’s RISC-V based ...

Last Week in RISC-V: Sept 28, 2018

by Palmer Dabbelt on SiFive
teaser image I spent too much time writing my single entry this week so it's all I have. The issue itself is somewhat complex, so I thought it warranted a deep dive. Relaxing R_RISCV_PCREL_* in the Presence of Addends Jim recently found an issue with our ELF relocation scheme. While technically it's a somewhat wide-ranging ABI bug, the actual set of cases in which the issue will manifest is somewhat restricted -- in other words: while I'm sure the proper long-term fix for this will be quite involved, ...

All Aboard, Part 3: Linker Relaxation in the RISC-V Toolchain

by Palmer Dabbelt on SiFive
teaser image Last week's blog entry discussed relocations and how they apply to the RISC-V toolchain. This week we'll be delving a bit deeper into the RISC-V linker to discuss linker relaxation, a concept so important it has greatly shaped the design of the RISC-V ISA. Linker relaxation is a mechanism for optimizing programs at link-time, as opposed to traditional program optimization which happens at compile-time. This blog will follow an example linker relaxation through the toolchain, demonstrate an ...

Last Week in RISC-V: Sept 14, 2018

by Palmer Dabbelt on SiFive
teaser image GNU Tools Cauldron Trip Report, Part 2 I was at the GNU tools cauldron last week. I summarized the two BoF sessions in last week's entry. While that was the extent of the RISC-V specific events at the cauldron, I attended the remainder of the cauldron where there were some great sessions. Vector ABI I attended the aarch64 BoF session, where one of the major issues at hand is to implement a system ABI that allows argument passing via SVE registers. This brought up a mirror in RISC-V land: ...

Introducing the U54-MC RISC-V Core IP – The First RISC-V Core with Linux Support

by Jack Kang on SiFive
teaser image Since we launched the industry’s first open-source RISC-V SoC back in July of last year, we’ve had the pleasure of pushing the boundaries of the RISC-V ecosystem and have been delighted by the support that SiFive – and RISC-V – has gained from system designers and Makers alike. Today, we are proud to announce we have taken the next step in our journey to deliver custom silicon to everyone who needs it. Introducing the U54-MC RISC-V Core IP, the industry’s first RISC-V based, 64-bit, ...

All Aboard, Part 6: Booting a RISC-V Linux Kernel

by Palmer Dabbelt on SiFive
teaser image This post begins a short detour into Linux land, during which we'll be discussing the RISC-V Linux kernel port. SiFive has recently announced the Linux-capable U54-MC RISC-V Core IP, and our Linux port was recently submitted to linux-next, Linux's staging branch, so assuming that everything goes smoothly we should be merged at the end of the next merge window. Along with Linux we should soon have the full suite of core system components upstream, both for embedded systems (via binutils, ...

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Last updated 22 May 2022 00:30 UTC