Planet LibreCores

OTA: LimeSDR Shipping, 6G Cellular, New Osmocom, and More

by Gareth Halfacree on Myriad
Work to deliver outstanding LimeSDR, LimeSDR Mini, and associated devices continues, but there’s been a major change in the background: Crowd Supply is now in full control of inventory management and distribution, which is going to make future fulfilment considerably smoother at the cost of a moderate delay in the short term. “Up until now, we’ve been manufacturing LimeSDR products in fits and starts in order to efficiently allocate resources to meet demand in close to real time. While ...

CRU: HiFive Expansion, Computer Vision, Osmocom, and More

by Gareth Halfacree on FOSSi – AB Open
AB Open and its hardware division Ground Electronics have launch a campaign for Circumference, a family of custom-designed desktop cluster computing units based around the popular Raspberry Pi and UDOO x86 single-board computer families. Available to pre-order now on crowdfunding site Crowd Supply, the Circumference C25 boasts support for up to eight Raspberry Pi computers while the Circumference C100 can hold up to 32 giving it a total maximum capacity of 128 64-bit low-power Arm ...

Run-Control Debug ahead!

by Open SoC Debug on
Stop the engines! This command will be understood by Open SoC Debug soon as Shivam Aggarwal (@shivmgg) adds run-control debug support to Open SoC Debug. Run-control debug, or “stop and stare debugging” is known to many when using a debugger such as GDB to set breakpoints and inspect the program state once the executed halted. Up to now, Open SoC Debug focused on tracing, leaving this other important debugging technique on the wishlist. But not any longer. Shivam, who does this work as part ...

OTA: Python SNAs and VNAs, High-Frequency Trading, Linux Containers, and More

by Gareth Halfacree on Myriad
A new Python package, pyLMS7002Soapy, has been published as a more feature-packed replacement for the old pyLMS7002M library – bringing with it bundled examples which use the LimeSDR or LimeSDR Mini as a scalar or vector network analyser (SNA/VNA). Uploaded to the Myriad RF GitHub repository late last month the new PyLMS7002Soapy package aims to provide easy prototyping and algorithm development for Python users, based on a SoapySDR back-end. Launching with support for the LimeSDR and ...

HiFive Unleashed Gets Packed PolarFire Powered Expansion

by Andrew Back on FOSSi – AB Open
teaser image World’s first Linux-capable RISC-V development board benefits from expansion that adds PCIe, M.2 SSD, SATA, HDMI, a 300K element PolarFire FPGA, and more. Launched back in February at FOSDEM the HiFive Unleashed RISC-V development board boasts a 64-bit Freedom U540 SoC with features that include a 4+1 Multi-Core Coherent Configuration (up to 1.5 GHz), implemented in TSMC 28nm process. The development board also has 8GB DDR4 RAM, a USB UART for console, gigabit Ethernet, Micro SD storage, ...

OnChip Announces New 32-bit RISC-V Microcontroller

by Gareth Halfacree on FOSSi – AB Open
Colombia-based semiconductor specialist OnChip has announced a 32-bit RISC-V microcontroller design aimed at low-power sensor applications, developed in partnership with SiFive. Fresh from announcing the next generation of Itsy-Chipsy, the company’s low-quantity semiconductor fabrication platform which aims to allow the creation of single-unit DIP-packaged chips for around $100, OnChip has shown off the design of a new microcontroller part based on a 32-bit implementation of the RISC-V ...

Barcelona RISC-V Workshop: Day Two

by LowRISC on lowRISC
The eighth RISC-V workshop is continuing today in Barcleona. As usual, I’ll be keeping a semi-live blog of talks and announcements throughout the day. Look back here for the day one live blog. Note that slides from most presentations are now available at riscv.org. Fast interrupts for RISC-V: Krste Asanovic Embedded is a major use for RISC-V. There is a desire for faster interrupt handling with support for nested preempted interrupts. Summary of current RISC-V interrupts Local ...

RISC-V Workshop in Barcelona Proceedings

by Carmen Soh on Events – RISC-V Foundation
teaser image Proceedings for the RISC-V Workshop in Barcelona 7-10 May, 2018 Co-hosted By Co-sponsored By   Keynote sessions will include Robert Oshana, vice president of software engineering research and development at NXP, Martin Fink, executive vice president and chief technology officer at Western Digital, and Mateo Valero, director at the Barcelona Supercomputing Center. The three-day event schedule is as follows: Monday, May 7, 2018 – A half-day of tutorials from the working groups of the ...

El Correo Libre — Issue 3

by Gareth Halfacree on LibreCores - Medium
teaser image Describing himself in his Twitter profile as a hardware verification architect, Luke Valenty has become a household name among FPGA enthusiasts for one very good reason: he’s the creator of TinyFPGA, a family of low-cost accessible and open hardware field-programmable gate array (FPGA) development boards. Costing between $12 and $38 depending on capabilities, the boards have proven extremely popular among both enthusiasts taking their first steps and professional hardware engineers looking ...

Barcelona RISC-V Workshop: Day One

by LowRISC on lowRISC
The eighth RISC-V workshop is going on today in Barcleona. As usual, I’ll be keeping a semi-live blog of talks and announcements throughout the day. Follow here for the day two live blog. Note that slides from most presentations are now available at riscv.org. Introduction: Rick O’Connor This workshop has 325 attendees representing 101 companies and 25 universties. Largest outside of Silicon Valley. Rick gives the usual overview of the RISC-V Foundation structure. The RISC-V Foundation ...

Intel Capital Investment Boosts Vision for the Future

by Naveed Sherwani, Chief Executive Officer at SiFive on SiFive
We’re very happy to announce that Intel Capital participated in our recent Series C funding round. The investment was revealed at the Intel Capital Global Summit earlier today. Now, you may be thinking, “$50.6 million provides immense potential for SiFive – so now what?” For those of you who aren’t familiar with what SiFive is all about, we aim to leverage the body of software and tools available from the open-source community under the guidance of the RISC-V Foundation with the intention ...

PULP Open Silicon Project Celebrates its Fifth Birthday

by Gareth Halfacree on FOSSi – AB Open
The Parallel Ultra-Low Power (PULP) Project has celebrated its fifth birthday with a retrospective, discussing the progress made since its inception during a meeting at the University of Bologna in May 2013. “It has been exactly 5 years since Luca Benini started the PULP (Parallel Ultra Low Power) project in a meeting attended by a handful of people squeezed in a tiny office in the University of Bologna,” writes Frank K. Gurkaynak, director of the Microelectronics Design Centre at ETH ...

CRU: Homebrew Silicon, OSHCamp 2018, eSIMs Delayed, and More

by Gareth Halfacree on FOSSi – AB Open
The cause of truly home-made semiconductors hit a major milestone late last month when engineer Sam Zeloof became, to common knowledge, the first person to successfully create an integrated circuit using a fully photolithographic process in a home lab, building a dual differential amplifier using entirely homebrew equipment. Hobbyists around the world have been making discrete circuits at home for years, but integrated circuits are a significantly trickier matter. Engineers like Jeri ...

Blink Demo

by Fatsie on Chips4Makers.io
Intro In order to show the progress I made on the Retro-uC a short video is presented with a demo with the Retro-uC running on an FPGA. For the demo an Alorium XLR8, a Velleman VMA201 proto shield and a Dangerous Prototypes BusPirate V3.6 were used. On the proto shield LEDs and accompanying resistors have been soldered on the D2-D9 Arduino IOs. The Retro-uC core used has the Z80 and the MOS6502 and a JTAG interface. In the video below a demo is giving by blinking the LEDs on the proto ...

OTA: LimeSDR Cases, HDSDR and GNU Radio Support, SDR Hacks, and More

by Gareth Halfacree on Myriad
Fulfilment of the LimeSDR Mini pre-orders continues, with the optional aluminium cases for the bundles having gone through assembly and testing ready for Crowd Supply to send them on. Delivered late last week and pictured in a campaign update, the LimeSDR Mini aluminium cases are designed to provide protection for the LimeSDR Mini without obstructing any of the ports – including the reference clock input/output connectors on the underside of the printed circuit board, which remains ...

Sam Zeloof Creates First Fully Photolithographic Homebrew IC

by Gareth Halfacree on FOSSi – AB Open
Engineer Sam Zeloof has become, to common knowledge, the first person to successfully create an integrated circuit using a fully photolithographic process in a home lab, building a dual differential amplifier using entirely homebrew equipment. Hobbyists around the world have been making discrete circuits at home for years, but integrated circuits are a significantly trickier matter. Engineers like Jeri Ellsworth have succeeded in the past using conductive epoxy and other tricks for the ...

RISC-V QEMU Part 2: The RISC-V QEMU port is upstream

by Michael Clark on SiFive
QEMU 2.12.0 was released on April 24th 2018 and this version is the first official QEMU version to contain the RISC-V port. This is yet another milestone towards the development of the Open Source RISC-V tools on top of the recent acceptance of RISC-V in Linux kernel 4.15 in December last year and GLIBC 2.27 this past February. The QEMU RISC-V port was being developed and maintained out-of-tree for several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V Privileged ...

OnChip Unveils Itsy-Chipsy Ultra-Low-Cost IC Fabrication Platform

by Gareth Halfacree on FOSSi – AB Open
Colombia-based OnChip has unveiled an open-source platform which aims to do for custom semiconductor creation what services like OSH Park have done for circuit boards: Itsy-Chipsy. “Chip prototyping used to be prohibitive for small start-ups and academy until services like MOSIS brought down prices to few thousands dollars per mm² in technology nodes capable to run circuitry at moderated performance,” OnChip explains of the current state of the semiconductor art. “MOSIS runs a multi-project ...

RISC-V Foundation And Informa Announce First Annual RISC-V Summit In Silicon Valley And 2018 Workshop Schedule

by Carmen Soh on Events – RISC-V Foundation
To Support the Ecosystem’s Ongoing Growth and Increased Global Footprint, RISC-V Foundation Partners with KNect365 to Help Facilitate Events in 2018 and Beyond Berkeley, Calif. – April 23, 2018 – The RISC-V Foundation, a non-profit corporation controlled by its members to drive forward the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced, in partnership with Informa’s Knowledge & Networking Division,  KNect365, the RISC-V ...

OSHCamp 2018 Schedule Finalised and Registration Opened Up

by Gareth Halfacree on FOSSi – AB Open
The Open Source Hardware User Group (OSHUG) has announced the schedule for OSHCamp 2018, to take place in Lincoln’s The Blue Room on the 30th of June and 1st July. Announced via a call for participation back in January, the Open Source Hardware Camp (OSHCamp) 2018 is to take place in Lincoln, once home to noted engine builders Ruston & Hornsby – a company which still lives on as Siemens, following a route via GEC and English Electric. As with previous years, OSHCamp 2018 is split across two ...

CRU: Neural Networks, Open Baseband, RISC-V, and More

by Gareth Halfacree on FOSSi – AB Open
It’s been a strong fortnight for machine intelligence fans, starting with Arm’s Robert Elliot and Mark O’Conner publishing a white paper on the company’s Arm NN machine learning platform and its optimisations for use on low-power embedded devices. “We expect machine learning to become a natural part of programming environments, with tiny embedded neural networks being part of program execution,” the pair explain of the inspiration behind Arm NN. “To prepare for this, we’ve developed a ...

RISC-V Workshop in Barcelona

by Carmen Soh on Events – RISC-V Foundation
teaser image RISC-V Workshop in Barcelona 7-10 May, 2018 Co-hosted By Co-sponsored By   The RISC-V Foundation invites you to attend the RISC-V Workshop in Barcelona, Spain on 7-10 May, 2018. Co-hosted by the Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC), and co-sponsored by NXP and Western Digital, the RISC-V Workshop in Barcelona will gather the RISC-V ecosystem to share notable RISC-V updates, projects and implementations. Keynote sessions will include Robert ...

chisel 3.1.0

by Jim Lawson on Chisel
We’ve just published Chisel v3.1.0 and FIRRTL v1.1.0 and compatible updates to the rest of the BIG5 Chisel projects – chisel-testers v1.2.0, firrtl-interpreter v1.1.0, and dsptools v1.1.0. This release is essentially a copy of the RC2 candidate. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is welcome.

SeL4 Microkernel v9.0.1 Ported to RISC-V

by Gareth Halfacree on FOSSi – AB Open
The open-source seL4 microkernel, the first general-purpose kernel to have been proven to-spec using formal verification methods, has been ported to the open RISC-V instruction set architecture – though its creators warn it’s in a very early, limited form. Originally developed by Australia’s National Information and Communications Technology (ICT) Research Centre of Excellence (NICTA) and now under the stewardship of Data61’s Trustworthy Systems Group, the seL4 microkernel is a ...

Rambus Announces RISC-V CryptoManager Security Core

by Gareth Halfacree on FOSSi – AB Open
Rambus has become the latest company to adopt the open RISC-V instruction set architecture (ISA), using its openness as the basis for a new embedded and Internet of Things (IoT) security core dubbed the CryptoManager Root of Trust. “The fundamental pillars of architectural design freedom, secure processing siloed away from general processing, and layered security with a root of trust designed for multiple security layers, are unique to the CryptoManager Root of Trust design and enable easy ...

RISC-V Foundation Announces Agenda For Workshop In Barcelona

by Carmen Soh on Events – RISC-V Foundation
Workshop features more than 30 tutorials, presentations, networking receptions and a tour of the Barcelona Supercomputing Center WHAT: RISC-V Workshop in Barcelona, Spain WHERE: Universitat Politècnica de Catalunya, Campus Nord, Vertex Building Auditorium WHEN: Monday, May 7 to Wednesday, May 9, 2018 DETAILS: Co-hosted by the Barcelona Supercomputing Center and the Universitat Politècnica de Catalunya (UPC), the RISC-V Workshop in Barcelona gathers the RISC-V ecosystem to share notable ...

Dover Microsystems Brings Real-Time Chip Security to SiFive’s DesignShare

by Shafy Eltoukhy, head of DesignShare on SiFive
Boy have we been busy. Over the last few months, our DesignShare ecosystem has continued to expand, and, this week, we were excited to welcome Dover Microsystems into the program. Through DesignShare, developers now have access to Dover Microsystems’ CoreGuard Silicon IP, which enables processors to defend themselves in real-time from all network-based attacks. CoreGuard prevents illegal instructions from executing before any damage can be done. Its security rules define the difference ...

The SiFive Download - The Next Revolution is Here!

by Jack Kang, vice president of product marketing, SiFive on SiFive
First, we are thrilled to have recently announced that we raised $50.6 million in our Series C funding round! We wanted to thank our existing and new investors - including Chengwei Capital, Huami, SK Telecom and Western Digital - for the continued support and new engagement, so we held a party to celebrate! Check out the full newsletter here!

OTA: Shipping Updates, Drones, Sirens, OsmoCon2018, and More

by Gareth Halfacree on Myriad
Fulfilment of the LimeSDR Mini, GPIO Board, Companion Board, Grove Starter Kit, and Hacker Case continue to progress, with Crowd Supply estimating that the final items will have been sent out by the end of May. Backers waiting for a LimeSDR Mini will be pleased to hear shipment continues in weekly batches, with all pre-orders expected to have been shipped by mid-May. Those who have ordered the LMS8001 Companion Board to boost their SDR’s frequency range, meanwhile, can expect to receive ...

chisel 3.1.0-RC2

by Jim Lawson on Chisel
We’ve just published Chisel v3.1.0-RC2 and FIRRTL v1.1.0-RC2 and compatible updates to the rest of the BIG5 Chisel projects – chisel-testers v1.2.0-RC2, firrtl-interpreter v1.1.0-RC2, and dsptools v1.1.0-RC2. These candidates contain bug fixes to the RC1 candidates and performance improvements. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is welcome.

El Correo Libre — Issue 2

by Gareth Halfacree on LibreCores - Medium
teaser image ORConf 2017 group photo © Craig Shaw Photography.Registration has opened for ORConf 2018 and presentation proposals are invited, while we release another newsletter packed with developments from across the community. Welcome to the second issue of the LibreCores newsletter, featuring topics including the Xilinx ACAP launch, an open audio controller IP, FuseSoC 1.8.1, the RISC-V Barcelona workshop, APIO 0.3.2, and the generation of a simple design for a Coolrunner-II XC2C32A using only open ...

CRU: Open Cellular, RISC-V Progress, Mbed LoRaWAN, and More

by Gareth Halfacree on FOSSi – AB Open
AB Open’s Andrew Back has published a look back at how the world of open source cellular networking has changed over the last six years, including the growth of the Osmocom project. “As exquisitely arcane as it may seem to the uninitiated, cellular infrastructure is very much within the reach of open source development projects,” writes Andrew. “The challenge of creating low cost, open source wireless infrastructure platforms does to some extent combine those of ‘creating the PC’ — or ...

Debian Linux Receives Official 64-bit RISC-V Port

by Gareth Halfacree on FOSSi – AB Open
The Debian Linux distribution now has an official 64-bit RISC-V bootstrap in its ports infrastructure, allowing packages to be easily downloaded for use on the growing number of RISC-V devices on the market. “We’ve been working in the last few weeks to do a (second) bootstrap of Debian for RISC-V, and after a few weeks of hard work it is now bootstrapped and has been imported into the Debian infrastructure, in particular, debian-ports,” explains Manuel Montezelo in the announcement post. ...

OTA: New LimeSuite, RISC-V LimeNET, ‘Minecraft’ Video, and More

by Gareth Halfacree on Myriad
teaser image There’s a fresh new version of the Lime Suite software stack out, version 18.03.0, which brings with it full support for the LimeSDR Mini. Released earlier this week on the Lime Suite GitHub repository, Lime Suite v18.03.0 brings with it full support for programming and controlling the LimeSDR Mini as well as the existing models in the LimeSDR family. Other changes and tweaks include additional controls for the SPI panel in the LimeSuite GUI, fixes for a range of bugs, and updated gateware ...

An open source frequency meter and clock generator

by DP on FPGA – Dangerous Prototypes
teaser image Boris Landoni writes about an open source project frequency meter and clock generator: On the hardware of the controller board LED Matrix, by taking advantage of the reconfigurability of the onboard FPGA, we can build a bivalent tool that is extremely useful to have on our work bench. Via Open Electronics.

CRU: Circumference, the Pi 3 B+, El Correo Libre, SDR, and More

by Gareth Halfacree on FOSSi – AB Open
Ground Electronics, AB Open’s manufacturing division, today unveils a new “datacentre-in-a-box” platform targeting software development, testing, and education: the Raspberry Pi-powered Circumference. Presented to the public for the first time today ahead of a crowdfunding campaign launch in the coming weeks, Circumference is designed to offer all the functionality of a datacentre environment in a compact and attractive package. Based around clusters of eight Raspberry Pi 3 Model B+ compute ...

Register for the Upcoming RISC-V Workshop in Barcelona: May 7-10, 2018

by Carmen Soh on Events – RISC-V Foundation
teaser image About the Workshop Registration is now open for the RISC-V Workshop in Barcelona, co-hosted by the Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC) May 7-10, 2018. The event will be sponsored by NXP and Western Digital. As with past workshops, this event will bring together the RISC-V community to share RISC-V activities underway around the globe, and build consensus on the future evolution of the instruction set. Co-Hosted By         Co-Sponsored ...

FuseSoC 1.8.1

by Olof Kindgren on Tales from Beyond the Register Map
With great features come great bugs. FuseSoC 1.8 had a lot of new functionality but it also has some shortcomings. Some of it was intentional. For both the library support and CAPI2 I wanted to push out an early version with the most important functionality, test the waters and add the missing pieces later. (Un)fortunately both these features turned out to be really really good and I came to depend on them immediately. This made it more important to make sure they were useful as I don't ...

Lime Micro Working on RISC-V LimeNET Base Station

by Gareth Halfacree on FOSSi – AB Open
Lime Microsystems are working with SiFive to build an open wireless base station featuring the former’s field-programmable radio frequency (FPRF) IC and the latter’s RISC-V processor technology. Building on the existing LimeNET platform, which pairs the open LimeSDR software defined radio with x86 host hardware, the prototype design replaces the latter with a HiFive Unleashed multi-core 64-bit  RISC-V board and a Xilinx VC707 FPGA development board. The result: a software-defined wireless ...

Verilator - Verilator 3.922 Released

by Wilson Snyder on Veripool: News
Verilator 3.922 2018-03-17 Support IEEE 1800-2017 as default language. Support trig functions ($sin() etc), bug1281. [Patrick Stewart] Support calling system functions as tasks, bug1285. [Joel Holdsworth] Support assert properties, bug785, bug1290. [John Coiner, et al] Support $writememh. [John Coiner] Add --no-debug-leak to reduce memory use under debug. [John Coiner] Fix severe runtime performance bug in certain foreach loops. [John Coiner] On ...

OTA: GSOC, LimeSDR Mini Updates, Radiosondes, Massive MIMO, and More

by Gareth Halfacree on Myriad
Shipping of the LimeSDR Mini continues apace, with all crowdfunding orders and many outstanding post-campaign pre-orders expected to have been filled within a week of this post – and there’s going to be enough stock left over for latecomers, too. In a shipping update on the Crowd Supply campaign page, the team behind the LimeSDR Mini confirmed that over 300 boards have shipped to backers so far with another 900 arriving at Crowd Supply’s fulfilment facility earlier this month. Shipping is ...

Call for GSoC 2018 Students

by Andrew Back on Myriad
We are delighted once again to be participating in Google Summer of Code as a mentoring organisation with the Free and Open Source SIlicon Foundation. Stefan Wallentowitz, FOSSi Foundation Director, notes “Google Summer of Code is an excellent program for students to get a stipend by Google to work on open source projects.” Adding, “As a student you are free to base your project on one of these ideas, but remember that it is your idea we are looking for, and you should come up with an idea ...

GDB Upstreaming and Binaries: 7.2.0

by OpenRISC Community on OpenRISC
We are proud to announce that the OpenRISC port for gdb has been merged upstream. This was done back in December 2017 so its a bit late notice, but here it is. With that we have released an updated version of the toolchain with x86_64 binaries for easy consumption. The new version, tagged or1k-7.2.0-20180317 is available on our github release page. There are 3 different binaries to choose from: newlib - this is the baremetal toolchain good for running c code directly on the OpenRISC ...

Implementing FizzBuzz on an FPGA

by DP on FPGA – Dangerous Prototypes
teaser image Ken Shirriff writes: I recently started FPGA programming and figured it would be fun to use an FPGA to implement the FizzBuzz algorithm. An FPGA (Field-Programmable Gate Array) is an interesting chip that you can program to implement arbitrary digital logic. This lets you build a complex digital circuit without wiring up individual gates and flip flops. It’s like having a custom chip that can be anything from a logic analyzer to a microprocessor to a video generator. The “FizzBuzz test” is ...

OSDDI: Dr Jeremy Bennett, Embecosm

by Andrew Back on FOSSi – AB Open
In the latest episode of Open Source Digital Design Insights we hear from Dr Jeremy Bennett, CEO of Embecosm, on the numerous motivations for open source silicon, its already modestly successful if largely unknown history, through LEON and OpenRISC ASIC manufacture, Embecosm’s own work on the AAP architecture designed to put compilers through their paces, and the importance of RISC-V. In closing Jeremy notes how there is a bright future ahead for open source silicon, a point which he ...

Mike Wishart Calls for “Open Innovation” in the IoT

by Gareth Halfacree on FOSSi – AB Open
Mike Wishart, chief executive officer at electronics crowdsourcing platform efabless, has issued a call for a move beyond open source software and into the realm of “open innovation.” “Embedded open source software not only works; most our world runs on it today,” Mike writes in the introduction of an opinion piece published in the EE Times this week. “That said, the real story is open innovation, of which open source licenses are simply one part. Open innovation means looking outside ...

LibreCores launches El Correo Libre Newsletter

by Andrew Back on FOSSi – AB Open
LibreCores launch newsletter for the free and open source silicon community, with news on everything from personal projects, through to research and industry developments. The inaugural edition of the El Correo Libre newsletter was published today and features news items on Google Summer of Code 2018, TinyFPGA, the 4th generation myStorm iCE40 development board, Microchip move to acquire Microsemi, lowRISC release 0.5, RISC-V Workshop CFP, and two PULP platform major releases — amongst ...

El Correo Libre — Issue 1

by Gareth Halfacree on LibreCores - Medium
teaser image ¡Hola, amigos! Welcome to the first edition of El Correo Libre, the LibreCores newsletter. Have you ever experienced this? You’ve arrived in a foreign country where you don’t speak the language. You feel a bit left alone, when soon enough a friendly stranger approaches you and shows you all the interesting places in town. This newsletter, of which you’re reading the first ever edition, wants to be your guide and show you around in the world of free and open source digital hardware design. ...

Verilog-Perl - Verilog-Perl 3.450 Released

by Wilson Snyder on Veripool: News
Verilog::Language 3.450 2018-03-12 Support SystemVerilog 1800-2017. Moving forward, use the git "stable" branch to track the latest release and git "v#.###" tags for specific releases.

CRU: Security, Open Consumer Products, Solderpad Hardware Licence 2.0, and More

by Gareth Halfacree on FOSSi – AB Open
GreenWaves Technologies has officially launched GAP8, its RISC-V based low-power application processor for Internet of Things (IoT) and artificial intelligence (AI) applications. Based on the work of the Parallel Ultra Low Power (PULP) project, GAP8 was first shown off as a field-programmable gate array (FPGA) core back in March 2017. Now, it’s physical silicon boasting an eight-core computational cluster and on-board convolutional neural network (CNN) accelerator capable, its creators ...

eeNews Europe Interview With Rick O’Connor Of RISC-V Foundation

by Carmen Soh on RISC-V Foundation
The RISC-V Foundation was present at the Embedded World exhibition with its own booth that also hosted a number of companies within its growing ecosystem. eeNews caught up with Rick O’Connor, executive director of the foundation and asked why a new and open processor architecture was relevant to embedded applications. “RISC-V (pronounced five) was really the result of a summer academic program to create a processor that could be used to teach processor design in 2010,” O’Connor ...

RISC-V’s Potential Highlighted in Low Start-up Costs

by Gareth Halfacree on FOSSi – AB Open
The benefit of an open instruction set architecture (ISA) like RISC-V have been laid bare in a piece by Stacey Higginbotham which puts the real-world cost of launching your own RISC-V semiconductor company below the cost of simply licensing proprietary intellectual property (IP) from a company like Arm. Following the launch of the GAP8 RISC-V application processor (AP) late last month, Stacey highlighted a particular aspect of the GreenWaves story that really showcases the potential that ...

chisel 3.1.0-RC1

by Jim Lawson on Chisel
We’ve just published Chisel v3.1.0-RC1 and FIRRTL v1.1.0-RC1 and compatible updates to the rest of the BIG5 Chisel projects – chisel-testers v1.2.0-RC1, firrtl-interpreter v1.1.0-RC1, and dsptools v1.1.0-RC1. These contain significant updates to annotations and Chisel type cloning, as well as moving to sbt 1.1.1. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. The Chisel and ...

Stacey On IoT Article: GreenWaves Technologies Joins The Race For Machine Learning At The Edge

by Carmen Soh on RISC-V Foundation
A few weeks back, I wrote about the need for machine learning at the edge and what big chip firms are doing to address the challenge. Even as Intel, ARM, and others invest in new architectures, startups are also attempting to innovate with new platforms. GreenWaves Technologies, based in France, is one such company. It has built a machine learning chip that offers multiple cores and low-power machine learning at the edge. The chip is called the GAP8 application processor. GreenWaves CEO ...

The SiFive Download - Are you ready to UNLEASH your genius?

by Jack Kang, vice president of product marketing, SiFive on SiFive
We’re heading to the Embedded Linux Conference next week, March 12-14, to hold our first hackathon. Developers will be among the first to run code on the HiFive Unleashed board with a chance to take home a board of their own and win a $1,000 cash prize. Check out the full newsletter here!

Solderpad Hardware Licence Gets New Release

by Andrew Back on FOSSi – AB Open
Version 2.0 release of Solderpad Hardware Licence is simplified and presented as a wraparound to the Apache 2.0 software license. The Solderpad Hardware Licence is based upon the popular Apache 2.0 software license, which in contrast to simpler permissive software licences such as BSD and MIT, provides greater clarity by defining terms such as source, object and derivative works, while also including patent provisions. The Solderpad Hardware Licence extends Apache 2.0 by covering additional ...

All Aboard, Part 11: RISC-V Hackathon, Presented by SiFive

by Palmer Dabbelt on SiFive
Date: Monday, March 12 – Wednesday, March 14 Time: 10:30am Monday – 1:00pm Wednesday Location: Embedded Linux Conference, Hilton Portland Downtown, Skyline II, Floor 23 UPDATE 2 (3/7/2018) We’ve doubled the cash prize to $2,000 for each challenge! Plus we’ve added a “coolest demo” category, with the same prize package as the other challenges (a HiFive Unleashed board plus the $2,000). You can register here for the Hackathon. UPDATE (3/7/2018) We’ve seen a lot of interest in the ...

OTA: LimeSDR in Space, 4G on the Moon, and More

by Gareth Halfacree on Myriad
The European Space Agency (ESA) has announced a joint project with Lime Microsystems which will see the LimeSDR family of software defined radios used to develop new and innovative satellite communications systems both on ground and in space. “With modern satellite communications, many design challenges are unique, requiring testing and experimentation to reveal what does and does not work,” explains the ESA’s Frank Zeppenfeldt of his organisation’s decision to work with the LimeSDR. “For ...

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Last updated 26 May 2018 08:00 UTC