Planet LibreCores

CRU: RISC-V Hits Consumer Products, GSM Freed, Festival of Maintenance, and More

by Gareth Halfacree on FOSSi – AB Open
Huami, a subsidiary of Chinese electronics specialist Xiaomi, has announced a new family of smartwatches and fitness wearables, and in doing so is set to become the first company to bring a product based on the open RISC-V instruction set architecture (ISA) to the consumer market. Announced by Huami at its technology event in Beijing this week, the Huangshan No. 1 system-on-chip (SoC) is based on the SiFive E31 processor core intellectual property (IP), which is itself based on the open ...

Huami Announces RISC-V Based Fitness Wearables, Smartwatch

by Gareth Halfacree on FOSSi – AB Open
Huami, a subsidiary of Chinese electronics specialist Xiaomi, has announced a new family of smartwatches and fitness wearables, and in doing so is set to become the first company to bring a product based on the open RISC-V instruction set architecture (ISA) to the consumer market. Announced by Huami at its technology event in Beijing this week, the Huangshan No. 1 system-on-chip (SoC) is based on the SiFive E31 processor core intellectual property (IP), which is itself based on the open ...

PULP Platform Announces RISC-V HERO Heterogeneous Research Platform

by Gareth Halfacree on FOSSi – AB Open
The Parallel Ultra-Low Power (PULP) Platform team has announced the release of its latest creation: HERO, the open heterogeneous research platform combining an FPGA-based RISC-V many-core accelerator with an Arm Cortex-A host processor. “HERO combines a PULP-based open-source parallel many-core accelerator implemented on FPGA with a hard ARM Cortex-A multicore host processor running full-stack Linux,” its creators explain. “HERO is the first heterogeneous system architecture that mixes a ...

Verilator - Verilator 4.002 Released

by Wilson Snyder on Veripool: News
Verilator 4.002 2018-09-16 This is a major release. Any patches may require major rework to apply. [Thanks everyone] Add multithreaded model generation. Add runtime arguments. Add GTKWave LXT2 native tracing, bug1333. [Yu Sheng Lin] Note $random has new algorithm; results may vary vs. previous versions. Better optimize large always block splitting, bug1244. [John Coiner] Add new reloop optimization for repetitive assignment compression. Support ...

Retro-uC first time right - yes, we can

by Fatsie on Chips4Makers.io
This post is again about comments posted after launch of the Retro-uC campaign claiming it defies 'common wisdom' and thus is unrealistic. This time about the fact the project assumes the chip will work the first time; in the industry also as first-time-right. In order to explain what are possible problems and the strategy to avoid them, this post will need to be more technical than the previous posts. As expained in the previous post, the startup costs are a big contributor to the final ...

OTA: CrowdCell Hackathon, LimeSDR Projects, Alphabet’s Loon, and More

by Gareth Halfacree on Myriad
Vodafone and Lime Microsystems have announced the first in a planned series of annual hackathon events designed to benefit the Telecom Infra Project, focused on developing on top of the LimeSDR powered CrowdCell platform. A part of the Telecom Infra Project, which aims to drive innovation in the telecommunications arena through the development of more efficient and more interoperable technologies, the CrowdCell Project Group was founded with the aim of producing a 4G cellular relay system ...

chisel 3.1.3

by Jim Lawson on Chisel
We’ve just published Chisel v3.1.3 and FIRRTL v1.1.3 and compatible updates to the rest of the BIG6 Chisel projects – chisel-testers v1.2.4, firrtl-interpreter v1.1.3, and dsptools v1.1.3, and announcing treadle v1.0.1. treadle is a re-write of the firrtl-interpreter optimized for speed. This release of the tool set consists of bug fixes and performance improvements. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and ...

El Correo Libre Issue 7

by Gareth Halfacree on LibreCores - Medium
teaser image Google Summer of Code 2018 Retrospective As in previous years, the FOSSi Foundation has participated in this year’s Google Summer of Code. In this programme Google provides three-month scholarships to students worldwide, allowing them to contribute to open source projects. Even more important than the actual code contributions, the students are encouraged to become active members of open source communities and to learn how those communities work. This way the students become long-term ...

Western Digital CTO: RISC-V Offers “A Clean Sheet of Paper”

by Gareth Halfacree on FOSSi – AB Open
Western Digital has released a short video discussing how the open RISC-V instruction set architecture is changing its vision for data processing, as it pledges to ship billions of RISC-V cores in its future products. Western Digital had previously pledged support for the open RISC-V instruction set architecture with the promise that it was to launch data processing products at a rate of a billion RISC-V cores a year – a billion cores which were previously based on proprietary, locked-down ...

CRU: Vintage FOSSi, ORConf 2018, Tink Cryptography, and More

by Gareth Halfacree on FOSSi – AB Open
Chips4Makers has officially launched a crowdfunding campaign to produce the Retro-uC, an open-silicon microcontroller capable of acting as a Zilog Z80, MOS Technologies 6502, or Motorola M68K microprocessor. “I am delighted to announce that the Retro-uC crowdsupply campaign has now been launched. It has taken a little longer to straighten out the last hurdles in production and delivery but now the campaign is waiting for you,” says Staf Verhaegen of the project’s launch, in an announcement ...

Last Week in RISC-V: Sept 7, 2018

by Palmer Dabbelt on SiFive
This is the last version of “Last Week in RISC-V” that I plan on sending to the various mailing lists, as we’ll be posting the rest of them on SiFive’s Blog. I didn’t get any contributions, but I also haven’t gotten through my email yet – sorry if I missed anything that’s been sent it, but I’m not too far behind so I should have everything read from this week by the end of next week. Linux 4.19-rc3 On Tuesday I tagged my pull request for Linux 4.19-rc3, which contains what I hope to be ...

An Open Source Release of the Freedom U540-C000’s Bootloader

by Troy Benjegerdes and Palmer Dabbelt on SiFive
The FU540-C000, which is available on the HiFive Unleashed development board, is a Linux capable board based on the open source Freedom platform. We built this chip to drive RISC-V Linux development, and it’s been incredibly successful. In the three months since we started shipping the board the RISC-V Linux distribution porting effort, with Debian and Fedora leading the charge, has come farther that it had come in the previous 5 years. It’s been incredible watching the open source ...

Lattice iCE40 Ultra Plus FPGA: Gnarly Grey Upduino – Tutorial 1: The basics

by DP on FPGA – Dangerous Prototypes
teaser image A how-to getting an LED flashing using VHDL from Harris’ Electronics: The cheap price however comes with a few niggles, namely getting it up and running in the first place with the limited documentation. Gnarly Grey do a great job of explaining programming a starting program but don’t say much about further development. With that in mind, I’m going to run through the methodology of getting an LED flashing using VHDL. There seem to be a fair few Verilog methods but not many people seem to ...

ORConf 2018 Programme Finalised, Western Digital Confirmed as Headline Sponsor

by Gareth Halfacree on FOSSi – AB Open
The finalised programme for ORConf, the open-source digital design conference organised by the Free and Open Source Silicon (FOSSi) Foundation, has been published ahead of the event’s opening later this month – and with it the news that storage giant Western Digital has become the headline sponsor. Scheduled for the 21st to the 23rd of September at Poland’s Gdansk University of Technology, the ORConf schedule is packed with talks and workshops covering everything from the RISC-V ecosystem ...

Startup costs and low-volume manufacturing

by Fatsie on Chips4Makers.io
After my Retro-uC crowdfunding campaign was announced comments were made on social media that this project defied 'common wisdom' and therefor is not realistic. One of the comments was on the funding goal that was too low to make a custom ASIC. In this blog I want to go deeper into the choices made for the Retro-uC that made the current goal possible. Unfortunately almost everything in the current semiconductor manufacturing world is done under NDA; this includes the quotes for ...

OTA: EMF Camp Base Stations, LimeSDR in Space, GNU Radio, and More

by Gareth Halfacree on Myriad
LimeSDR units will be a key feature of this year’s Electromagnetic Field (EMF Camp) event, taking place in the UK this weekend, powering a local GSM cellular network for attendees’ use. Part camping festival, part gigantic temporary hackspace, Electromagnetic Field is this year held in Eastnor, UK, and on top of the usual Wi-Fi connectivity and power grid there’s a GSM-based cellular network powered by LimeSDRs. “When the organisers got in touch to ask if we could help out with providing ...

Last Week in RISC-V: August 31, 2018

by Palmer Dabbelt on SiFive
Welcome to the first issue of “Last Week in RISC-V”, a weekly newsletter tracking the RISC-V community. This newsletter was born out of a discussion in SiFive’s internal RISC-V software team and I’m compiling it so it’ll have a somewhat heavy focus on the open source software community for now as that’s where I spend most of my time. The general idea behind “Last Week in RISC-V” is that the RISC-V ecosystem is getting big enough that it’s impossible for any single person to ...

Darkriscv: An Overnight BSD-Licensed RISC-V Implementation

by Gareth Halfacree on FOSSi – AB Open
Developer Marcelo Samsoniuk has demonstrated just how flexible the open RISC-V instruction set architecture is by creating his own implementation – in, he claims, just one night. “Developed in a magic night of 19 Aug, 2018 between 2am and 8am, the darkriscv is a very experimental implementation of the open source RISC-V instruction set,” Marcelo writes of his creation. “Nowadays, after one week of exciting sleepless nights of work (which explains the lots of typos you will found ahead), the ...

Retro-uC Brings Open Silicon to Vintage Computing IP

by Gareth Halfacree on FOSSi – AB Open
Chips4Makers has officially launched a crowdfunding campaign to produce the Retro-uC, an open-silicon microcontroller capable of acting as a Zilog Z80, MOS Technologies 6502, or Motorola M68K microprocessor. “I am delighted to announce that the Retro-uC crowdsupply campaign has now been launched. It has taken a little longer to straighten out the last hurdles in production and delivery but now the campaign is waiting for you,” says Staf Verhaegen of the project’s launch, in an announcement ...

Retro-uC crowdfunding campaign launched on crowdsupply

by Fatsie on Chips4Makers.io
I am delighted to announce that the Retro-uC crowdsupply campaign has now been launched. It has taken a little longer to straighten out the last hurdles in production and delivery but now the campaign is waiting for you. Together with the crowdsupply staff, the delay has also been used to streamline the pledge targets. Next to the hardware targets now also open silicon development support is included in some of the targets. This is to help to bootstrap the low-volume open silicon movement. ...

Verilator - Verilator 4.000 approaches; announcement at OrCONF

by Wilson Snyder on Veripool: News
We're glad to announce that Verilator 4.000 is now in beta test and will be formally announced at OrConf 2018 The git tree now contains the beta, please give it a try, and enjoy the main new feature of multithreaded simulation! If your git repo was using the 'master' branch (the default) as upstream you need do nothing, you'll now get the 4.000 sources. If you were using the git 'develop-v4' branch, that branch is now merged into 'master'. 'develop-v4' was deleted. Pulling from a ...

CRU: RISC-V Edge AI, microPlatforms, MQTT Woes, and More

by Gareth Halfacree on FOSSi – AB Open
AB Open is proud to confirm its sponsorship of ORConf 2018, the open-source digital design conference, to be held this year at the Gdansk University of Technology in Poland. Officially announced by the Free and Open Source Silicon (FOSSi) Foundation today, AB Open’s sponsorship follows our commitment in the fields of free and open source software, hardware, and – thanks to projects including RISC-V, which have begun to enter their maturity with off-the-shelf product launches – silicon. This ...

Verilator - Verilator 3.926 Released

by Wilson Snyder on Veripool: News
Verilator 3.926 2018-08-22 Add OBJCACHE envvar support to examples and generated Makefiles. Change MODDUP errors to warnings, msg2588. [Marshal Qiao] Fix define argument stringification (`"), broke since 3.914. [Joe DErrico] Fix to ignore Unicode UTF-8 BOM sequences, msg2576. [HyungKi Jeong] Fix std:: build error, bug1322. Fix function inlining inside certain while loops, bug1330. [Julien Margetts]

SiFive, Nvidia Partner for RISC-V, NVDLA Edge AI SoC

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneer SiFive has announced a partnership with graphics and Arm-based processor giant Nvidia to integrate the former’s RISC-V core intellectual property with the latter’s deep-learning acceleration IP in a single high-performance system-on-chip (SoC) design. “Nvidia open sourced its NVDLA [Nvidia Deep Learning Architecture] architecture to drive the adoption of AI,” explains Deepu Talla, vice president and general manager of autonomous Machines at Nvidia, of his company’s ...

Zephyr Project RTOS Gets RISC-V Partners, Board Support

by Gareth Halfacree on FOSSi – AB Open
The Zephyr Project, which maintains an eponymous open-source real-time operating system (RTOS) for the Internet of Things (IoT) under The Linux Foundation, has announced partnerships with SiFive and Antmicro to add RISC-V support to the platform. “RISC-V is about creating open source platforms for the entire world to collaborate on, but hardware doesn’t exist without software,” explains SiFive’s Jack Kang of the partnership that sees his company becoming a Zephyr Project member. “Given ...

OTA: OpenLST, Radiosonde Guidance, Wi-Fi Weapon Detection, and More

by Gareth Halfacree on Myriad
Satellite communications specialist Planet Labs has announced its entry into the open-source radio community, with an open-hardware device dubbed the OpenLST built exclusively using widely-available commercial off-the-shelf (COTS) parts. “Radio system design is often viewed as a ‘black box’ that is out of reach to all but the most experienced of engineers. This leads many educational groups to commercial radio solutions, which are often very expensive, difficult to integrate, and can ...

Bluespec Releases Apache-Licensed Piccolo RISC-V Core

by Gareth Halfacree on FOSSi – AB Open
Massachusetts-based Bluespec, a founding member of the RISC-V Foundation, has released the first entry in its open-source RISC-V processor family: the 32-bit three-stage Piccolo. Designed, the company explains, for Internet of Things (IoT) and other embedded uses, the small-footprint Piccolo design uses the 32-bit RV32IM variant of the open RISC-V instruction set architecture. The company’s initial release includes a synthesisable Verilog core for deployment on a field-programmable gate ...

El Correo Libre Issue 6

by Gareth Halfacree on LibreCores - Medium
teaser image Preparing for ORConf 2018 This time of year finds the FOSSi Foundation preparing for ORConf, our annual open source digital design gathering. We felt it might be appropriate to explore the history of ORConf in the newsletter this month, and why we’re proud to run this event. ORConf, now in its seventh year, was inspired by an informal meeting of OpenRISC project developers in 2011 in a pub in Stockholm, Sweden. It was decided that an annual meeting should be arranged, and ORConf became a ...

AB Open Confirms Sponsorship of ORConf 2018

by Gareth Halfacree on FOSSi – AB Open
AB Open is proud to confirm its sponsorship of ORConf 2018, the open-source digital design conference, to be held this year at the Gdansk University of Technology in Poland. Officially announced by the Free and Open Source Silicon (FOSSi) Foundation today, AB Open’s sponsorship follows our commitment in the fields of free and open source software, hardware, and – thanks to projects including RISC-V, which have begun to enter their maturity with off-the-shelf product launches – silicon. This ...

CRU: RISC-V SSDs, Open Satellite Radio, LoRaWAN 1.0.3, and More

by Gareth Halfacree on FOSSi – AB Open
This fortnight has been a strong one for the open RISC-V instruction set architecture, starting with the news that IIT Madras has partnered with Intel and HCL Technologies to create an I/O-packed microcontroller test chip in 22nm FinFET that takes aim at ARM Cortex A35/A55 and has successfully booted Linux on the design. In a presentation at the RISC-V workshop hosted at the Indian Institute of Technology (IIT) Madras in July, researchers shared details of a collaboration between the ...

Mobiveil Partners with SiFive for RISC-V-based Programmable Storage

by Gareth Halfacree on FOSSi – AB Open
SiFive’s implementation of the open RISC-V instruction set architecture (ISA) has scored another design win, this time to power a smart reprogrammable storage device aimed at the data centre and enterprise markets from Mobiveil. Fresh from the announcement of the world’s first RISC-V based SSD controller and SSD implementation from Fadu, RISC-V pioneer SiFive has confirmed a design win that will see the company’s E51 and U54 multi-core RISC-V intellectual property (IP) used in Mobiveil’s ...

Chisel Community Conference – 11/13/18 – 11/14/18

by Jim Lawson on Chisel
WHAT: Save the Date for the first Chisel Community Conference (CCC) WHERE: To be determined in the Bay Area. WHEN: Tuesday 11/13/18 – Wednesday 11/14/18   DETAILS: We are holding the first Chisel Community Conference, located in the Bay Area, on November 13-14, 2018 (details forthcoming). This will be the first event promoting the Chisel language, FIRRTL compiler, and associated software ecosystem, bringing together the community for multiple talks, tutorials, exhibitions and ...

Fadu Announces World’s First RISC-V SSD, Controller

by Gareth Halfacree on FOSSi – AB Open
Fadu, a fabless semiconductor company specialising in the memory and storage markets, has announced the launch of the world’s first RISC-V based solid state drive (SSD) controller, the Annapurna, based on SiFive’s E51 multi-core IP. Beating Western Digital, which announced its own plans to switch from proprietary instruction set architectures to the open RISC-V ISA late last year, to the punch, Fadu’s Annapurna is claimed to have market-leading specifications: at one third the power and one ...

RISC-V Foundation Announces Call For Papers And Registration Promotions For Inaugural RISC-V Summit

by Carmen Soh on Events – RISC-V Foundation
Discounts on Conference and Exhibition Passes Available Now Through Sept. 17 WHAT: RISC-V Summit in Santa Clara, Calif. WHERE: Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, Calif., 95054 WHEN: Monday, Dec. 3 to Thursday, Dec. 6, 2018 DETAILS: The RISC-V Foundation, in partnership with Informa’s Knowledge & Networking Division, KNect365, will hold its first annual RISC-V Summit at the Santa Clara Convention Center from Dec. 3-6, 2018. The Summit will be a major ...

RISC-V Architecture SHAKTI Test Chip Boots Linux

by Andrew Back on FOSSi – AB Open
IIT Madras partner with Intel Corporation and HCL Technologies to create I/O packed microcontroller test chip in 22nm FinFET that takes aim at ARM Cortex A35/A55. In a presentation at the RISC-V workshop hosted at the Indian Institute of Technology (IIT) Madras in July, researchers shared details of a collaboration between the SHAKTI project, Intel and HCL, which resulted in a chip that has successfully booted Linux and supports the secure L4 microkernel. The test chip was fabricated in ...

SiFive Hosts Girl Geek X and Champions Custom Silicon For All

by Ali Sana, Business Development Manager on SiFive
teaser image On Wednesday, July 25th, SiFive had the pleasure of hosting Girl Geek X at our offices in San Mateo. Girl Geek X is a brilliant organization with the aim of connecting women across companies large and small for the purposes of networking and sharing career advice in the fast-paced tech industry. Over the past 10 years, Girl Geek X has grown from a 400-person dinner hosted by Google to a well-known Bay Area group with a membership base of more than 15,000. As the champions of innovation ...

Silicon Dreams: RISC-V from Emulation to FPGA to ASIC

by Gareth Halfacree on FOSSi – AB Open
teaser image When working with brand-new silicon designs, particularly free and open source silicon, there’s a bit of a bootstrapping issue: you want to write software for the new silicon, but there’s no silicon yet available; nobody wants to go to the expense of making the silicon, meanwhile, when there’s no software to use it. The answer is a three-pronged approach: emulation, soft-core implementations running on a field-programmable gate array (FPGA), and finally application-specific integrated ...

CRU: ORConf 2018, Quantum Education, KiCad 5.0, and More

by Gareth Halfacree on FOSSi – AB Open
An initial programme for ORConf 2018, the open-source digital design conference to be held in Gdansk, Poland this September, has been published – and there are some big names showing off the state of the art on the schedule. While there are more speakers yet to be announced, the initial schedule for ORConf 2018 is already shaping up to be the most impressive list of heavy-hitters yet – including Wilson Snyder, who will be presenting on the Verilator 4.0 multi-threaded Verilog simulator he ...

ORConf 2018 update

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image This year’s ORConf is but 8 weeks away and we’re pleased to announce that we have another great event lined up for everyone. First, I’d like to announce and publicly thank our major sponsor this year; Google. In addition to them I’d like to thank AntMicro and Rick O’Connor and the RISC-V Foundation for their continued support of ORConf. Already we have a fantastic lineup of presentations in store; Wilson Snyder’s presentation on Verilator 4.0, Tim Ansell’s talk on SymbiFlow, an update on ...

chisel 3.1.2

by Jim Lawson on Chisel
We’ve just published Chisel v3.1.2 and FIRRTL v1.1.2 and compatible updates to the rest of the BIG5 Chisel projects – chisel-testers v1.2.2, firrtl-interpreter v1.1.2, and dsptools v1.1.2. This release consists of bug fixes and performance improvements. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is welcome.

RISC-V Foundation’s SSC Calls on Big Data, Defence Companies

by Gareth Halfacree on FOSSi – AB Open
RISC-V Foundation director Ted Speers has offered up more details on the organisations he would like to see involved in the recently-announced Security Standing Committee. Announced earlier this month by executive director Rick O’Connor, the RISC-V Foundation’s Security Standing Committee came with a request: “[A] call to action for industry leaders, universities and government organisations to join the Foundation and work with us to build a more secure world for the benefit of ...

Initial ORConf 2018 Programme Published

by Gareth Halfacree on FOSSi – AB Open
An initial programme for ORConf 2018, the open-source digital design conference to be held in Gdansk, Poland this September, has been published – and there are some big names showing off the state of the art on the schedule. While there are more speakers yet to be announced, the initial schedule for ORConf 2018 is already shaping up to be the most impressive list of heavy-hitters yet – including Wilson Snyder, who will be presenting on the Verilator 4.0 multi-threaded Verilog simulator he ...

OTA: Cave Rescue Radios, Spectrum Pricing, Clones, and More

by Gareth Halfacree on Myriad
This fortnight’s big news was, of course, the successful rescue of 12 children and one adult stranded in a Thai cave by flooding, and there’s a surprise twist in the tale: the rescue was carried out using USB radio transceivers designed by a radio ham. Hackaday explains that members of the British Cave Rescue Council (BCRC) called by the Thai authorities to assist with the rescue of 12 children and an adult stranded in the Tham Luang Nang Non cave had a now near-two-decade old device to ...

CRU: RISC-V Security, LoRaWAN Tutorial, Fog Computing, and More

by Gareth Halfacree on FOSSi – AB Open
It’s been a busy fortnight for the open silicon, starting with the news that the RISC-V Foundation, the driving force behind the eponymous open processor architecture, has announced the formation of a security standing committee – and is asking for cooperation from the broader industry. “As the number of connected devices grows exponentially and new security vulnerabilities like Meltdown and Spectre emerge, it’s become increasingly important to develop more robust security approaches. The ...

Interrupts on the SiFive E2 Series

by Drew Barbier, Sr. Field Applications Engineer on SiFive
Last week SiFive launched the new E2 Series RISC-V Core IP. The E2 Series represents SiFive’s smallest, most efficient Core IP Series and is targeted specifically for embedded microcontroller designs. One of the reasons it is great for microcontroller applications is because of its extremely small area footprint, just 0.023mm2 in 28nm for the entire E20 Standard Core! Another reason it’s great for the embedded market is its configurability. The E2 Series can be configured even smaller than ...

RISC-V Foundation Announces Agenda For RISC-V Workshop In Chennai

by Carmen Soh on Events – RISC-V Foundation
Workshop features more than 20 speaking sessions and a keynote from Western Digital   WHAT: RISC-V Workshop in Chennai, India WHERE: IC&SR Building, Indian Institute of Technology (IIT) Madras, Sardar Patel Road, Opposite to C, L.R.I, Adyar, Chennai, Tamil Nadu 600036, India WHEN: Wednesday, July 18 and Thursday, July 19, 2018 DETAILS: The RISC-V Workshop in Chennai will showcase the expansive RISC-V ecosystem, highlighting current and prospective projects and implementations that influence ...

Rattled Arm Launches Anti-RISC-V Marketing Campaign

by Gareth Halfacree on FOSSi – AB Open
The growing impetus behind the free and open source silicon (FOSSi) RISC-V project appears to have industry incumbents rattled, with Arm launching an aggressive marketing campaign which attempts to sow the seeds of doubt in engineers’ minds about the ISA’s benefits versus Arm’s own proprietary intellectual property (IP). Following the launch of affordable RISC-V ASICs from companies including SiFive and the news that Nvidia, Rambus, and Western Digital are all shipping or planning to ship ...

El Correo Libre Issue 5

by Gareth Halfacree on LibreCores - Medium
teaser image In Praise of Documentation Welcome to the July issue of El Correo Libre! I’d like to start with a thank you to everyone working on free and open-source silicon projects around the world. It’s because of your hard work and dedication that there’s so much to talk about in our monthly newsletters, and frankly it wouldn’t make a scrap of sense for the FOSSi Foundation itself to exist if not for your efforts. With all these projects, though, it can be hard to keep track of what’s new, what’s ...

OnChip Teases Itsy-Chipsy Call for Participation

by Gareth Halfacree on FOSSi – AB Open
Open silicon specialist OnChip has promised to launch a call for participation in its Itsy-Chipsy low-cost semiconductor manufacturing facility, and is already receiving interesting suggestions from potential users. Announced back in April, Itsy-Chipsy aims to allow smaller companies and hobbyists to produce application-specific integrated circuits (ASICs) for as little as $100 by providing a chip platform with utility blocks placed on a chip to service custom blocks designed by the ...

Renode 1.4 Brings HiFive Unleashed, Freedom E310 Support

by Gareth Halfacree on FOSSi – AB Open
Renode, Antmicro’s virtual development tool for multinode embedded networks, has received support for SiFive’s Freedom E310 and HiFive Unleashed development boards. “Renode was created based on many years of experience with the development of software for embedded systems – both for gateways, on-board computers as well as sensor nodes and microcontrollers. Testing and developing physical embedded systems is difficult due to poor reproducibility and lack of insight into the current state of ...

OTA: LoRa Testing, Homebrew Antennas, Reactor Monitoring, and More

by Gareth Halfacree on Myriad
Engineer Mark Zachmann has posted of his work using the LimeSDR Mini to test low-power long-range LoRa radios, as part of an Internet of Things (IoT) project. “I’m working on a LoRa system at 915MHz. LoRa is a frequency modulation method used on low power IOT devices. Being able to see spectral lines, decipher messages and send messages, is key to successful development. This is a real-life example,” Mark writes. “One of the units I had would communicate sometimes. It worked with some of ...

RISC-V Foundation at Design Automation Conference (DAC) Proceedings

by Carmen Soh on Events – RISC-V Foundation
teaser image RISC-V Foundation at Design Automation Conference (DAC) Proceedings June 24 – 27, 2018 The 54th Design Automation Conference (DAC) was held at the Moscone Center West, in San Francisco from June 25 – 25, 2018. DAC 2018 demonstrated the exciting momentum of the RISC-V ecosystem. The RISC-V Foundation booth featured member companies Imperas Software, Microsemi, SiFive, Syntacore, UltraSoC and Western Digital. Throughout the event, the RISC-V Foundation hosted panels and speaking  sessions, ...

RISC-V Day in Shanghai Proceedings

by Alicia Daleiden on Events – RISC-V Foundation
teaser image RISC-V Day in Shanghai June 30, 2018   The RISC-V Day in Shanghai, China took place on June 30, 2018. Hosted by Fudan University in Shanghai, the event included in-depth technical presentations and updates on the RISC-V architecture, a speaking lineup from leading technology companies and research institutions in the RISC-V ecosystem and networking opportunities. Proceedings Check out the slides from each of the sessions below. Time Event Speaker, Affiliation Slides 8:00 ...

RISC-V Foundation Forms Security Standing Committee

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation, the driving force behind the eponymous open processor architecture, has announced the formation of a security standing committee – and is asking for cooperation from the broader industry. “As the number of connected devices grows exponentially and new security vulnerabilities like Meltdown and Spectre emerge, it’s become increasingly important to develop more robust security approaches. The RISC-V community has the historic opportunity to leverage a new platform for ...

CRU: Open Silicon, LoRa Growth, LPWA-CB, and More

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneers OnChip and SiFive have separately announced new microcontroller chip designs, taking aim at the low-power sensor market with their own takes on the open architecture. In a message to social networking service Twitter, OnChip revealed a RISC-V microcontroller design described as having always-on features, three power states with fine-grained power management, deep sleep, power-on reset and brown-out detector, in-house designed non-volatile memory (NV-RAM), USB 1.1 and 2.0 ...

FuseSoC 1.8.2

by Olof Kindgren on Tales from Beyond the Register Map
FuseSoC 1.9 will have an impact so great that people will divide history into the eras before and after it's release. But before that happens, it's time for a less earth-shattering minor release. Allow me to introduce FuseSoC 1.8.2Backend separationThe biggest feature is also the least visible for most users. A lot of time since the last release was spent on moving stuff around with the ultimate goal of splitting out the backends (the part that create project files and launches EDA tools) ...

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Last updated 21 September 2018 17:30 UTC