Planet LibreCores

X-FAB, Efabless Announces RISC-V-Based Raven Mixed-Signal SoC

by Gareth Halfacree on FOSSi – AB Open
X-FAB Silicon Foundries and Efabless Corporation have announced the creation of a new mixed-signal system-on-chip (SoC) reference design boasting a RISC-V core: Raven. Designed, its creators claim, in just three months, the open-source mixed-signal Raven SoC was built using an open-source tool set put together by Efabless. Its PicoRV32 32-bit RISC-V processing core runs at 100MHz in bench testing, with simulations suggesting its clock rate could be boosted to 150MHz. Wedded to Efabless’ ...

Verilator - Verilator 4.016 Released

by Wilson Snyder on Veripool: News
Verilator 4.016 2016-06-16 Add --quiet-exit, bug1436. [Todd Strader] Error continuation lines no longer have %Error prefix. Support logical equivalence operator <->. Support VerilatedFstC set_time_unit, bug1433. [Pieter Kapsenberg] Support deferred assertions, bug1449. [Charles Eddleston] Mark infrequently called functions with GCC cold attribute. Fix sign-compare warning in verilated.cpp, bug1437. [Sergey Kvachonok] Fix fault on $realtime with %t, bug1443. ...

OpTiMSoC wins the Eurolab4HPC Open Source Project Award!

by OpTiMSoC on OpTiMSoC
teaser image How exciting! At the Week of Open Source Hardware (WOSH) in Zürich, OpTiMSoC co-won the Eurolab4HPC Open Source Project Award! We’re very excited and honored to see the efforts we put into OpTiMSoC being more widely recognized. Thanks a lot to the sponsors of this award! The other prices went to Nyuzi, a processor for highly parallel and GPGPU applications, and FuseSoC, a hardware package manager and build tool which we use in OpTiMSoC! You can find OpTiMSoC, Nyuzi, FuseSoC, and many ...

Embench Embedded Benchmark Project Calls for Aid

by Gareth Halfacree on FOSSi – AB Open
A call-to-arms has been raised by the Embench team for assistance in developing a new, fully-open benchmark suite designed to offer embedded developers an alternative to the products of the Embedded Microprocessor Benchmark Consortium (EMBC). As detailed in an article on EE Times, the Embench team is working to produce an open-source benchmark for embedded developers which distils performance metrics from around 20 real-world applications into a single score. This score will be relative to ...

lowRISC at Week of Open Source Hardware

by LowRISC on lowRISC on lowRISC
teaser image Pretty much the whole team is in Zurich this week for the RISC-V Workshop and inaugural Week of Open Source Hardware, with a packed programme that got off to a start today and which runs all the way through to Friday afternoon. This morning lowRISC board member, Professor Luca Benini, gave a RISC-V Workshop keynote entitled, Energy efficient computing from Exascale to MicroWatts: The RISC-V playground. Our friends and close collaborators at PULP Platform are giving a number of talks this ...

El Correo Libre Issue 16

by Gareth Halfacree on LibreCores - Medium
teaser image WOSH and the Google Summer of Code Kick Off It’s finally here: the Week of Open Source Hardware starts today with two days of RISC-V workshops followed by two days of presentations and tutorials all around free and open source silicon topics. For those not attending, you’ll be able to read more about the event in next month’s El Correo Libre! In other great news, the FOSSi Foundation has been accepted into the Google Summer of Code (GSOC) programme. In GSOC Google pays selected students a ...

European Processor Initiative Delivers First Architectural Designs

by Gareth Halfacree on FOSSi – AB Open
The European Processor Initiative (EPI) has announced the delivery of its first architectural designs to the European Commission, marking the first steps in its efforts to create a made-in-Europe processor family for high-performance and automotive computing. Launched in December 2018, the European Processor Initiative boasts 26 industry partners – up from 23 at foundation – and has three primary goals on its roadmap: the creation of a general-purpose processor (GPP) with a focus on high ...

The RISC-V Revolution is Sweeping Across the APAC Region and Australia

by Swamy Irrinki on SiFive
Join SiFive Tech Symposiums in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney As we make our way around the world meeting and engaging with others in the semiconductor and hardware design community, we are seeing an increased interest in RISC-V based hardware innovation. This is due in large part to the emergence of market-ready RISC-V core IP, development tools and silicon solutions based on cloud-based design platforms that facilitate the creation of custom SoC solutions for edge ...

El Correo Libre - Issue 16

by FOSSi Foundation on FOSSi Foundation - News & Posts
The FOSSi Foundation’s monthly roundup of all things Open Source semiconductor design, including an overview about our Google Summer of Code, can be found here: El Correo Libre Issue 16 - LibreCores - Medium

An update on Ibex, our microcontroller-class CPU core

by LowRISC on lowRISC on lowRISC
teaser image At the beginning of many chips projects, there’s a dream. Could we create a more future-proof chip by embedding an FPGA fabric into it? Could we measure glucose levels more accurately by integrating a small bio lab onto a chip? Could we more reliably recognize kittens in a set of pictures by implementing neural network inference in hardware? In implementation, this dream becomes a piece of hardware, with digital or analog logic, sensors, actuators, and much more. Let’s get it produced and ...

OpenHW Group Announced

by FOSSi Foundation on FOSSi Foundation - News & Posts
Today the OpenHW Group was announced. This is yet another great step for Free and Open Source Silicon. With the rise of RISC-V we have seen some great momentum beyond the processor cores itself. We now see groups growing from and around the RISC-V ecosystem with big players involved. This strongly confirms our story and we look forward to the next months of continuous growth of the FOSSi community. The OpenHW Group is backed for example by Alibaba, NXP, Thales and Silicon Labs, with a ...

Announcing Architecture Version 1.3

by OpenRISC Community on OpenRISC
It has been been a few years since the release of OpenRISC version 1.2. But, it’s been a busy few years of getting GDB and GCC ports upstream. Now with the GCC port upstream we are able to make progress and this new architecture revision does just that bringing in a handful of new instructions: New instruction lf.stod.d for converting floats from single precision to double prevision New instruction lf.dtos.d for converting floats from double precision to single precision New ...

Introducing Pirmin & Laura

by LowRISC on lowRISC on lowRISC
teaser image Pirmin Vogel and Laura James both joined lowRISC on May 1st this year. A few weeks in to their new roles, they each share thoughts on what attracted them to work at lowRISC. Pirmin: “After having traveled around the world for 6 months, I finally started my new position as hardware/software engineer at lowRISC C.I.C. in Cambridge at the beginning of May. At lowRISC, we are working on open-source hardware/software ecosystems with a fully open-sourced, Linux-capable, RISC-V-based SoC being ...

Google Summer of Code 2019 - Kickoff

by FOSSi Foundation on FOSSi Foundation - News & Posts
The Google Summer of Code (GSoC) has started and we are happy to announce that we have seven students working for projects related to FOSSi Foundation: Analysis of WARP-V on FireSim with RocketChip, Alaa Salman The WARP-V RISC-V core generator was developed in 2018 as a configurable, adaptable open-source RISC-V CPU core generator, taking advantage of advanced digital design features of TL-Verilog. It can be configured as a low-power, slow-clock, single stage pipeline, a high-frequency ...

The Design Revolution in Europe: Highlights From the SiFive Tech Symposiums

by Purvi Shenoy on SiFive
teaser image We just wrapped up our six-city tour in Europe, which included Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam. Together with our co-hosts, Qamcom, Syntacore, Imagination Technologies and Mentor; and ecosystem partners, Rambus, IAR Systems, UltraSoC, Antmicro, SecureRF, Credo and lowRISC, we engaged with over 500 responses/registrations throughout the tour. One of the highlights was having people from the audience come onto the stage and use SiFive's Core Designer to build ...

Google Summer of Code 2019

by OpenRISC Community on OpenRISC
The Google Summer of Code is a yearly event which teams open source projects with college students. Students learn about technology and the open source community and projects benefit from new contributions. As in previous years this year OpenRISC is participating as part of the FOSSi foundation project. We have teamed up with librecores-ci, also of FOSSi, to work with Nancy Chauhan on improving the mor1kx’s continuous integration pipeline. You can read the details of the project on ...

OTA: LimeSDR WSPR, Angle of Arrival Experiments, DSPs without Maths, and More

by Gareth Halfacree on MyriadRF
Community member Kiril Miloshev has been interviewed for the Lime Micro Community Hub, on his experiments with Weak Signal Propagation Reporting (WSPR) using the LimeSDR Mini. “Software defined radios got my attention as they are very universal, and you can do whatever you can imagine with them. Especially ones like the LimeSDR Mini, which are inexpensive yet powerful at the same time,” Kiril explains. “I love the huge frequency range. The full duplex makes it possible to use the device as ...

Antmicro Launches Renode 1.7 with TSN, PTP Support, PicoRV32, Murax SoC

by Gareth Halfacree on FOSSi – AB Open
Antmicro has announced the release of Renode 1.7 – quickly followed by version 1.7.1 – with the framework’s first support for time-sensitive networking (TSN) and precision time protocol (PTP) on RISC-V platforms. An open-source simulation framework popular among those working within the proprietary Arm and open RISC-V ecosystems, and recently praised by Dover Microsystems for helping to significantly shorten the company’s design cycle, the latest release of Antmicro’s Renode brings with it ...

BML S7-Mini FPGA Module

by kevinhub88 on Black Mesa Labs
teaser image 2019.05.19 : This blog posting is about the open source S7 Mini FPGA module designed by Black Mesa Labs and professionally manufactured and distributed by Trenz Electronics.  In short, it is a Xilinx Spartan7 7S25 on a 1″x2″ module with 64 Mbits of DRAM, Config PROM, 5V single supply solution and provides either 32 user I/Os on a 0.100″ (2.54mm) DIP grid or 64 user I/Os on a 0.050″ (1.27mm) grid at LVCMOS33 levels. This posting isn’t complete, but a work in progress and central point for ...

CRU: ‘Unhackable’ Chips, Grove AI HAT, RISC-V Drones, and More

by Gareth Halfacree on FOSSi – AB Open
Researchers from the University of Michigan have announced a new RISC-V processor design with a strong focus on security, using ‘churn’ to keep attackers from exploiting vulnerabilities. “Today’s approach of eliminating security bugs one by one is a losing game,” claims Todd Austin, professor of computer science and engineering at the University of Michigan and one of the developers behind the design, dubbed Morpheus. “People are constantly writing code, and as long as there is new code, ...

Western Digital’s Zvonimir Bandić Offers an Intro to SweRV Core

by Gareth Halfacree on FOSSi – AB Open
Western Digital’s Zvonimir Bandić has published an introduction to the company’s open SweRV Core, which it has released to the public following its efforts to move to the RISC-V instruction set architecture (ISA) for its future storage processing products. Western Digital unveiled the SweRV Core late last year, making the source code available in late January under a permissive licence. Based on the RISC-V ISA, the SweRV Core has seen what Western Digital chief technical officer Martin Fink ...

Onwards and upwards at lowRISC

by LowRISC on lowRISC on lowRISC
If you haven’t checked it out yet, be sure to take a look at our press release and the corresponding Google blog post. This industry support and growth of our board is a huge step forwards for lowRISC. As Royal Hansen, vice president of Security, Google, said: "Google believes that open source is good for everyone. To further our commitment, we are investing both capital and engineering resources to create a sustainable open source hardware ecosystem. In addition to engineering resources, ...

lowRISC Expands and Appoints New Members to the Board of Directors from Google and ETH Zurich

by LowRISC on lowRISC on lowRISC
teaser image London, England - lowRISC C.I.C., the open source system on a chip (SoC) organisation, today announced that Prof. Luca Benini (ETH Zurich), Dominic Rizzo (Google) and Ron Minnich (Google) have joined its board of directors. The announcement coincides with a new phase of hiring by lowRISC with the goal of significantly increasing the size of its Cambridge-based engineering team during 2019. lowRISC is a not-for-profit, community-driven organisation working to provide a high quality, ...

PULP Platform Partners with GreenWaves, Bitcraze for RISC-V AI Drone Controller

by Gareth Halfacree on FOSSi – AB Open
The Parallel Ultra-Low Power (PULP) Platform has announced a partnership between ETH Zurich, Greenwaves Technology, and Bitcraze to develop a PULP-powered and wireless artificial intelligence module for drone use: the AI Deck. Based on the earlier PULP-Shield, built as part of the PULP-DroNet project, the AI Shield is designed to control a Crazyflie 2.0 micro-drone. The original design partnered GreenWaves’ GAP8 RISC-V system-on-chip with two off-chip memories, a QVGA ultra-low-power ...

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part I

by Camille Kokozaki on SiFive
teaser image SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing, Calista Redmond was just appointed the new CEO of the RISC-V Foundation). He shared a slide showing the growing RISC-V ecosystem from tools vendors, to IP/semi chip ...

El Correo Libre Issue 15

by Gareth Halfacree on LibreCores - Medium
teaser image Catch-Up and Latch-Up: FOSSi Foundation’s First US Multi-Day Event Latch-Up in Portland, Oregon last weekend marked the first multi-day FOSSi Foundation event we’ve held outside Europe. What transpired surpassed even our best expectations. We cannot thank everyone involved enough, and it’ll be difficult for this write-up to do justice to the quality of the presenters and the enthusiasm for open source hardware in the room and, later, in the bars of Portland. A soft opening to the weekend ...

OpenPiton+Ariane Workshops Scheduled for WOSH, ISCA in June

by Gareth Halfacree on FOSSi – AB Open
The OpenPiton project has announced a pair of workshops centred around its OpenPiton+Ariane platform, taking place in Zurich during the Week of Open Source Hardware (WOSH) and Arizona as part of International Symposium on Computer Architecture (ISCA). Created in partnership with the Parallel Ultra-Low Power (PULP) Platform, OpenPiton+Ariane combines the former’s 64-bit application-class RISC-V processor design with the OpenSPARC-based OpenPiton research processor – designed, its creators ...

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part II

by Camille Kokozaki on SiFive
teaser image During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded Processors, and E Cores 32-bit Embedded Processors. Embedded intelligence allows mixing of application cores with embedded cores, extensible custom instructions, ...

The SiFive Tech Symposiums are Heading to Six Cities in Europe in May!

by Swamy Irrinki on SiFive
Hello Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam Our 2019 global symposiums and workshops have been hugely successful in promoting the RISC-V ISA and fostering expansive collaboration within the open-source community. It's invigorating to see how the worldwide semiconductor ecosystem is energized and mobilized by the open ISA. One of the areas receiving the most attention is embedded intelligence. The RISC-V ISA is enabling designers and innovators to actively pursue ...

lowRISC at the SiFive Symposium in Cambridge

by LowRISC on lowRISC on lowRISC
teaser image Several lowRISC team members attended the SiFive Symposium in our home town of Cambridge on May 13th 2019, a lovely sunny day. Imagination Technologies were co-hosting with SiFive, and we heard from both companies. Krste Asanovic, chairman of the board at the RISC-V Foundation, gave a great introduction to RISC-V and progress so far. Naveed Sherwani, CEO of SiFive, talked us through their silicon design platform and future services. We also heard from SecureRF and IAR Systems. Alex gave a ...

OpenPiton+Ariane Tutorials in June

by Jonathan Balkind on OpenPiton Blog
teaser image We are excited to announce two OpenPiton+Ariane tutorials this June! Now is your chance to get hands-on with the RISC-V hardware research platform. The first tutorial is part of the Week of Open Source Hardware (WOSH) in conjunction with the RISC-V Workshop Zurich. It is a half-day tutorial on Thursday afternoon, June 13th, at ETH Zurich, Switzerland. Interested attendees can register here. The second tutorial is in conjunction with ISCA/FCRC 2019 in Phoenix, Arizona. It is a half-day ...

OTA: DAB/DAB+ via ODR-mmbTools, IQ Server for a Pi, LimeSDR on a Nintendo Switch, and More

by Gareth Halfacree on MyriadRF
Community member Godfrey L has published a multi-part series on using a LimeSDR and the ODR-mmbTools software bundle to transmit Digital Audio Broadcasting (DAB) signals. “My journey on the reason to use LimeSDR and ODR-mmbTools for DAB/DAB+ transmission started from the announcement that Raspberry Pi could transmit FM station all by itself,” Godfrey explains. “I said alright, let me try with LimeSDR then since it can transimit and receive almost everything. Well on that front it took me to ...

Seeed Studio Opens Pre-Orders for RISC-V-based Grove AI HAT Board

by Gareth Halfacree on FOSSi – AB Open
Seeed Studio has begun taking pre-orders for its Grove AI HAT for Edge Computing, an artificial intelligence-focused accelerator add-on for the Raspberry Pi which is based on the RISC-V Kendryte K210 processor. Based on the Sipeed MAIX M1 module, a development board for which the company crowdfunded late last year, the Grove AI HAT features a dual-core 64-bit RISC-V CPU running at 600MHz along with a 16-bit neural network co-processor dubbed the Kendryte Processing Unit (KPU), a dedicated ...

Verilator - Verilator 4.014 Released

by Wilson Snyder on Veripool: News
Verilator 4.014 2019-05-08 Add --trace-fst-thread. Support '#' comments in $readmem, bug1411. [Frederick Requin] Support "'dx" constants, bug1423. [Udi Finkelstein] For FST tracing use LZ4 compression. [Tony Bybell] Add error when use parameters without value, bug1424. [Peter Gerst] Auto-extend and WIDTH warn on unsized X/Zs, bug1423. [Udi Finkelstein] Fix missing VL_SHIFTL_ errors, bug1412, bug1415. [Larry Lee] Fix MinGW GCC 6 printf formats, bug1413. ...

The CHIPS Alliance Announces Inaugural Workshop Agenda

by Gareth Halfacree on FOSSi – AB Open
The CHIPS Alliance, a Linux Foundation-backed consortium for free and open source silicon (FOSSi) efforts, has announced in inaugural workshop for the 19th of June at Google’s Sunnyvale, California facility. Launched back in March, the CHIPS Alliance includes among its founding members Google, Western Digital, Esperanto, and SiFive, all but one of which has announced or shipped products based on the open RISC-V instruction set architecture (ISA). Its first workshop will, its organisers ...

Gentoo Linux Announces Experimental RISC-V Support

by Gareth Halfacree on FOSSi – AB Open
The Gentoo Linux distribution has announced initial, experimental support for the free and open RISC-V instruction set architecture (ISA). “After some preparations, we’re happy to announce (initially experimental) support for a new arch: riscv,” writes Andreas Huettel in the gentoo-dev mailing list. “The keyword is ‘~riscv’; no stable keyword will be used in the beginning.” Details on the support, which has been confirmed as working using the QEMU emulator on non-RISC-V hardware, can be ...

Researchers Turn to RISC-V for High-Security Morpheus Processor Design

by Gareth Halfacree on FOSSi – AB Open
Researchers from the University of Michigan have announced a new RISC-V processor design with a strong focus on security, using ‘churn’ to keep attackers from exploiting vulnerabilities. “Today’s approach of eliminating security bugs one by one is a losing game,” claims Todd Austin, professor of computer science and engineering at the University of Michigan and one of the developers behind the design, dubbed Morpheus. “People are constantly writing code, and as long as there is new code, ...

CRU: Fieldbus in Linux, FPGA SweRV Core, Wuthering Bytes Tickets, and More

by Gareth Halfacree on FOSSi – AB Open
Linux 5.2, the upcoming release of the open source kernel, is to receive an official subsystem for the Fieldbus networking protocol family – bringing built-in support for the monitoring and control of industrial equipment. Spotted by Michael Larabel on the Linux news site Phoronix, the Fieldbus subsystem has been accepted into the Linux 5.2 merge window ahead of the kernel’s stable release in July. “”The subsystem allows for devices to exchange data over a Fieldbus whether it be Profinet, ...

LimeRFE Front-End Add-On, the Field Report Contest, SatNOGS in HackSpace Mag, and More

by Gareth Halfacree on MyriadRF
The LimeSDR family has grown a little larger with the unveiling of the LimeRFE, an open hardware software-definable front-end add on for the LimeSDR, LimeSDR Mini and LimeNET Micro. Due to launch on Crowd Supply in the near future, the LimeRFE includes power amplifier, filter, and support circuitry, is programmable using the Arduino IDE, and integrates with Lime Suite. It’s designed with real-world use-cases in mind, from custom HAM radio to cellular and wideband network use – and even ...

QEMU 4.0.0 Brings New RISC-V Features

by Gareth Halfacree on FOSSi – AB Open
Version 4.0.0 of the QEMU emulator has been released, bringing with it new features for those working with the RISC-V instruction set architecture (ISA). Designed to allow a system to run code designed for a different instruction set, emulation via QEMU or a similar package is a key part of developing for less-common ISAs like RISC-V – allowing a developer to produce software without requiring access to a hardware implementation, whether that’s a soft core on a field-programmable gate array ...

Dover Microsystems Details Shift to Open-Source Renode Framework

by Gareth Halfacree on FOSSi – AB Open
Dover Microsystems’ Greg Sullivan has written of how Antmicro’s open-source Renode development framework has considerably decreased the length of his company’s design cycle – showcasing why the framework is becoming increasingly popular. Built with embedded platforms and the Internet of Things (IoT) in mind, Renode allows for the execution, debugging, and testing of embedded software unmodified on a standard off-the-shelf PC, and is proving popular for those designing the hardware itself. ...

Western Digital Boasts of “Gratifying” SweRV Response, Releases FPGA Reference Design

by Gareth Halfacree on FOSSi – AB Open
Western Digital has announced a strong response to the release of its RISC-V based open silicon SweRV Core, along with the availability of an official implementation for field-programmable gate array (FPGA) use. Announced back in December 2018 as part of a company-wide initiative to transition data processing products away from proprietary cores to alternatives based on the RISC-V instruction set architecture (ISA), released in January this year, and the subject of a deep-dive analysis by ...

OTA: AMSAT-F QO-100 Transmissions, SDR Added to RSGB Syllabus, New limeSNA, and More

by Gareth Halfacree on MyriadRF
The second AMSAT-F Recontre Radiomateur Spatiale was a special one, for an out-of-this-world reason: its lectures were transmitted to a global audience using a LimeSDR Mini and the Es’hail-2 (QO-100) satellite. Evariste Courjaud explained the transmission chain in an interview published this week on the Lime Micro community hub: “The chain was: a PC running Vmix (video mixer) to NDI [Network Device Interface] (over Ethernet) to a PC modulator. On the PC modulator: NDI to ffmpeg H.264 ...

RISC-V Foundation Finalises Schedule for RISC-V Workshop Zurich

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has released the agenda for its RISC-V Workshop Zurich, to be held on the 11th-13th of June as part of the larger Week of Open Source Hardware (WOSH). Following its call for speakers, which closed back in February, the RISC-V Foundation has firmed up the schedule for the three-day RISC-V Workshop Zurich 2019 – though only the first two of these days are open to the general public, with the latter being reserved for RISC-V Foundation members. The agenda includes a ...

CRU: Open Source Awards 2019, MIPS Open, RISC-V Priorities, and More

by Gareth Halfacree on FOSSi – AB Open
Open UK, a membership organisation dedicated to promoting and supporting the use of free and open source standards and software in the UK, has announced a call for nominations for the UK Open Source Awards 2019. “The awards have happened five times in the last 10 years, but not since 2015,” explains Open UK’s Amanda Brock. “With the massive move to adoption of open source across businesses and its rightful place as mainstream in our society by being recognised through events like the Red ...

El Correo Libre Issue 14

by Gareth Halfacree on LibreCores - Medium
teaser image Healthy Signs for the Free and Open Source Silicon Movement I really feel like the whole Free and Open Source Silicon movement has finally taken off. Many from our community have been around for ten years or more, but only over the last few years have we really seen a steadily increasing interest in open silicon design and engineering design automation tools. Many awesome projects are becoming very popular and attracting new folks, and we are seeing many companies, large enterprises, ...

chisel 3.1.7

by Jim Lawson on Chisel
We’ve recently (3/20/2019) published Chisel v3.1.7 and FIRRTL v1.1.7 and compatible updates to the rest of the BIG6 Chisel projects – chisel-testers v1.2.9, firrtl-interpreter v1.1.7, treadle v1.0.5, and dsptools v1.1.8. This release of the tool set consists of bug fixes. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is welcome.

SPDX Project Adds Open Hardware Licences to Licence List

by Gareth Halfacree on FOSSi – AB Open
The Software Package Data Exchange (SPDX) project, the initial standard for which AB Open’s Andrew Back acted as a contributor, has released the latest version of its SPDX Licence List – and it now includes open hardware licences. Made for ease of reference and to simplify identification of licences and their applied exceptions in documentation, source files, and elsewhere, the SPDX Licence List is now in Version 3.5 and includes both the licences themselves and a list of commonly found ...

Calista Redmond Outlines “Key Priorities” for the RISC-V Foundation

by Gareth Halfacree on FOSSi – AB Open
Calista Redmond, newly-appointed chief executive of the RISC-V Foundation, has highlighted the organisation’s key priorities for accelerating adoption and deployment of the open instruction set architecture (ISA) and related technologies. “With the significant uptick in RISC-V adoption over the past few years, the RISC-V Foundation Technical Committee has made it a priority to prepare the RISC-V base ISA and standard extensions for ratification,” Calista, who was appointed chief executive ...

Latch-Up Portland venue, speakers and sponsors

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image The FOSSi Foundation announced Latch-Up (latchup.io), earlier this year - its annual North American open source digital design conference in the mold of ORConf. Latch-Up opens a new chapter for the FOSSi Foundation, with it being the first event in the spirit of ORConf held in North America. Latch-Up is a community-focused conference for open source semiconductor, digital design and embedded systems professionals and enthusiasts. Expect presentations on a wide range of topics; open source ...

Freedom Studio Version 2019.03

by Drew Barbier on SiFive
teaser image Ever since we launched Freedom Studio in 2017, it has been a great way to quickly and easily get started writing code for SiFive platforms, whether those platforms are development boards such as the HiFive1 Rev B, Digilent Arty FPGA, or even our testbench, which ships along with SiFive IP deliverables. Freedom Studio is based on the industry-standard Eclipse IDE and comes with several plugins and pre-built tools supporting Windows, macOS, and Linux, to help with embedded development for ...

Wave Computing Announces First MIPS Open Release

by Gareth Halfacree on FOSSi – AB Open
Wave Computing has made the first public release under its MIPS Open initiative, announced back in December 2018, though its licence terms lag behind competitors like RISC-V. Following the sale of MIPS by Imagination Technologies, new owner Wave Computing came up with a plan to boost the popularity of the instruction set architecture (ISA): take on free and open source silicon darling RISC-V head-to-head with MIPS Open, an initiative that would see the company release its latest MIPS core ...

OTA: LimeSNA, QO-100 Projects, a Self-Tuning Antenna, and More

by Gareth Halfacree on MyriadRF
Forum user Peter ‘nepe’ Kis has published a scalar network analyser (SNA), developed using the LimeSDR Mini, which displays its user interface in the user’s web browser: limeSNA. Based on the pyLMS7002Soapy example, Peter’s software has been tested with the LimeSDR Mini and should be compatible – or easily made so – with other LimeSDR family members. It’s also under continuous improvement: “I have lots of ideas for how i can improve the tool,” he explains in an interview published to the ...

LLVM 8.0.0 Release Adds RISC-V Support to lld Linker

by Gareth Halfacree on FOSSi – AB Open
The LLVM project has announced the release of LLVM 8.0.0, which brings with it a wealth of new features including the first support for the open RISC-V architecture in the lld linker. Released this week, LLVM 8.0.0 includes a range of enhancements to the compiler and toolchain collection. “This release contains the work on trunk up to Subversion revision r351319, plus work on the release branch,” explains Hans Wennborg. “It’s the result of the LLVM community’s work over the past six months, ...

PULP Platform Announces Silicon Labs Partnership

by Gareth Halfacree on FOSSi – AB Open
The Parallel Ultra-Low Power (PULP) Platform has announced that Silicon Labs has adopted the platform to extend and customise embedded processor cores in their integrated circuit designs. Now approaching its sixth year, having been launched by Luca Benini at the University of Bologna back in May 2013, the PULP Platform’s numerous projects include the Hero open heterogeneous research platform, the RISC-V Ariane core and extended OpenPiton+Ariane design in partnership with the OpenPiton ...

Verilator - Verilator 4.012 Released

by Wilson Snyder on Veripool: News
Verilator 4.012 2019-3-23 Add +verilator+seed, bug1396. [Stan Sokorac] Support $fread. [Leendert van Doorn] Support void' cast on functions called as tasks, bug1383. [Al Grant] Add IGNOREDRETURN warning, bug1383. Report PORTSHORT errors on concat constants, bug 1400. [Will Korteland] Fix VERILATOR_GDB being ignored, msg2860. [Yu Sheng Lin] Fix $value$plus$args missing verilated_heavy.h. [Yi-Chung Chen] Fix MSVC compile error, bug1406. [Benjamin ...

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Last updated 19 June 2019 01:00 UTC