Planet LibreCores

CRU: RISC-V Security, LoRaWAN Tutorial, Fog Computing, and More

by Gareth Halfacree on FOSSi – AB Open
It’s been a busy fortnight for the open silicon, starting with the news that the RISC-V Foundation, the driving force behind the eponymous open processor architecture, has announced the formation of a security standing committee – and is asking for cooperation from the broader industry. “As the number of connected devices grows exponentially and new security vulnerabilities like Meltdown and Spectre emerge, it’s become increasingly important to develop more robust security approaches. The ...

Interrupts on the SiFive E2 Series

by Drew Barbier, Sr. Field Applications Engineer on SiFive
Last week SiFive launched the new E2 Series RISC-V Core IP. The E2 Series represents SiFive’s smallest, most efficient Core IP Series and is targeted specifically for embedded microcontroller designs. One of the reasons it is great for microcontroller applications is because of its extremely small area footprint, just 0.023mm2 in 28nm for the entire E20 Standard Core! Another reason it’s great for the embedded market is its configurability. The E2 Series can be configured even smaller than ...

RISC-V Foundation Announces Agenda For RISC-V Workshop In Chennai

by Carmen Soh on Events – RISC-V Foundation
Workshop features more than 20 speaking sessions and a keynote from Western Digital   WHAT: RISC-V Workshop in Chennai, India WHERE: IC&SR Building, Indian Institute of Technology (IIT) Madras, Sardar Patel Road, Opposite to C, L.R.I, Adyar, Chennai, Tamil Nadu 600036, India WHEN: Wednesday, July 18 and Thursday, July 19, 2018 DETAILS: The RISC-V Workshop in Chennai will showcase the expansive RISC-V ecosystem, highlighting current and prospective projects and implementations that influence ...

Rattled Arm Launches Anti-RISC-V Marketing Campaign

by Gareth Halfacree on FOSSi – AB Open
The growing impetus behind the free and open source silicon (FOSSi) RISC-V project appears to have industry incumbents rattled, with Arm launching an aggressive marketing campaign which attempts to sow the seeds of doubt in engineers’ minds about the ISA’s benefits versus Arm’s own proprietary intellectual property (IP). Following the launch of affordable RISC-V ASICs from companies including SiFive and the news that Nvidia, Rambus, and Western Digital are all shipping or planning to ship ...

El Correo Libre Issue 5

by Gareth Halfacree on LibreCores - Medium
teaser image In Praise of Documentation Welcome to the July issue of El Correo Libre! I’d like to start with a thank you to everyone working on free and open-source silicon projects around the world. It’s because of your hard work and dedication that there’s so much to talk about in our monthly newsletters, and frankly it wouldn’t make a scrap of sense for the FOSSi Foundation itself to exist if not for your efforts. With all these projects, though, it can be hard to keep track of what’s new, what’s ...

OnChip Teases Itsy-Chipsy Call for Participation

by Gareth Halfacree on FOSSi – AB Open
Open silicon specialist OnChip has promised to launch a call for participation in its Itsy-Chipsy low-cost semiconductor manufacturing facility, and is already receiving interesting suggestions from potential users. Announced back in April, Itsy-Chipsy aims to allow smaller companies and hobbyists to produce application-specific integrated circuits (ASICs) for as little as $100 by providing a chip platform with utility blocks placed on a chip to service custom blocks designed by the ...

Renode 1.4 Brings HiFive Unleashed, Freedom E310 Support

by Gareth Halfacree on FOSSi – AB Open
Renode, Antmicro’s virtual development tool for multinode embedded networks, has received support for SiFive’s Freedom E310 and HiFive Unleashed development boards. “Renode was created based on many years of experience with the development of software for embedded systems – both for gateways, on-board computers as well as sensor nodes and microcontrollers. Testing and developing physical embedded systems is difficult due to poor reproducibility and lack of insight into the current state of ...

OTA: LoRa Testing, Homebrew Antennas, Reactor Monitoring, and More

by Gareth Halfacree on Myriad
Engineer Mark Zachmann has posted of his work using the LimeSDR Mini to test low-power long-range LoRa radios, as part of an Internet of Things (IoT) project. “I’m working on a LoRa system at 915MHz. LoRa is a frequency modulation method used on low power IOT devices. Being able to see spectral lines, decipher messages and send messages, is key to successful development. This is a real-life example,” Mark writes. “One of the units I had would communicate sometimes. It worked with some of ...

RISC-V Foundation at Design Automation Conference (DAC) Proceedings

by Carmen Soh on Events – RISC-V Foundation
teaser image RISC-V Foundation at Design Automation Conference (DAC) Proceedings June 24 – 27, 2018 The 54th Design Automation Conference (DAC) was held at the Moscone Center West, in San Francisco from June 25 – 25, 2018. DAC 2018 demonstrated the exciting momentum of the RISC-V ecosystem. The RISC-V Foundation booth featured member companies Imperas Software, Microsemi, SiFive, Syntacore, UltraSoC and Western Digital. Throughout the event, the RISC-V Foundation hosted panels and speaking  sessions, ...

RISC-V Day in Shanghai Proceedings

by Alicia Daleiden on Events – RISC-V Foundation
teaser image RISC-V Day in Shanghai June 30, 2018   The RISC-V Day in Shanghai, China took place on June 30, 2018. Hosted by Fudan University in Shanghai, the event included in-depth technical presentations and updates on the RISC-V architecture, a speaking lineup from leading technology companies and research institutions in the RISC-V ecosystem and networking opportunities. Proceedings Check out the slides from each of the sessions below. Time Event Speaker, Affiliation Slides 8:00 ...

RISC-V Foundation Forms Security Standing Committee

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation, the driving force behind the eponymous open processor architecture, has announced the formation of a security standing committee – and is asking for cooperation from the broader industry. “As the number of connected devices grows exponentially and new security vulnerabilities like Meltdown and Spectre emerge, it’s become increasingly important to develop more robust security approaches. The RISC-V community has the historic opportunity to leverage a new platform for ...

CRU: Open Silicon, LoRa Growth, LPWA-CB, and More

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneers OnChip and SiFive have separately announced new microcontroller chip designs, taking aim at the low-power sensor market with their own takes on the open architecture. In a message to social networking service Twitter, OnChip revealed a RISC-V microcontroller design described as having always-on features, three power states with fine-grained power management, deep sleep, power-on reset and brown-out detector, in-house designed non-volatile memory (NV-RAM), USB 1.1 and 2.0 ...

FuseSoC 1.8.2

by Olof Kindgren on Tales from Beyond the Register Map
FuseSoC 1.9 will have an impact so great that people will divide history into the eras before and after it's release. But before that happens, it's time for a less earth-shattering minor release. Allow me to introduce FuseSoC 1.8.2Backend separationThe biggest feature is also the least visible for most users. A lot of time since the last release was spent on moving stuff around with the ultimate goal of splitting out the backends (the part that create project files and launches EDA tools) ...

OnChip, SiFive Announce New RISC-V Microcontroller Cores

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneers OnChip and SiFive have separately announced new microcontroller chip designs, taking aim at the low-power sensor market with their own takes on the open architecture. In a message to social networking service Twitter, OnChip revealed a RISC-V microcontroller design described as having always-on features, three power states with fine-grained power management, deep sleep, power-on reset and brown-out detector, in-house designed non-volatile memory (NV-RAM), USB 1.1 and 2.0 ...

chisel 3.1.1

by Jim Lawson on Chisel
We’ve just published Chisel v3.1.1 and FIRRTL v1.1.1 and compatible updates to the rest of the BIG5 Chisel projects – chisel-testers v1.2.1, firrtl-interpreter v1.1.1, and dsptools v1.1.1. This release consists of bug fixes and performance improvements. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is welcome.

OpenPiton Research Processor Reaches Release 7

by Gareth Halfacree on FOSSi – AB Open
The team behind the OpenPiton Open Source Research Processor project has announced Release 7, bringing with it a range of improvements designed to make it easier to implement. Built on top of the open-source OpenSPARC processor, created in 2006 when Sun Microsystems released RTL code for its UltraSPARC T1 processor, OpenPiton is a free and open-source silicon (FOSSi) project which aims to scale from a single low-power core to a 500 million count many-core implementation. OpenPiton Release ...

OTA: One-Box Cellular, Finalised 5G, Altair-Powered SDR, and More

by Gareth Halfacree on Myriad
Community member Lucas Riobó has, alongside colleagues Francisco Veiras, María Garea, and Patricio Sorichetti, announced a novel use for a LimeSDR: software-defined optoelectronics. “In this work, we propose a general architecture for the implementation of Software-Defined Optoelectronic systems (SDOs),” Lucas explains in the forum post announcing the early-access publication of his team’s paper. “As an application example, we built a software-defined optical interferometer (SDOI) using the ...

RISC-V Workshop in Chennai

by Carmen Soh on Events – RISC-V Foundation
teaser image RISC-V Workshop in Chennai July 18-19, 2018 The RISC-V Foundation invites you to attend the RISC-V Workshop in Chennai, India on July 18-19, 2018. Hosted by The Indian Institute of Technology Madras (IIT Madras) and sponsored by Western Digital, the RISC-V Workshop in Chennai will discuss current and prospective RISC-V projects and implementations, as well as influence the future evolution of the instruction set architecture (ISA) from Silicon Valley to Silicon Fenn and beyond. The RISC-V ...

RISC-V Ecosystem Highlights Momentum Across Asia At RISC-V Day In Shanghai

by Carmen Soh on Events – RISC-V Foundation
RISC-V members to present on RISC-V based products and solutions WHERE: Fudan University, Handan Campus, 220 Handan Rd, WuJiaoChang, Yangpu Qu, Shanghai Shi, China, 200433 WHEN:  Saturday, June 30, 2018, 8 a.m. – 6 p.m. CST WHAT:  The RISC-V Foundation will share updates on new projects and implementations from its international membership at the RISC-V Day in Shanghai, with a focus on the growth of the RISC-V ecosystem across Asia. RISC-V Foundation member companies Andes Technologies, ...

Retro-uC for XLR8 Release 20180617

by Fatsie on Chips4Makers.io
A release has been done of the Retro-uC on the XLR8 implementing Motorola 68000 support for Retro-uC. Please find the release notes and the file to download on the gitlab page.

Motorola 68000 support complete in Retro-uC

by Fatsie on Chips4Makers.io
I'm happy to announce that now support for the Motorola 68000 in the Retro-uC is complete. It uses the ao68000 core to implement the Motorola 68000 instruction set. As usual, it has taken more effort than originally planned. As the ao68000 already had a Wishbone interface used as the internal bus for the Retro-uC the first steps went fluently. I needed to fix a bug in my block read support but that was quickly done. The most time consuming was to get the endianness right. In the Retro-uC I ...

CRU: York’s LoRaWAN Plan, HiFive Unleashed Unleashed, and More

by Gareth Halfacree on FOSSi – AB Open
First unveiled back at FOSDEM, the SiFive HiFive Unleashed Linux-compatible RISC-V development board heralds an exciting time in the world of free and open source silicon – and AB Open’s Andrew Back has been working with one. “It’s great that we now have a Linux capable development board for 64-bit RISC-V in ASIC, with features including plenty of RAM, gigabit Ethernet and flash storage,” Andrew writes in the conclusion of his detailed out-of-the-box experience write-up. “Everything is in ...

RISC-V Day in Shanghai

by Carmen Soh on Events – RISC-V Foundation
teaser image RISC-V Day in Shanghai June 30, 2018   The RISC-V Foundation invites you to attend RISC-V Day in Shanghai, China on June 30, 2018. Hosted by Fudan University in Shanghai, the event will include in-depth technical presentations and updates on the RISC-V architecture, a speaking lineup from leading technology companies and research institutions in the RISC-V ecosystem and ample opportunity for networking. The RISC-V Day in Shanghai agenda will be categorized into the following topics: ...

Verilator - Verilator 3.924 Released

by Wilson Snyder on Veripool: News
Verilator 3.924 2018-06-12 Renamed --profile-cfuncs to --prof-cfuncs. Report interface ports connected to wrong interface, bug1294. [Todd Strader] When tracing, use scalars on single bit arrays to appease vcddiff. Fix parsing "output signed" in V2K port list, msg2540. [James Jung] Fix parsing error on bad missing #, bug1308. [Dan Kirkham] Fix $clog2 to be in verilog 2005, bug1319. [James Hutchinson]

Version 3.6.0 released

by Esko Pekkarinen on Kactus2: News
+ Added support to run Kactus2 from command-line without GUI+ Added editor for port type definitions+ Added support for multiple abstraction definitions in a bus interface+ Improvements to Memory Designer Improved item scaling in non-compressed mode Improved search through hierarchies Improved visulization for multiple address spaces connected to one memory map + Added feature to save HW, System and Memory Designer view as a PNG, JPG or SVG image+ Improved expression ...

Growing RISC-V Ecosystem To Share New Developments And Momentum At DAC 2018

by Carmen Soh on Events – RISC-V Foundation
RISC-V Foundation and members to exhibit and participate in a variety of speaking tracks WHERE: DAC 2018, West Hall, Level Two at Booth #2638; Moscone Center West, 800 Howard St, San Francisco, CA 94103 WHEN: Sunday, June 24 to Wednesday, June 27, 2018 WHAT: The RISC-V Foundation will share updates on new projects, products and implementations from its expansive membership at DAC 2018. The RISC-V Foundation will be exhibiting with member companies Imperas Software, Microsemi, SiFive, ...

El Correo Libre Issue 4

by Gareth Halfacree on LibreCores - Medium
teaser image Reports from the RISC-V Barcelona Workshop 2018 Welcome to the June issue of El Correo Libre, the official newsletter of LibreCores and the Free and Open Source Silicon Foundation. There’s no better place to start things off, of course, than to take a look at the eighth RISC-V Workshop which recently took place in Barcelona — and there was plenty for attendees to see and do, including welcome news from the RISC-V Foundation’s Rick O’Connor that the Foundation has grown to over 150 members ...

Getting Started with the HiFive Unleashed

by Andrew Back on FOSSi – AB Open
teaser image Creating a new bootable Micro SD card, building a custom Poky Linux system, and running Debian on the world’s first RISC-V-based, Linux-capable development board. The HiFive Unleashed was unveiled back at FOSDEM only a matter of months ago and so, unsurprisingly, it’s still relatively early days for Linux distribution support. However, as we’ll come to see, it’s not difficult to get up and running with an embedded build system and thanks to emulation having been available for some time, ...

Unleashing More Fun Under the Sun

by David Lee, Product Manager on SiFive
teaser image Good news, HiFive fans! A limited supply of HiFive Unleashed Development Kits are now available on CrowdSupply for purchase. Since the launch of HiFive Unleashed, many new capabilities are being enabled on the Freedom U540 SoC, the industry’s first RISC-V based, 64-bit quad-core application processor running Linux. The updated boards now support Debian and Fedora Linux, both of which enable developers to build a fully functional Linux PC with a modern desktop. Additionally, with the help ...

The SiFive Download - What’s Up Next?

by Jack Kang, vice president of product marketing, SiFive on SiFive
We recently announced that Intel Capital participated in our Series C funding round! Our CEO, Naveed Sherwani, revealed the investment earlier this month at the Intel Capital Global Summit. Check out the full newsletter here!

RISC-V At Design Automation Conference (DAC)

by Carmen Soh on Events – RISC-V Foundation
teaser image Join the RISC-V Foundation at the 54th Design Automation Conference (DAC) conference at the Moscone Center West in San Francisco, California from June 25 – 27, 2018. Visit Our Booth The RISC-V Foundation booth will feature pods from member companies: Imperas, Microsemi, SiFive, Syntacore, UltraSoC and Western Digital. Visit us in West Hall, Level Two at Booth #2638. Check Out Our Members’ Booths Additional RISC-V member companies will be onsite at DAC: Andes Technology – West Hall, Level ...

OTA: LimeSDR Shipping, 6G Cellular, New Osmocom, and More

by Gareth Halfacree on Myriad
Work to deliver outstanding LimeSDR, LimeSDR Mini, and associated devices continues, but there’s been a major change in the background: Crowd Supply is now in full control of inventory management and distribution, which is going to make future fulfilment considerably smoother at the cost of a moderate delay in the short term. “Up until now, we’ve been manufacturing LimeSDR products in fits and starts in order to efficiently allocate resources to meet demand in close to real time. While ...

CRU: HiFive Expansion, Computer Vision, Osmocom, and More

by Gareth Halfacree on FOSSi – AB Open
AB Open and its hardware division Ground Electronics have launch a campaign for Circumference, a family of custom-designed desktop cluster computing units based around the popular Raspberry Pi and UDOO x86 single-board computer families. Available to pre-order now on crowdfunding site Crowd Supply, the Circumference C25 boasts support for up to eight Raspberry Pi computers while the Circumference C100 can hold up to 32 giving it a total maximum capacity of 128 64-bit low-power Arm ...

Run-Control Debug ahead!

by Open SoC Debug on
Stop the engines! This command will be understood by Open SoC Debug soon as Shivam Aggarwal (@shivmgg) adds run-control debug support to Open SoC Debug. Run-control debug, or “stop and stare debugging” is known to many when using a debugger such as GDB to set breakpoints and inspect the program state once the executed halted. Up to now, Open SoC Debug focused on tracing, leaving this other important debugging technique on the wishlist. But not any longer. Shivam, who does this work as part ...

OTA: Python SNAs and VNAs, High-Frequency Trading, Linux Containers, and More

by Gareth Halfacree on Myriad
A new Python package, pyLMS7002Soapy, has been published as a more feature-packed replacement for the old pyLMS7002M library – bringing with it bundled examples which use the LimeSDR or LimeSDR Mini as a scalar or vector network analyser (SNA/VNA). Uploaded to the Myriad RF GitHub repository late last month the new PyLMS7002Soapy package aims to provide easy prototyping and algorithm development for Python users, based on a SoapySDR back-end. Launching with support for the LimeSDR and ...

HiFive Unleashed Gets Packed PolarFire Powered Expansion

by Andrew Back on FOSSi – AB Open
teaser image World’s first Linux-capable RISC-V development board benefits from expansion that adds PCIe, M.2 SSD, SATA, HDMI, a 300K element PolarFire FPGA, and more. Launched back in February at FOSDEM the HiFive Unleashed RISC-V development board boasts a 64-bit Freedom U540 SoC with features that include a 4+1 Multi-Core Coherent Configuration (up to 1.5 GHz), implemented in TSMC 28nm process. The development board also has 8GB DDR4 RAM, a USB UART for console, gigabit Ethernet, Micro SD storage, ...

OnChip Announces New 32-bit RISC-V Microcontroller

by Gareth Halfacree on FOSSi – AB Open
Colombia-based semiconductor specialist OnChip has announced a 32-bit RISC-V microcontroller design aimed at low-power sensor applications, developed in partnership with SiFive. Fresh from announcing the next generation of Itsy-Chipsy, the company’s low-quantity semiconductor fabrication platform which aims to allow the creation of single-unit DIP-packaged chips for around $100, OnChip has shown off the design of a new microcontroller part based on a 32-bit implementation of the RISC-V ...

Barcelona RISC-V Workshop: Day Two

by LowRISC on lowRISC
The eighth RISC-V workshop is continuing today in Barcleona. As usual, I’ll be keeping a semi-live blog of talks and announcements throughout the day. Look back here for the day one live blog. Note that slides from most presentations are now available at riscv.org. Fast interrupts for RISC-V: Krste Asanovic Embedded is a major use for RISC-V. There is a desire for faster interrupt handling with support for nested preempted interrupts. Summary of current RISC-V interrupts Local ...

RISC-V Workshop in Barcelona Proceedings

by Carmen Soh on Events – RISC-V Foundation
teaser image Proceedings for the RISC-V Workshop in Barcelona 7-10 May, 2018 Co-hosted By Co-sponsored By   Keynote sessions will include Robert Oshana, vice president of software engineering research and development at NXP, Martin Fink, executive vice president and chief technology officer at Western Digital, and Mateo Valero, director at the Barcelona Supercomputing Center. The three-day event schedule is as follows: Monday, May 7, 2018 – A half-day of tutorials from the working groups of the ...

El Correo Libre — Issue 3

by Gareth Halfacree on LibreCores - Medium
teaser image Describing himself in his Twitter profile as a hardware verification architect, Luke Valenty has become a household name among FPGA enthusiasts for one very good reason: he’s the creator of TinyFPGA, a family of low-cost accessible and open hardware field-programmable gate array (FPGA) development boards. Costing between $12 and $38 depending on capabilities, the boards have proven extremely popular among both enthusiasts taking their first steps and professional hardware engineers looking ...

Barcelona RISC-V Workshop: Day One

by LowRISC on lowRISC
The eighth RISC-V workshop is going on today in Barcleona. As usual, I’ll be keeping a semi-live blog of talks and announcements throughout the day. Follow here for the day two live blog. Note that slides from most presentations are now available at riscv.org. Introduction: Rick O’Connor This workshop has 325 attendees representing 101 companies and 25 universties. Largest outside of Silicon Valley. Rick gives the usual overview of the RISC-V Foundation structure. The RISC-V Foundation ...

Intel Capital Investment Boosts Vision for the Future

by Naveed Sherwani, Chief Executive Officer at SiFive on SiFive
We’re very happy to announce that Intel Capital participated in our recent Series C funding round. The investment was revealed at the Intel Capital Global Summit earlier today. Now, you may be thinking, “$50.6 million provides immense potential for SiFive – so now what?” For those of you who aren’t familiar with what SiFive is all about, we aim to leverage the body of software and tools available from the open-source community under the guidance of the RISC-V Foundation with the intention ...

PULP Open Silicon Project Celebrates its Fifth Birthday

by Gareth Halfacree on FOSSi – AB Open
The Parallel Ultra-Low Power (PULP) Project has celebrated its fifth birthday with a retrospective, discussing the progress made since its inception during a meeting at the University of Bologna in May 2013. “It has been exactly 5 years since Luca Benini started the PULP (Parallel Ultra Low Power) project in a meeting attended by a handful of people squeezed in a tiny office in the University of Bologna,” writes Frank K. Gurkaynak, director of the Microelectronics Design Centre at ETH ...

CRU: Homebrew Silicon, OSHCamp 2018, eSIMs Delayed, and More

by Gareth Halfacree on FOSSi – AB Open
The cause of truly home-made semiconductors hit a major milestone late last month when engineer Sam Zeloof became, to common knowledge, the first person to successfully create an integrated circuit using a fully photolithographic process in a home lab, building a dual differential amplifier using entirely homebrew equipment. Hobbyists around the world have been making discrete circuits at home for years, but integrated circuits are a significantly trickier matter. Engineers like Jeri ...

Blink Demo

by Fatsie on Chips4Makers.io
Intro In order to show the progress I made on the Retro-uC a short video is presented with a demo with the Retro-uC running on an FPGA. For the demo an Alorium XLR8, a Velleman VMA201 proto shield and a Dangerous Prototypes BusPirate V3.6 were used. On the proto shield LEDs and accompanying resistors have been soldered on the D2-D9 Arduino IOs. The Retro-uC core used has the Z80 and the MOS6502 and a JTAG interface. In the video below a demo is giving by blinking the LEDs on the proto ...

OTA: LimeSDR Cases, HDSDR and GNU Radio Support, SDR Hacks, and More

by Gareth Halfacree on Myriad
Fulfilment of the LimeSDR Mini pre-orders continues, with the optional aluminium cases for the bundles having gone through assembly and testing ready for Crowd Supply to send them on. Delivered late last week and pictured in a campaign update, the LimeSDR Mini aluminium cases are designed to provide protection for the LimeSDR Mini without obstructing any of the ports – including the reference clock input/output connectors on the underside of the printed circuit board, which remains ...

Sam Zeloof Creates First Fully Photolithographic Homebrew IC

by Gareth Halfacree on FOSSi – AB Open
Engineer Sam Zeloof has become, to common knowledge, the first person to successfully create an integrated circuit using a fully photolithographic process in a home lab, building a dual differential amplifier using entirely homebrew equipment. Hobbyists around the world have been making discrete circuits at home for years, but integrated circuits are a significantly trickier matter. Engineers like Jeri Ellsworth have succeeded in the past using conductive epoxy and other tricks for the ...

RISC-V QEMU Part 2: The RISC-V QEMU port is upstream

by Michael Clark on SiFive
QEMU 2.12.0 was released on April 24th 2018 and this version is the first official QEMU version to contain the RISC-V port. This is yet another milestone towards the development of the Open Source RISC-V tools on top of the recent acceptance of RISC-V in Linux kernel 4.15 in December last year and GLIBC 2.27 this past February. The QEMU RISC-V port was being developed and maintained out-of-tree for several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V Privileged ...

OnChip Unveils Itsy-Chipsy Ultra-Low-Cost IC Fabrication Platform

by Gareth Halfacree on FOSSi – AB Open
Colombia-based OnChip has unveiled an open-source platform which aims to do for custom semiconductor creation what services like OSH Park have done for circuit boards: Itsy-Chipsy. “Chip prototyping used to be prohibitive for small start-ups and academy until services like MOSIS brought down prices to few thousands dollars per mm² in technology nodes capable to run circuitry at moderated performance,” OnChip explains of the current state of the semiconductor art. “MOSIS runs a multi-project ...

RISC-V Foundation And Informa Announce First Annual RISC-V Summit In Silicon Valley And 2018 Workshop Schedule

by Carmen Soh on Events – RISC-V Foundation
To Support the Ecosystem’s Ongoing Growth and Increased Global Footprint, RISC-V Foundation Partners with KNect365 to Help Facilitate Events in 2018 and Beyond Berkeley, Calif. – April 23, 2018 – The RISC-V Foundation, a non-profit corporation controlled by its members to drive forward the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced, in partnership with Informa’s Knowledge & Networking Division,  KNect365, the RISC-V ...

OSHCamp 2018 Schedule Finalised and Registration Opened Up

by Gareth Halfacree on FOSSi – AB Open
The Open Source Hardware User Group (OSHUG) has announced the schedule for OSHCamp 2018, to take place in Lincoln’s The Blue Room on the 30th of June and 1st July. Announced via a call for participation back in January, the Open Source Hardware Camp (OSHCamp) 2018 is to take place in Lincoln, once home to noted engine builders Ruston & Hornsby – a company which still lives on as Siemens, following a route via GEC and English Electric. As with previous years, OSHCamp 2018 is split across two ...

CRU: Neural Networks, Open Baseband, RISC-V, and More

by Gareth Halfacree on FOSSi – AB Open
It’s been a strong fortnight for machine intelligence fans, starting with Arm’s Robert Elliot and Mark O’Conner publishing a white paper on the company’s Arm NN machine learning platform and its optimisations for use on low-power embedded devices. “We expect machine learning to become a natural part of programming environments, with tiny embedded neural networks being part of program execution,” the pair explain of the inspiration behind Arm NN. “To prepare for this, we’ve developed a ...

RISC-V Workshop in Barcelona

by Carmen Soh on Events – RISC-V Foundation
teaser image RISC-V Workshop in Barcelona 7-10 May, 2018 Co-hosted By Co-sponsored By   The RISC-V Foundation invites you to attend the RISC-V Workshop in Barcelona, Spain on 7-10 May, 2018. Co-hosted by the Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC), and co-sponsored by NXP and Western Digital, the RISC-V Workshop in Barcelona will gather the RISC-V ecosystem to share notable RISC-V updates, projects and implementations. Keynote sessions will include Robert ...

chisel 3.1.0

by Jim Lawson on Chisel
We’ve just published Chisel v3.1.0 and FIRRTL v1.1.0 and compatible updates to the rest of the BIG5 Chisel projects – chisel-testers v1.2.0, firrtl-interpreter v1.1.0, and dsptools v1.1.0. This release is essentially a copy of the RC2 candidate. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is welcome.

SeL4 Microkernel v9.0.1 Ported to RISC-V

by Gareth Halfacree on FOSSi – AB Open
The open-source seL4 microkernel, the first general-purpose kernel to have been proven to-spec using formal verification methods, has been ported to the open RISC-V instruction set architecture – though its creators warn it’s in a very early, limited form. Originally developed by Australia’s National Information and Communications Technology (ICT) Research Centre of Excellence (NICTA) and now under the stewardship of Data61’s Trustworthy Systems Group, the seL4 microkernel is a ...

Rambus Announces RISC-V CryptoManager Security Core

by Gareth Halfacree on FOSSi – AB Open
Rambus has become the latest company to adopt the open RISC-V instruction set architecture (ISA), using its openness as the basis for a new embedded and Internet of Things (IoT) security core dubbed the CryptoManager Root of Trust. “The fundamental pillars of architectural design freedom, secure processing siloed away from general processing, and layered security with a root of trust designed for multiple security layers, are unique to the CryptoManager Root of Trust design and enable easy ...

RISC-V Foundation Announces Agenda For Workshop In Barcelona

by Carmen Soh on Events – RISC-V Foundation
Workshop features more than 30 tutorials, presentations, networking receptions and a tour of the Barcelona Supercomputing Center WHAT: RISC-V Workshop in Barcelona, Spain WHERE: Universitat Politècnica de Catalunya, Campus Nord, Vertex Building Auditorium WHEN: Monday, May 7 to Wednesday, May 9, 2018 DETAILS: Co-hosted by the Barcelona Supercomputing Center and the Universitat Politècnica de Catalunya (UPC), the RISC-V Workshop in Barcelona gathers the RISC-V ecosystem to share notable ...

Dover Microsystems Brings Real-Time Chip Security to SiFive’s DesignShare

by Shafy Eltoukhy, head of DesignShare on SiFive
Boy have we been busy. Over the last few months, our DesignShare ecosystem has continued to expand, and, this week, we were excited to welcome Dover Microsystems into the program. Through DesignShare, developers now have access to Dover Microsystems’ CoreGuard Silicon IP, which enables processors to defend themselves in real-time from all network-based attacks. CoreGuard prevents illegal instructions from executing before any damage can be done. Its security rules define the difference ...

The SiFive Download - The Next Revolution is Here!

by Jack Kang, vice president of product marketing, SiFive on SiFive
First, we are thrilled to have recently announced that we raised $50.6 million in our Series C funding round! We wanted to thank our existing and new investors - including Chengwei Capital, Huami, SK Telecom and Western Digital - for the continued support and new engagement, so we held a party to celebrate! Check out the full newsletter here!

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Last updated 16 July 2018 20:00 UTC