Planet LibreCores

Microsoft Opens Zipline Hardware-Implementable Compression Algorithm

by Gareth Halfacree on FOSSi – AB Open
Microsoft’s cloud computing division, Azure, has announced the release of its hardware-implementable compression algorithm Project Zipline under a permissive licence, as part of the Open Compute project (OCP). “Microsoft’s Project Zipline compression algorithm yields dramatically better results, up to 2X high compression ratios versus the commonly used Zlib-L4 64KB model,” claims Microsoft’s Kushagra Vaid. “Enhancements like this can lead to direct customer benefits in the potential for ...

OTA: LimeNET Micro Upgrades, Es’hail-2 Transmissions, and More

by Gareth Halfacree on MyriadRF
Backers of the LimeNET Micro are set to receive a boost in computing power and storage thanks to a last-minute switch in Raspberry Pi Compute Module model, while shipping has now been pushed to the end of March. “As you all know, there were quite a few changes to the original specification and we decided to go for USB transceiver interfacing, fully active PoE, and add camera and display LVDS interfaces, as well as a HDMI connector,” explains Lime Micro’s Zydrunas Tamosevicius in a campaign ...

Tom Verbeure’s Deep-Dive Into WD’s SweRV RISC-V Core

by Gareth Halfacree on FOSSi – AB Open
Tom Verbeure has published comments on a deep-dive of the Western Digital SweRV open-source RISC-V core, following a workshop at the Bay Area RISC-V Meetup earlier this year. Announced late last year and released under a permissive licence in January, the SweRV Core is Western Digital’s open-source implementation of the RISC-V instruction set architecture (ISA). It was also the subject of a deep-dive workshop at the Bay Area RISC-V Meetup, and it’s details from this workshop on which Tom ...

The First Leg of our Global Symposiums is a Wrap, and it was an Enormous Success!

by Purvi Shenoy on SiFive
teaser image We welcomed over 600 attendees to the SiFive Tech Symposiums in Austin, Mountain View and Boston. The feedback we received is flattering. We heard comments like, “You guys are going bold, and we love it!” and “SiFive has built a solid team with good breadth of business and technology expertise,” and “Very different take – and someone is addressing the pain point for hardware folks, finally!” There was a great deal of energy in the crowd, and people were thoroughly engaged all day long. ...

Calista Redmond Named as RISC-V Foundation CEO

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has announced the appointment of IBM alumnus Calista Redmond as chief executive officer, taking over from interim chief Martin Fink. Calista Redmond’s work history includes 20 years of senior-level management and alliance experience at companies including Affinity Lab and Articulated Impact, including 12 years at IBM where she was most recently the vice president of the IBM Z Ecosystem division and, prior to that, the president of the OpenPOWER Foundation. “I’ve always ...

El Correo Libre Issue 13

by Gareth Halfacree on LibreCores - Medium
teaser image FOSSi Hits the Prime Time Last week I visited a small RISC-V themed workshop in Munich, Germany — or so I thought. When I showed up there, a crowd of over 50 people from industry and academia was eager to hear what RISC-V is all about, and how open source offerings could make their lives easier. This clearly show that, even though FOSSi has been with us for a long time, it is now ready for prime time. Companies are thinking hard about how they could replicate the success of open source ...

Linux Foundation to Launch FOSSi-Focused CHIPS Alliance

by Gareth Halfacree on FOSSi – AB Open
The Linux Foundation has launched a new group, dubbed the CHIPS Alliance, through which it hopes to support the burgeoning free and open source silicon (FOSSi) ecosystem. Officially announced today by the Linux Foundation, the CHIPS Alliance includes as founding members Esperanto, SiFive, and Western Digital – all of whom have announced or shipped products based around the open RISC-V instruction set architecture (ISA) – alongside cloud and consumer computing giant Google. “Open ...

Seeed Details RISC-V Raspberry Pi AI HAT, Development Board

by Gareth Halfacree on FOSSi – AB Open
Seeed Studio has announced a new Grove AI HAT for the Raspberry Pi, designed for edge computing projects, based around the Sipeed MAIX-I 64-bit RISC-V system-on-module (SOM) – and, interestingly, it will also function as a standalone development board. Unveiled on the official Seeed forum by Elaine Wu, the new design uses the full-size Hardware Attached on Top (HAT) form factor to connect to a Raspberry Pi single-board computer via its 40-pin GPIO header. Its primary feature: a Sipeed ...

CRU: Amazon, Imagination Bet on RISC-V, Google Targets Edge Acceleration, and More

by Gareth Halfacree on FOSSi – AB Open
Amazon has announced that it has added support for the RISC-V open instruction set architecture (ISA) to the MIT-licensed FreeRTOS real-time operating system kernel. “RISC-V is a free and open ISA that was designed to be simple, extensible, and easy to implement. The simplicity of the RISC-V model, coupled with its permissive BSD licence, makes it ideal for a wide variety of processors, including low-cost microcontrollers that can be manufactured without incurring licence costs,” Amazon’s ...

FuseSoC 1.9.1 Brings Improved, Sphinx-Generated Documentation

by Gareth Halfacree on FOSSi – AB Open
Olof Kindgren has announced the release of FuseSoC 1.9.1, and it brings with it improved documentation produced using the Sphinx Python Documentation Generator. Having a useful end product should be the primary goal of all open-source projects, but it shouldn’t be viewed as the only goal: no matter how useful a tool may be, if it’s not usable it may as well not exist. Documentation is key to accessibility, and all-too-often overlooked – which is why Olof’s work to improve the documentation ...

Linux Kernel 5.0 Launches with New RISC-V Features, Fixes

by Gareth Halfacree on FOSSi – AB Open
Linus Torvalds has announced the release of Linux 5.0, the latest version of the Linux kernel, and once again it pulls in a range of improvements and new features for the RISC-V instruction set architecture (ISA). Linux has boasted support for the open RISC-V ISA for a while, now, to the point where it’s possible to build a fully-functional desktop using off-the-shelf hardware. That doesn’t mean there isn’t still work to do, however, and the launch of the Linux 5.0 kernel brings with it a ...

FOSSi Foundation Selected as Google Summer of Code Mentor Organisation

by Gareth Halfacree on FOSSi – AB Open
The Free and Open Source Silicon (FOSSi) Foundation has announced it has been selected once again to be a mentor organisation in the Google Summer of Code (GSoC) programme, and is looking for students to participate. A not-for-profit organisation founded with the aim of promoting and assisting with the development and deployment of free and open source silicon solutions, the FOSSi Foundation’s participation in the Google Summer of Code programme will see it acting as a mentor organisation ...

OTA: Es’hail 2’s Amateur Transponder, Cellular Satcom, Magma, and More

by Gareth Halfacree on MyriadRF
The amateur transponder on board the Es’hail-2 satellite, launched back in November, has been activated and qualified as ready for amateur use – and use it amateurs most certainly are. Launched in November 2018 by Qatari communications company Es’hailSat, the Es’hail 2 satellite is located at 25.5 degrees East and carries a 2.4 GHz Phase 4 transponder, a 10.45 GHz Phase 4 transponder, 250 kHz linear transponder, and an 8 MHz transponder for experimental digital modulation schemes and ...

Amazon Adds RISC-V Support to FreeRTOS Kernel

by Gareth Halfacree on FOSSi – AB Open
Amazon has announced that it has added support for the RISC-V open instruction set architecture (ISA) to the MIT-licensed FreeRTOS real-time operating system kernel. “RISC-V is a free and open ISA that was designed to be simple, extensible, and easy to implement. The simplicity of the RISC-V model, coupled with its permissive BSD licence, makes it ideal for a wide variety of processors, including low-cost microcontrollers that can be manufactured without incurring licence costs,” Amazon’s ...

Imagination, Andes Partner on Wireless RISC-V Microcontroller Product

by Gareth Halfacree on FOSSi – AB Open
Imagination Technologies and Andes Technology have announced a partnership to combine the former’s Ensigma wireless intellectual property (IP) with the latter’s RISC-V N22 microcontroller IP in order to create an off-the-shelf product aimed at the Internet of Things (IoT) sector. The collaboration between the two companies marks the first time Imagination has shown interest in the RISC-V market; previously, the company’s general purpose processing products had centred around the proprietary ...

Become a GSoC student 2019!

by FOSSi Foundation on FOSSi Foundation - News & Posts
We are happy and honored to be part of the Google Summer of Code (GSoC) again this year. We are a mentoring organization and serve as an umbrella organization for many projects related to open source silicon design, open source EDA tools and the related ecosystem. Google Summer of Code is an excellent program for students to get a stipend by Google to work on open source projects. To start things off, we have prepared a list of project ideas. As a student you are free to base your project ...

GreenWaves’ €7m Series A Round Shows Hunger for RISC-V, FOSSi

by Gareth Halfacree on FOSSi – AB Open
GreenWaves Technologies, which launched the GAP8 RISC-V low-power processor and GAPuino development board in February last year, has announced that it has raised €7 million in Series A funding – a clear demonstration of the startling growth in the free and open source silicon (FOSSi) market. “This support from a distinguished group of corporate investors demonstrates the GAP processor family’s unique value proposition within this emerging market,” claims Loic Lietar, GreenWaves co-founder ...

Announcing Latch-Up in Portland, Oregon

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image The FOSSi Foundation is proud to announce Latch-Up (latchup.io), a conference dedicated to free and open source silicon to be held over the weekend of May 4th and 5th in Portland, Oregon, USA. Latch-Up opens a new chapter for the FOSSi Foundation, with it being the first event in the spirit of ORConf held in North America. Latch-Up is a community-focused conference for open source semiconductor, digital design and embedded systems professionals and enthusiasts. Expect presentations on a ...

Reolink Argus Pro and Argus 2 Security Camera Installation and Review

by kevinhub88 on Black Mesa Labs
teaser image 2019.02.22 This blog is a quick setup guide and evaluation of the Reolink Argus family of solar powered motion activity security cameras.  I purchased both the Argus Pro and the Argus 2 which vary primarily only in the low light image sensor used. Installation manual was downloaded from here.  Goal of this blog is to provide a simple setup guide and a camera evaluation for use in an external security scenario for capturing both pedestrians on a sidewalk and car license plates entering a ...

CRU: Open ISA Events, New RISC-V & LoRaWAN Parts, IoT Regulation, and More

by Gareth Halfacree on FOSSi – AB Open
AB Open’s Andrew Back has published a piece on building a personal computer based on the RISC-V instruction set architecture (ISA), using a custom-designed housing containing a SiFive HiFive Unleashed development board and Microsemi Expansion Board. “While it’s clear that the most significant opportunities for RISC-V will be in democratising custom silicon for accelerating specific tasks and enabling new applications — and it’s already driving a renaissance in novel computer architectures, ...

DVCon 2019 to Host Panel Discussion on Open ISAs’ Impact on Verification and Compliance

by Gareth Halfacree on FOSSi – AB Open
The Design and Verification Conference (DVCon) 2019 is to host a panel on the verification and compliance implications of open instruction set architectures (ISAs) like RISC-V, organised by industry expert Imperas. Dubbed “Verification and Compliance in the Era of Open ISA – Is the Industry Ready to Address the Coming Tsunami of Innovation,” the panel is to be organised by Imperas’ Larry Lapides, moderated by Tirias Research’s Kevin Krewell, and feature Andes Technology’s Emerson Hsiao, ...

The RISC-V Revolution is Going Global This Month, you can join SiFive in Austin, Mountain View, or Boston

by Swamy Irrinki on SiFive
In 2018, we hosted several RISC-V technology symposia in India, China and Israel. These events were very successful in fueling the growing momentum surrounding the RISC-V ISA in these countries. It turns out that these events were just the tip of the iceberg. In 2019, SiFive is greatly expanding its reach by hosting over 50 SiFive Tech Symposia in cities throughout the world. The first leg of the global tour begins in the USA. In collaboration with our co-hosts and partner companies, we aim ...

RISC-V Workshop Zurich Call for Speakers Now Open

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has issued a call for speakers ahead of the RISC-V Workshop Zurich, scheduled for mid-June 2019, with a submission deadline of the 28th of February. Hosted by the non-profit RISC-V Foundation in partnership with Informa’s Knowledge & Networking Division, KNect365, the RISC-V Workshop Zurich is to be held at ETH Zürich on the 11th to 13th of June 2019 as one of several events around the globe dedicated to the promotion of the free and open source instruction set ...

WCH Adds Upcoming RISC-V Bluetooth LE Microcontroller to CH57x Family

by Gareth Halfacree on FOSSi – AB Open
Embedded news site CNXSoft has highlighted an upcoming part from Jiangsu Qinheng Co., Ltd, also known as WinChipHead (WCH), which combines a RISC-V core running at 60MHz with Bluetooth Low Energy (BLE) connectivity. Recently added to WCH’s parts list, the 32-bit microcontroller has been dubbed the CH572 – putting it into the same CH57x family as the company’s Arm Cortex-M0 microcontroller offerings – and is claimed to run at 60MHz. Full details haven’t yet been supplied by the company, but ...

Seeed Studio Stocks Sub-$18 RISC-V Sipeed Tang Primer FPGA Board

by Gareth Halfacree on FOSSi – AB Open
Internet of Things (IoT)-focused components provider Seeed Studio has begun stocking the Sipeed Tang Primer FPGA development board, a sub-$18 part which features an Anlogic EG4S20 FPGA running a RISC-V soft core. Designed to offer a full RISC-V implementation in a very small form factor, the Tang is based around the Anlogic EG4S20 field-programmable gate array (FPGA) with 20,000 logic units, around 130KB of SRAM, and 64Mb of SDRAM on a 32-bit bus. The board also includes 8Mb user-accessible ...

OTA: MarconISSta Deinstalled, LimeSDR 35km Barefoot Transmission, RPi CNI, and More

by Gareth Halfacree on MyriadRF
teaser image The MarconISSta mission, which saw a LimeSDR and Raspberry Pi installed on the International Space Station (ISS), has successfully completed its first phase and has been safely deinstalled and stowed. “MarconISSta was deinstalled on Saturday, February 9th 2019, by NASA astronaut Anne McClain,” writes project lead Martin Buscher in what is the last live mission update from phase one. “The system is stowed in a safe location and waits for MarconISSta phase II, which we currently plan for not ...

Hailey Lynne McKeefry on the Procurement Benefits of Open Source Hardware

by Gareth Halfacree on FOSSi – AB Open
EBN editor-in-chief Hailey Lynne McKeefry has penned a piece pointing to the considerable benefits of open hardware, and in particular the RISC-V instruction set architecture (ISA), to the procurement process. “It’s clear that open source hardware will have a ripple effect, not just on design, but also on procurement practices,” Hailey writes, citing industry experts including RISC-V Foundation executive director Rick O’Connor and Wave Computing’s Art Swift. “With so many organisations ...

“Arm’s Days Could Be Numbered,” Claims RISC-V Vendor

by Gareth Halfacree on FOSSi – AB Open
EE Times correspondent Nitin Dahad has pointed to growing troubles for embedded processing giant Arm, and the source should be of no surprise: the growing tide of free and open source silicon (FOSSi) designs, including RISC-V. That the ability to literally clone a GitHub repository and have a fully-working processor design ready to use or modify with no royalties or restrictive licensing is causing something of a revolution in the semiconductor industry is no secret – RISC-V pioneer ...

El Correo Libre Issue 12

by Gareth Halfacree on LibreCores - Medium
teaser image FOSSi Foundation Applies to Join Google Summer of Code 2019 The Free and Open Source Silicon Foundation has announced its application for a mentorship position in the Google Summer of Code (GSoC) programme, as part of its efforts towards expanding and improving the ecosystem. “In the Google Summer of Code, Google grants students a scholarship to contribute to open source projects over the summer,” explains Foundation director Stefan Wallentowitz. “The FOSSi Foundation applies as an umbrella ...

Building a RISC-V PC

by Andrew Back on FOSSi – AB Open
teaser image How we assembled a RISC-V desktop computer. (video at the bottom of this post.) While it’s clear that the most significant opportunities for RISC-V will be in democratising custom silicon for accelerating specific tasks and enabling new applications — and it’s already driving a renaissance in novel computer architectures, for e.g. IoT and edge processing — one question that people cannot help but ask is, so when can I have a RISC-V PC? The answer to which is, right now. The SiFive HiFive ...

CRU: Wuthering Bytes 2019 Planning, SweRV RISC-V Released, and More

by Gareth Halfacree on FOSSi – AB Open
AB Open is pleased to announce a call for participation (CFP) in Wuthering Bytes, the annual community technology festival it produces, seeking those interested in hosting a talk, workshop, roundtable, or other event between Friday the 30th of August and Sunday the 8th of September. Wuthering Bytes — produced by AB Open as part of its contribution to the community — has grown considerably from the first event, held at Hebden Bridge Town Hall, in 2013: Wuthering Bytes 2017 saw attendees ...

RISC-V Growth Showcased by Bumper Embedded World 2019 Showing

by Gareth Halfacree on FOSSi – AB Open
The free and open-source silicon (FOSSi) ecosystem continues to grow, and nowhere will that growth be more obvious than at the Embedded World 2019 conference this year where 17 companies will be exhibiting RISC-V implementations and supporting technologies alone. Due to take place at the NürnbergMesse, Germany, from Tuesday the 26th of February to Thursday the 28th of February, Embedded World 2019 is to play host to a booth from the RISC-V Foundation which will include pods from members ...

OTA: PiTop SDR Upgrade, Osmocom, srsLTE Updates, and More

by Gareth Halfacree on Myriad
A video demonstrating the integration of a LimeSDR Mini with the modular, Raspberry Pi-based PiTop laptop has been released – and all it took was a few laser-cut parts. “The PiTop is a rather cool modular laptop that you build yourself and which is based around the Raspberry Pi platform. Eminently hackable, we thought it would be fun to see if we could integrate a LimeSDR Mini for software-defined radio development on the move,” explains Andrew Back in the latest video update to the LimeSDR ...

RISC-V Foundation Announces OpenSBI 0.1 Release

by Gareth Halfacree on FOSSi – AB Open
An initial implementation of an open supervisor binary interface (SBI) for RISC-V, imaginatively dubbed OpenSBI v0.1, has been released with support for the HiFive Unleashed, Kendryte K210-based development boards, and QEMU virtual machines. “OpenSBI is an open source implementation of the RISC-V Supervisor Binary Interface (SBI). SBI serves a critical purpose, enabling an operating system to interact with the supervisor execution environment (SEE),” explains the RISC-V Foundation of the ...

OTA: PiTop SDR Upgrade, Osmocom, srsLTE Updates, and More

by Gareth Halfacree on MyriadRF
A video demonstrating the integration of a LimeSDR Mini with the modular, Raspberry Pi-based PiTop laptop has been released – and all it took was a few laser-cut parts. “The PiTop is a rather cool modular laptop that you build yourself and which is based around the Raspberry Pi platform. Eminently hackable, we thought it would be fun to see if we could integrate a LimeSDR Mini for software-defined radio development on the move,” explains Andrew Back in the latest video update to the LimeSDR ...

Verilator - Verilator 4.010 Released

by Wilson Snyder on Veripool: News
Verilator 4.010 2019-01-27 Removed --trace-lxt2, use --trace-fst instead. For --xml, add additional information, bug1372. [Jonathan Kimmitt] Add circular typedef error, bug1388. [Al Grant] Add unsupported for loops error, msg2692. [Yu Sheng Lin] Fix FST tracing of wide arrays, bug1376. [Aleksander Osman] Fix error when pattern assignment has too few elements, bug1378. [Viktor Tomov] Fix error when no modules in $unit, bug1381. [Al Grant] Fix missing too ...

Western Digital Releases SweRV RISC-V Core Source Code

by Gareth Halfacree on FOSSi – AB Open
Storage giant Western Digital has officially released the source code for its SweRV RISC-V core, under the permissive Apache 2.0 Licence, allowing anyone to run, experiment with, or modify its implementation. Announced back in December, SweRV is a RISC-V core implementation developed in-house as part of Western Digital’s aim to transition its storage processing products away from proprietary cores and onto the free and open instruction set architecture (ISA). “Our SweRV Core and the new ...

Embedded Intelligence Everywhere

by Jack Kang on SiFive
teaser image In 2018, we saw the rapid proliferation of the RISC-V architecture, with commercial deployments of SiFive Core IP in a broad range of applications ranging from wearables and edge devices to the enterprise core. Modern compute workloads are evolving rapidly and require the ability to scale performance on demand and very often have real-time, deterministic requirements. This diversity of workloads poses computational challenges that can be resolved only by domain-specific architectures. With ...

CRU: RISC-V’s Bumper Year, LoRaWAN Growth, cocotb 1.1, and More

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has released a video highlighting some of the key features of the 2018 RISC-V Summit, held in Santa Clara late last year and attended by over 1,100 community members. To say that the free and open source silicon (FOSSi) movement in general and RISC-V in particular had a banner year is no exaggeration: in 2018 we saw Ethernet support added to lowRISC, Future ship its first RISC-V FPGA dev board, Esperanto announce its 4,112-core RISC-V AI accelerator, SiFive announce ...

Verilog-Perl - Verilog-Perl 3.454 Released

by Wilson Snyder on Veripool: News
Verilog::Language 3.454 2018-08-21 Support parsing around Cadence protected meta-comments. Fix define argument stringification (`"), broke since 3.446. [Joe DErrico] Fix to ignore Unicode UTF-8 BOM sequences, msg2576. [HyungKi Jeong]

Cocotb Testbench Hits 1.1, Promises More Rapid Release Schedule

by Gareth Halfacree on FOSSi – AB Open
Cocotb, the Coroutine-based Cosimulation TestBench for verifying Verilog or VHDL register-transfer level (RTL) designs using Python, has reached its version 1.1 release – and brings with it the promise of a more rapid and streamlined release schedule for the future. “This release is the culmination of work done by 50 contributors over a little less than four years,” explains Philipp Wagner of the release. “During that time we merged 242 pull requests, resulting in 257 files changed, with ...

Chisel/FIRRTL Digest: 2018 Year-in-review

by Schuyler Eldridge on Chisel
Contributors We’re extremely grateful for the growth of the developer community over the past year. We’ve seen 20 new contributors across 9 projects 1 in the Chisel/FIRRTL ecosystem. In addition, 17 previous contributors contributed again in 2018. Chisel, FIRRTL, and the broader ecosystem of projects is impossible without your involvement! Thank you! New ...

Semiconductor Engineering on RISC-V, FOSSi’s Growing Potential

by Gareth Halfacree on FOSSi – AB Open
Semiconductor Engineering’s Brian Bailey has published a piece on the growth of RISC-V, including comment from industry experts including SiFive’s Krste Asanovic and Microsemi’s Ted Speers – and the conclusion that 2019 will be a year of major design wins for the open instruction set architecture. Beginning with a look at the troubles besetting those clinging to Moore’s Law – the observation turned mandated development target by Intel co-founder Gordon Moore that the number of transistors ...

OTA: LimeSCAN Demo, GRCon18 Videos, Google Assistant via Ham, and More

by Gareth Halfacree on Myriad
The LimeNET Micro campaign has posted a demonstration of an alpha-status project dubbed LimeSCAN, taking advantage of the ability to run software defined radio and general purpose processing tasks on a single standalone unit to scan for radio spectrum usage data and share it via a private Ethereum blockchain. “The intention is for LimeSCAN to become a public resource for crowdsourced radio spectrum information, where anyone is free to operate a probe that uploads data, and to make use of ...

OTA: LimeSCAN Demo, GRCon18 Videos, Google Assistant via Ham, and More

by Gareth Halfacree on MyriadRF
The LimeNET Micro campaign has posted a demonstration of an alpha-status project dubbed LimeSCAN, taking advantage of the ability to run software defined radio and general purpose processing tasks on a single standalone unit to scan for radio spectrum usage data and share it via a private Ethereum blockchain. “The intention is for LimeSCAN to become a public resource for crowdsourced radio spectrum information, where anyone is free to operate a probe that uploads data, and to make use of ...

RISC-V Summit 2018 Highlight Video Celebrates a Banner Year

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has released a video highlighting some of the key features of the 2018 RISC-V Summit, held in Santa Clara late last year and attended by over 1,100 community members. To say that the free and open source silicon (FOSSi) movement in general and RISC-V in particular had a banner year is no exaggeration: in 2018 we saw Ethernet support added to lowRISC, Future ship its first RISC-V FPGA dev board, Esperanto announce its 4,112-core RISC-V AI accelerator, SiFive announce ...

CRU: Raspberry Pi Goes RISC-V, New FOSS Business Model, KiCon 2019, and More

by Gareth Halfacree on FOSSi – AB Open
Wave Computing has announced the MIPS Open initiative, under which it plans to make the instruction set architecture (ISA) available free of charge with no licensing or royalty payments required – a clear response to the growing popularity of the open RISC-V ISA. Wave Computing, which acquired MIPS from Imagination Technologies in June last year, has confirmed that MIPS Open will allow both 32-bit and 64-bit variants of the MIPS ISA to be adopted for research and commercial use with no ...

Design News Picks 2019 as “The Year of Open Source”

by Gareth Halfacree on FOSSi – AB Open
Design News’ Chris Wiltz has predicted that 2019 will be “the year of open source,” and while it’s hard to imagine the impact of open source software getting any greater than it already has it’s clear that the impetus behind open hardware is growing at an exponential pace. In the piece, which begins as a retrospective of the big moves in the world of free and open source software (FOSS) and open hardware throughout 2018, Chris points to what appears to have been an inflection point for open ...

El Correo Libre Issue 11

by Gareth Halfacree on LibreCores - Medium
teaser image The Year of Free and Open Source Silicon We wish all our readers a happy new year, and we hope you had some relaxing holidays. Looking back at 2018, it’s clear to see a further rise of Free and Open Source Silicon projects. We have, for example, seen many great things coming from the RISC-V ecosystem, as well as the SymbiFlow project, just to mention some of the most popular. Last year’s ORConf was another great success, and we were thrilled to host so many brilliant speakers and support ...

chisel 3.1.6

by Jim Lawson on Chisel
We’ve recently published Chisel v3.1.6 and FIRRTL v1.1.6 and compatible updates to the rest of the BIG6 Chisel projects – chisel-testers v1.2.8, firrtl-interpreter v1.1.6, treadle v1.0.4, and dsptools v1.1.7. This release of the tool set consists of bug fixes. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is welcome.

Raspberry Pi Foundation Announces RISC-V Foundation Membership

by Gareth Halfacree on FOSSi – AB Open
The Raspberry Pi Foundation has announced its membership of the RISC-V Foundation at the Silver Member tier, offering support for the instruction set architecture on a software – though not yet hardware – level. The original Raspberry Pi launched in February 2012 as a low-cost single-board computer (SBC) primarily targeting the hobbyist and educational market and based around a Broadcom BCM2835 single-core Arm system-on-chip. Originally developed for set-top box use, the Broadcom chip ...

OTA: SatNOGS Dashboard, Tempest Tutorial, Es’Hail 2 Update, and More

by Gareth Halfacree on Myriad
The 35th Chaos Communication Congress (35c3) played host to antenna engineer Friederike Maier, whose talk on software defined radio basics and modulation theory serves as a great introduction to the concepts for beginners. “Encoding or decoding random radio-waveforms doesn’t need incredible expensive hardware any more, which offers new possibilities for building up over-the-air communication systems,” Friederike explains. “There are Software Defined Radios providing affordable cellular ...

OTA: SatNOGS Dashboard, Tempest Tutorial, Es’Hail 2 Update, and More

by Gareth Halfacree on MyriadRF
The 35th Chaos Communication Congress (35c3) played host to antenna engineer Friederike Maier, whose talk on software defined radio basics and modulation theory serves as a great introduction to the concepts for beginners. “Encoding or decoding random radio-waveforms doesn’t need incredible expensive hardware any more, which offers new possibilities for building up over-the-air communication systems,” Friederike explains. “There are Software Defined Radios providing affordable cellular ...

VerilogCreator Tunes QtCreator IDE for FPGA Project Use

by Gareth Halfacree on FOSSi – AB Open
Engineers working on field-programmable gate array (FPGA) projects and looking for a friendly development environment to add to their toolchain now have a new option: the VerilogCreator plugin for QtCreator. Written by Rochus Keller and brought to our attention by Hackaday, VerilogCreator is designed to turn the QtCreator integrated development environment (IDE) into one suitable for working on Verilog 2005 projects, complete with syntax highlighting, code warnings and errors, jump-to ...

You Will Not Get Fired for Choosing RISC-V

by Camille Kokozaki on SiFive
teaser image Published by SemiWiki. These were the closing words Yunsup Lee, CTO, SiFive used at one of the December RISC-V Summit Keynotes entitled ‘Opportunities and Challenges of Building Silicon in the Cloud’. Fired up was more the mood among the 1000+ attendees of the RISC-V Summit held at the Santa Clara Convention Center and SiFive was among the companies showcasing their latest offerings, providing an update among the increasingly active and productive ecosystem blending open-source initiatives ...

Welcome - The SiFive Download, Part III

by Jack Kang on SiFive
Earlier this month, we took a huge step in democratizing access to custom silicon when we unveiled our newest core, the U54-MC Coreplex - the industry’s first RISC-V based, 64-bit, quadcore application processor with support for full featured operating systems including Linux, Unix and FreeBSD. Check out the full newsletter here!

Welcome - The SiFive Download, Part II

by Jack Kang on SiFive
On August 15, we announced that regarded industry veteran Naveed Sherwani has joined SiFive as CEO. We invited him to share his vision for the company and his optimism for fomenting a revolution in the semiconductor industry. Check out the full newsletter here!

The SiFive Download - What's Up Next?

by Jack Kang on SiFive
We recently announced that Intel Capital participated in our Series C funding round! Our CEO, Naveed Sherwani, revealed the investment earlier this month at the Intel Capital Global Summit. Check out the full newsletter here!

What's happing in the open silicon ecosystem around you? Planet LibreCores helps you to get the latest news from all corners of the community by aggregating blog posts.

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Last updated 18 March 2019 16:00 UTC