Planet LibreCores

RISC-V Summit 2018 Highlight Video Celebrates a Banner Year

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has released a video highlighting some of the key features of the 2018 RISC-V Summit, held in Santa Clara late last year and attended by over 1,100 community members. To say that the free and open source silicon (FOSSi) movement in general and RISC-V in particular had a banner year is no exaggeration: in 2018 we saw Ethernet support added to lowRISC, Future ship its first RISC-V FPGA dev board, Esperanto announce its 4,112-core RISC-V AI accelerator, SiFive announce ...

CRU: Raspberry Pi Goes RISC-V, New FOSS Business Model, KiCon 2019, and More

by Gareth Halfacree on FOSSi – AB Open
Wave Computing has announced the MIPS Open initiative, under which it plans to make the instruction set architecture (ISA) available free of charge with no licensing or royalty payments required – a clear response to the growing popularity of the open RISC-V ISA. Wave Computing, which acquired MIPS from Imagination Technologies in June this year, has confirmed that MIPS Open will allow both 32-bit and 64-bit variants of the MIPS ISA to be adopted for research and commercial use with no ...

Design News Picks 2019 as “The Year of Open Source”

by Gareth Halfacree on FOSSi – AB Open
Design News’ Chris Wiltz has predicted that 2019 will be “the year of open source,” and while it’s hard to imagine the impact of open source software getting any greater than it already has it’s clear that the impetus behind open hardware is growing at an exponential pace. In the piece, which begins as a retrospective of the big moves in the world of free and open source software (FOSS) and open hardware throughout 2018, Chris points to what appears to have been an inflection point for open ...

El Correo Libre Issue 11

by Gareth Halfacree on LibreCores - Medium
teaser image The Year of Free and Open Source Silicon We wish all our readers a happy new year, and we hope you had some relaxing holidays. Looking back at 2018, it’s clear to see a further rise of Free and Open Source Silicon projects. We have, for example, seen many great things coming from the RISC-V ecosystem, as well as the SymbiFlow project, just to mention some of the most popular. Last year’s ORConf was another great success, and we were thrilled to host so many brilliant speakers and support ...

chisel 3.1.6

by Jim Lawson on Chisel
We’ve recently published Chisel v3.1.6 and FIRRTL v1.1.6 and compatible updates to the rest of the BIG6 Chisel projects – chisel-testers v1.2.8, firrtl-interpreter v1.1.6, treadle v1.0.4, and dsptools v1.1.7. This release of the tool set consists of bug fixes. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is welcome.

Embedded Intelligence Everywhere

by Jack Kang on SiFive
teaser image In, 2018, we saw the rapid proliferation of the RISC-V architecture, with commercial deployments of SiFive Core IP in a broad range of applications ranging from wearables and edge devices to the enterprise core. Modern compute workloads are evolving rapidly and require the ability to scale performance on demand and very often have real-time, deterministic requirements. This diversity of workloads poses computational challenges that can be resolved only by domain-specific architectures. With ...

Raspberry Pi Foundation Announces RISC-V Foundation Membership

by Gareth Halfacree on FOSSi – AB Open
The Raspberry Pi Foundation has announced its membership of the RISC-V Foundation at the Silver Member tier, offering support for the instruction set architecture on a software – though not yet hardware – level. The original Raspberry Pi launched in February 2012 as a low-cost single-board computer (SBC) primarily targeting the hobbyist and educational market and based around a Broadcom BCM2835 single-core Arm system-on-chip. Originally developed for set-top box use, the Broadcom chip ...

OTA: SatNOGS Dashboard, Tempest Tutorial, Es’Hail 2 Update, and More

by Gareth Halfacree on Myriad
The 35th Chaos Communication Congress (35c3) played host to antenna engineer Friederike Maier, whose talk on software defined radio basics and modulation theory serves as a great introduction to the concepts for beginners. “Encoding or decoding random radio-waveforms doesn’t need incredible expensive hardware any more, which offers new possibilities for building up over-the-air communication systems,” Friederike explains. “There are Software Defined Radios providing affordable cellular ...

VerilogCreator Tunes QtCreator IDE for FPGA Project Use

by Gareth Halfacree on FOSSi – AB Open
Engineers working on field-programmable gate array (FPGA) projects and looking for a friendly development environment to add to their toolchain now have a new option: the VerilogCreator plugin for QtCreator. Written by Rochus Keller and brought to our attention by Hackaday, VerilogCreator is designed to turn the QtCreator integrated development environment (IDE) into one suitable for working on Verilog 2005 projects, complete with syntax highlighting, code warnings and errors, jump-to ...

You Will Not Get Fired for Choosing RISC-V

by Camille Kokozaki on SiFive
teaser image Published by SemiWiki. These were the closing words Yunsup Lee, CTO, SiFive used at one of the December RISC-V Summit Keynotes entitled ‘Opportunities and Challenges of Building Silicon in the Cloud’. Fired up was more the mood among the 1000+ attendees of the RISC-V Summit held at the Santa Clara Convention Center and SiFive was among the companies showcasing their latest offerings, providing an update among the increasingly active and productive ecosystem blending open-source initiatives ...

Welcome - The SiFive Download, Part III

by Jack Kang on SiFive
Earlier this month, we took a huge step in democratizing access to custom silicon when we unveiled our newest core, the U54-MC Coreplex - the industry’s first RISC-V based, 64-bit, quadcore application processor with support for full featured operating systems including Linux, Unix and FreeBSD. Check out the full newsletter here!

Welcome - The SiFive Download, Part II

by Jack Kang on SiFive
On August 15, we announced that regarded industry veteran Naveed Sherwani has joined SiFive as CEO. We invited him to share his vision for the company and his optimism for fomenting a revolution in the semiconductor industry. Check out the full newsletter here!

The SiFive Download - What's Up Next?

by Jack Kang on SiFive
We recently announced that Intel Capital participated in our Series C funding round! Our CEO, Naveed Sherwani, revealed the investment earlier this month at the Intel Capital Global Summit. Check out the full newsletter here!

The SiFive Download - The Next Revolution is Here!

by Jack Kang on SiFive
First, we are thrilled to have recently announced that we raised $50.6 million in our Series C funding round! We wanted to thank our existing and new investors - including Chengwei Capital, Huami, SK Telecom and Western Digital - for the continued support and new engagement, so we held a party to celebrate! Check out the full newsletter here!

The SiFive Download - Ringing in 2018 with Fresh Faces and Big Resolutions

by Jack Kang on SiFive
Before we dive into our newsletter, we want to take a moment to talk about the vulnerabilities around Meltdown and Spectre. First off -- and most fortunately -- SiFive’s RISC-V Core IP offerings are not affected by Meltdown and Spectre. Secondly, as the RISC-V Foundation’s statement on these vulnerabilities notes, now is the time for open architecture and open hardware designs to shine. Check out the full newsletter here!

The SiFive Download - Are you ready to UNLEASH your genius?

by Jack Kang on SiFive
We’re heading to the Embedded Linux Conference next week, March 12-14, to hold our first hackathon. Developers will be among the first to run code on the HiFive Unleashed board with a chance to take home a board of their own and win a $1,000 cash prize. Check out the full newsletter here!

The SiFive Download: A Year in Review

by Jack Kang on SiFive
Welcome to the first iteration of our bi-monthly newsletter, The SiFive Download! On a regular cadence, we will plan to give you a download on all things SiFive – from the events we will be attending to the articles we’ve been featured in. This newsletter is intended to give you a glimpse under the SiFive hood. Check out the full newsletter here!

RISC-V 101 Webinar

by Jack Kang on SiFive
This one-hour webinar is for Embedded Developers who are interested in learning more about the RISC-V architecture. It covers areas such as the Register File, Instruction Types, Modes, Interrupts, and Control and Status Registers. Prior knowledge of RISC-V is not necessary, but having a basic understanding of Computer Architecture is beneficial. Check out the webinar recording here!

OTA: LimeNET Micro Files, a Serial Adapter SDR Hack, Origami Filters, and More

by Gareth Halfacree on Myriad
The board design files for the LimeNET Micro v2.0, which includes expanded bandwidth for the radio portion as well as making more features of the Raspberry Pi Compute Module 3 available, have now been published to the Myriad-RF GitHub repository. First announced back in October, the LimeNET Micro v2.0 design’s primary change is to switch from the Serial Peripheral Interface (SPI) bus to USB for connectivity between the controlling Raspberry Pi Compute Module 3 and the LMS7002M ...

2018.1 Release: Linux, Debugging, Automation, and Tons of Fixes

by OpTiMSoC on OpTiMSoC
Woohoo! After more than two years of work and 479 git commits later we are very proud to present the all-new 2018.1 release of OpTiMSoC! A look at the statistics gives a first impression of how large this release is: diffstat tells us about 973 files changed, 133,697 lines inserted and 58,806 lines deleted. Or in other words, the code size increased by 74,891 lines! How do those lines of code translate into functionality, you may ask? Let’s have a closer look. Debug Infrastructure The ...

Thales, IIT Madras Partner for Fault-Tolerant SHAKTI RISC-V Processors

by Gareth Halfacree on FOSSi – AB Open
Thales, which recently became a member of the RISC-V Foundation, has announced a joint project with IIT Madras to develop a fault-tolerant version of the SHAKTI Project RISC-V CPU. “After the two successful fabrication and booting of SHAKTI with two technology nodes, 22nm (Intel Fab, Oregon USA) and 180nm (SCL Chandigarh fab, India), this tie-up with Thales is very exciting and certainly is a big step towards taking SHAKTI family to the global technology ecosystem,” claims Professor ...

Linux on OpTiMSoC: How many small steps unlock a whole new world

by OpTiMSoC on OpTiMSoC
teaser image Some projects we take upon ourselves are done quickly: start, do the work, profit. Others take a bit longer. And then there are these projects which seem to linger forever in an “almost done” state. Just one more small thing and we’ll be done. A small fix here. An extension to a module there. A new component elsewhere. And so it goes on, and on, and on. For days, for weeks, for years. Adding Linux support to OpTiMSoC is such a story. But there’s a happy end: Linux support has finally ...

Open Standards Work!

by Naveed Sherwani on SiFive
We are really excited to see Wave Computing announce the open MIPS ISA and R6 processor core. SiFive would like to congratulate and welcome MIPS to the open-source community with its MIPS Open Initiative. The addition of the MIPS 32 and 64-bit open ISA will provide more options freely available to SoC designers. The open-source processor community, based on the RISC-V ISA, is thriving, and the addition of MIPS underscores the fact that the world is indeed becoming more open. Open ISA ...

Wave Computing Announces MIPS Open Initiative

by Gareth Halfacree on FOSSi – AB Open
Wave Computing has announced the MIPS Open initiative, under which it plans to make the instruction set architecture (ISA) available free of charge with no licensing or royalty payments required – a clear response to the growing popularity of the open RISC-V ISA. Wave Computing, which acquired MIPS from Imagination Technologies in June this year, has confirmed that MIPS Open will allow both 32-bit and 64-bit variants of the MIPS ISA to be adopted for research and commercial use with no ...

Code with Confidence: OpTiMSoC Always Works!

by OpTiMSoC on OpTiMSoC
teaser image OpTiMSoC is a highly complex system. If all goes to plan, software, hardware and tooling work together to form a well-integrated SoC (framework). But as so often, the reality is less gloomy: changing a single line of code anywhere could lead to trouble anywhere else. Finding out about breakages only weeks of months after the fact makes debugging a nightmare. [1] Not any more. After multiple years of despair and a lot of work we can finally say with confidence: “OpTiMSoC always works!” In ...

Bluespec Launches Commercially-Supported Flute RISC-V Cores

by Gareth Halfacree on FOSSi – AB Open
RISC-V specialist Bluespec Inc. has announced its second RISC-V processor design, Flute, which it is making available as basic cores ahead of future releases which will include additional instructions for Linux and FreeRTOS compatibility. The follow-up to Bluespec’s existing Piccolo core, Flute is currently available in RV32IMU and RV64IMASU implementations with a floating-point and compressed-instruction variant supporting Linux and FreeRTOS operating systems to follow. The core uses a ...

chisel 3.1.5

by Jim Lawson on Chisel
Well, that was quick. We’ve discovered a regression in FIRRTL 1.1.4 (FIRRTL issue 972) The issue is fixed with FIRRTL v1.1.5 and we’ve published Chisel v3.1.5 and and compatible updates to the rest of the BIG6 Chisel projects – chisel-testers v1.2.7, firrtl-interpreter v1.1.5, treadle v1.0.3, and dsptools v1.1.6.  

chisel 3.1.4

by Jim Lawson on Chisel
We’ve just published Chisel v3.1.4 and FIRRTL v1.1.4 and compatible updates to the rest of the BIG6 Chisel projects – chisel-testers v1.2.6, firrtl-interpreter v1.1.4, treadle v1.0.2, and dsptools v1.1.5. This release of the tool set consists of bug fixes, performance improvements and some new features. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is ...

CRU: Free RISC-V Boards, Security in the FOSSi Era, and More

by Gareth Halfacree on FOSSi – AB Open
OpenISA has officially launched the VEGAboard microcontroller development board, based on the PULP Platform’s RI5CY and Zero-RI5CY RISC-V core, and it’s giving them away to encourage adoption of the free instruction set architecture (ISA). Developed in partnership with the Parallel Ultra Low Power (PULP) Platform, Express Logic, Foundries.io, Ashling, IAR Systems, and Segger, the OpenISA VEGAboard is powered by an NXP Semiconductors RV32M1 chip which combines Arm Cortex-M0 and Cortex-M4 ...

Round-Table Discusses RISC-V, FOSSi Impact on Hardware Security

by Gareth Halfacree on FOSSi – AB Open
Semiconductor Engineering’s Ed Sperling has published extracts of a round-table with Rambus’ Helena Handschuh, Microsemi’s Richard Newell, and Galois’ Joseph Kiniry on the impact the open RISC-V instruction set architecture (ISA) can have on security. “With open source, you have the opportunity to review it and come up with comments, feed it back to the community, and as a group you can advance maybe not faster but better,” explains Handschuh. “You have more hands. Everybody is available to ...

El Correo Libre Issue 10

by Gareth Halfacree on LibreCores - Medium
teaser image RISC-V Foundation Names Summit SoftCPU Contest Winners The RISC-V Foundation has named the four winners of the SoftCPU Contest, held as part of the RISC-V Summit, with the Free and Open Source Silicon Foundation’s Olof Kindgren receiving the Creativity Prize for a RISC-V implementation dubbed SERV. “The RISC-V ISA is ushering in a new era of innovation, empowering companies and designers around the world to develop a wide variety of implementations that solve today’s most complex design ...

Tom Verbeure on the VexRiscV CPU: “A New Way to Design”

by Gareth Halfacree on FOSSi – AB Open
Engineer Tom Verbeure has written up an analysis of the VexRiscV CPU, a RISC-V design implemented using the novel SpinalHDL hardware description language (HDL) – an approach he describes as being “as efficient as the most optimised Verilog, yet at the same time extremely configurable.” First-prize winner in the recent RISC-V Soft-Core CPU Contest, VexRiscV eschews traditional development methodologies in favour of using the novel SpinalHDL language – a Scala library providing hardware ...

OTA: A Mysterious Signal, FPV Antenna Gimbals, Fox-1Cliff, and More

by Gareth Halfacree on Myriad
Popular software package SDR-Console is set to get transmit support on the LimeSDR range, from version 3.0.4 onwards – once beta testing is complete. The new feature of SDR-Console v3.0.4 was teased by Jason Fairfax on Twitter late last month. “Calling CQ SSB on 144.300 MHz from IO81rk,” he wrote. “Hint: SDR-Console v3.0.4 beta now has TX support for the LimeSDR.” During testing, Jason found the LimeSDR’s internal clock suitable for use on FT8/WSJT with no need for an external clock ...

Microsemi, SiFive Launch Linux-Compatible RISC-V PolarFire SoC

by Gareth Halfacree on FOSSi – AB Open
Microsemi has announced a new system-on-chip (SoC) architecture which combines the company’s PolarFire low-power field-programmable gate arrays (FPGAs) with a complete RISC-V processor implementation for use with Linux platforms. Developed in partnership with RISC-V pioneer SiFive, the PolarFire SoC includes an asymmetric coherent CPU cluster with four 64-bit RV64GC RISC-V cores and one RV64IMAC monitor core, connected to a 2MB Layer 2 memory subsystem via a coherent switch, then on to a ...

Western Digital Unveils Open SweRV RISC-V Core

by Gareth Halfacree on FOSSi – AB Open
Western Digital has unveiled its first in-house RISC-V core, dubbed SweRV, and it has confirmed plans to release it under an open source licence early next year. Part of a company initiative, started in 2017, to switch from proprietary instruction set architectures (ISAs) to the open RISC-V ISA across its storage processing products, Western Digital’s SweRV marks the company’s first public announcement of an in-house processing core. Based on the 32-bit RISC-V variant and designed for ...

PULP, OpenPiton Partner on OpenPiton+Ariane Design

by Gareth Halfacree on FOSSi – AB Open
The OpenPiton project has announced a partnership with the PULP Platform to combine the OpenPiton open-source research processor platform with the 64-bit Ariane RISC-V core, creating what is described as “the ideal permissive open-source RISC-V system.” The Parallel Ultra Low Power (PULP) Platform announced Ariane, a 64-bit application-class RISC-V design, back in February, while the OpenSPARC-based OpenPiton research processor reached Release 7 in June. Now, with Release 10, OpenPiton is ...

OpenISA Launches New, Free RISC-V VEGAboard

by Gareth Halfacree on FOSSi – AB Open
OpenISA has officially launched the VEGAboard microcontroller development board, based on the PULP Platform’s RI5CY and Zero-RI5CY RISC-V core, and it’s giving them away to encourage adoption of the free instruction set architecture (ISA). Developed in partnership with the Parallel Ultra Low Power (PULP) Platform, Express Logic, Foundries.io, Ashling, IAR Systems, and Segger, the OpenISA VEGAboard is powered by an NXP Semiconductors RV32M1 chip which combines Arm Cortex-M0 and Cortex-M4 ...

Verilator - Verilator 4.008 Released

by Wilson Snyder on Veripool: News
Verilator 4.008 2018-12-01 Support "ref" and "const ref" pins and functions, bug1360. [Jake Longo] In --xml-only show the original unmodified names, and add module_files and cells similar to Verilog-Perl, msg2719. [Kanad Kanhere] Add CONTASSREG error on continuous assignments to regs, bug1369. [Peter Gerst] Add PROCASSWIRE error on behavioral assignments to wires, msg2737. [Neil Turton] Add IMPORTSTAR warning on import::* inside $unit scope. Fix --trace-lxt2 ...

CRU: RISC-V Growth, Transprecision Funding, Reverse-Engineering, and More

by Gareth Halfacree on FOSSi – AB Open
Princeton University’s OpenPiton free and open source silicon (FOSSi) project has announced what is claimed to be the world’s first open-source, general-purpose, heterogeneous-ISA processor: JuxtaPiton. Built by combining the SPARC v9-based OpenPiton with Clifford Wolf’s PicoRV32 RISC-V core, JuxtaPiton is something unique. “JuxtaPiton inherits all of the capabilities of OpenPiton, with the added ability to instantiate chosen tiles with RISC-V cores, rather than the usual OpenSPARC T1 core, ...

Announcing OpenPiton with Ariane

by Jonathan Balkind on OpenPiton Blog
teaser image We have great news for fans of open source hardware: The Princeton Parallel Group led by David Wentzlaff, and the Digital Circuits and Systems Group of ETH Zürich led by Luca Benini have joined forces to bring you the OpenPiton open-source research processor platform with first-class support for 64-bit Ariane RISC-V cores. The latest update of the open-source Ariane processor, (Ariane IV) now supports the P-Mesh cache system from OpenPiton, and with today’s OpenPiton release 10 ...

RISC-V Foundation, Linux Foundation Join Forces for a “New Era of Open Architecture”

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation and the Linux Foundation have announced a joint initiative which they claim will “enable a new era of open architecture” and “accelerate open source development and adoption of the RISC-V ISA [Instruction Set Architecture].” “With the rapid international adoption of the RISC-V ISA, we need increased scale and resources to support the explosive growth of the RISC-V ecosystem. The Linux Foundation is an ideal partner given the open source nature of both organisations,” ...

Verilator - RISC-V Contest Chooses Verilator

by Wilson Snyder on Veripool: News
The 2018 RISC-V design contest has announced all submissions must be submitted only using Verilator. The contest is to design a RISC-V soft CPU core, run by the RISC-V Foundation, and is sponsored by Google, Antmicro, Lattice Semiconductor and Microsemi. For more details see https://riscv.org/2018contest/

Thales Joins RISC-V Foundation, Praises ISA’s Protection from “Cyber Threats”

by Gareth Halfacree on FOSSi – AB Open
Thales Group, best known for its work in aerospace, defence, transportation, and security, has announced it has joined the RISC-V Foundation, declaring its commitment to “free, open-source hardware architectures based on RISC-V processors.” Founded in 2000 as the next stage from 1968-founded Thomson-CSF, which in turn was an evolution of Compagnie Française Thomson-Houston (CFTH) founded in 1893, Thales’ primary work is in high-security markets. That security focus, the company has ...

The Retro-uC is death - long live the Retro-uC !

by Fatsie on Chips4Makers.io
teaser image Retro-uC's death ? Last month the Retro-uC crowdfunding campaign ended without reaching it's funding goal. I do regret that it did not reach it's goal but I did learn some things: The typical retro-computing guy is not very interested in Arduino type maker stuff. He wants to assemble and program a system with CPU, memory and peripherals. One chip with just GPIO outputs is not really getting him exciting. The prospect of an open silicon movement is not attractive enough for Arduino loving ...

JuxtaPiton Merges OpenSPARC, RISC-V Soft-cores

by Gareth Halfacree on FOSSi – AB Open
Princeton University’s OpenPiton free and open source silicon (FOSSi) project has announced what is claimed to be the world’s first open-source, general-purpose, heterogeneous-ISA processor: JuxtaPiton. Built by combining the SPARC v9-based OpenPiton with Clifford Wolf’s PicoRV32 RISC-V core, JuxtaPiton is something unique. “JuxtaPiton inherits all of the capabilities of OpenPiton, with the added ability to instantiate chosen tiles with RISC-V cores, rather than the usual OpenSPARC T1 core, ...

OTA: LimeNET Micro v2.0, mmWave-to-Optical Breakthrough, Satellite News, and More

by Gareth Halfacree on Myriad
The LimeNET Micro has received a few upgrades since its crowdfunding campaign, now in its last two weeks, launched, including considerably improved RF bandwidth, active Power-over-Ethernet (PoE), and both DSI and HDMI display connectivity. Designed to meld the LimeSDR with the Raspberry Pi Compute Module 3 to create a fully-standalone software defined radio (SDR) and general-purpose processing (GPP) platform, the LimeNET Micro as originally designed saw the LMS7002M field-programmable radio ...

JuxtaPiton: Taking OpenPiton Heterogeneous with RISC-V

by Jonathan Balkind on OpenPiton Blog
teaser image What is JuxtaPiton? JuxtaPiton is (to our knowledge) the world’s first open-source, general-purpose, heterogeneous-ISA processor. It is an enhancement to OpenPiton, built by integrating the PicoRV32 RISC-V core, written by Clifford Wolf, into the OpenPiton framework. JuxtaPiton inherits all of the capabilities of OpenPiton, with the added ability to instantiate chosen tiles with RISC-V cores, rather than the usual OpenSPARC T1 core, which uses the SPARC v9 ISA. The PicoRV32 core is ...

CRU: RISC-V Security, GraphQL Foundation, lowRISC 0.6, and More

by Gareth Halfacree on FOSSi – AB Open
Esperanto Technologies, a company focused on developing energy-efficient many-core accelerators for artificial intelligence and machine learning applications, has announced the closure of a whopping $58 million in Series B funding – more than 10 times its previous investment rounds combined. “Despite still operating largely in stealth mode, we appreciate this strong show of support from strategic and VC investors who had confidential briefings about our plans and believe we have a ...

Getting Started with Zephyr RTOS v1.13.0 On RISC-V

by Nathaniel Graff on SiFive
teaser image Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architectures, and targets including SiFive's E-series CoreIP, and the HiFive 1 development board. I'm particularly excited about this release because it incorporates recent work making the RISC-V port of ...

Sipeed Launches Crowdfunder for RISC-V MAIX AI Dev Boards

by Gareth Halfacree on FOSSi – AB Open
Chinese electronics company Sipeed has launched a crowdfunding campaign for a range of development boards based on a Kendryte K210 dual-core 64-bit RISC-V processor, aiming to bring artificial intelligence (AI) processing to edge devices and with pricing starting at $5 per board. “Sipeed MAIX is the first RV64 AI board for edge computing,” the boards’ creator Sipeed explains. “It makes AI embedded to any IoT [Internet of Things] device possible. MAIX [boards] have tons of exciting features: ...

lowRISC 0.6 Release Brings Performance, Documentation, Ethernet Improvements

by Gareth Halfacree on FOSSi – AB Open
The lowRISC project has announced the release of version 0.6 of its open silicon offering, bringing improvements to performance, debugging, and network connectivity – alongside a pledge to add alternative RISC-V cores to the current Rocket option. Ten months after the release of lowRISC 0.5 brought initial support for Ethernet connectivity, lowRISC’s 0.6 milestone release offers a wealth of improvements. “This release includes an updated version of the Rocket RISC-V core, a higher core ...

El Correo Libre Issue 9

by Gareth Halfacree on LibreCores - Medium
teaser image ORConf 2018 Videos and Slides Now Available As detailed in our last El Correo Leibre newsletter, the recently-held ORConf 2018 event was a great success, with many fantastic talks, hallway discussions, and valuable insights into other projects relating to the free and open source silicon ecosystem. If you were unable to attend, if you need a refresher on how great the talks were, or if you are looking for archival copies for future reference, don’t despair: the videos and slides from the ...

lowRISC 0-6 milestone release

by LowRISC on lowRISC
The lowRISC 0.6 milestone release is now available. This release includes an updated version of the Rocket RISC-V core, a higher core clock frequency, JTAG debugging support, Ethernet improvements, and more. See the release notes, for full details. We’ve also taken the opportunity to re-organise our documentation, adding an easy to follow quick-start guide. Our next development focus is to add support for dropping in the Ariane RISC-V design (from ETH Zurich) as an alternative to ...

OTA: LimeNET Micro Improved, AfriCUBE, Reviving Analogue Cellphones, and More

by Gareth Halfacree on Myriad
The LimeNET Micro crowdfunding campaign continues, and has brought with it a welcome change to the design which will greatly increase the radio’s available bandwidth and sample rate while also adding support for camera and display accessories. Announced via a crowdfunding campaign late last month, the LimeNET Micro is the latest entry in the LimeNET family of open all-in-one software defined radio (SDR) basestation hardware. Based on the same technology as the LimeSDR, the LimeNET Micro ...

Hex Five, Andes, Gowin Collaborate on MultiZone Security Implementation

by Gareth Halfacree on FOSSi – AB Open
Hex Five Security, Andes Technology, and Gowin Semiconductor have jointly announced a collaboration which will see the former’s trusted execution environment added to the middle’s N(X)25 RISC-V cores on the latter’s GW-2A field programmable gate array (FPGA) family. “The cost of a robust security implementation on RISC-V is now negligible – the future of RISC-V is security by default,” claims Don Barnetson, co-founder of Hex Five Security, of the company’s MultiZone Security which it has ...

GCC Upstream for 9.0.0

by OpenRISC Community on OpenRISC
We are proud to announce that the OpenRISC port for gcc has been committed to upstream. Mainline OpenRISC support will be available in the upcoming 9.0.0 release of GCC. Note, this has been a clean room rewrite of the OpenRISC gcc port. The old port can still be found in the OpenRISC github repo. Pre-release toolchain binaries for the new toolchain can be found on Stafford’s github releases page. There are a few things still not supported in this new port which were available the ...

Videos and slides from ORConf 2018 now available!

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image ORConf 2018 was a great success, with many fantastic talks, hallway discussions, and valuable insights into other projects. If you couldn’t attend, or if you need a refresher on how great the talks were, don’t dispair: the videos and slides are now available online! Thanks to the hard work of Simon Cook who did all the video editing, you can watch (almost) all talks on our YouTube channel. The slides are also available online for most talks, find them next to the talk descriptions on the ...

RISC-V AI Accelerator Specialist Esperanto Closes $58m Funding Round

by Gareth Halfacree on FOSSi – AB Open
Esperanto Technologies, a company focused on developing energy-efficient many-core accelerators for artificial intelligence and machine learning applications, has announced the closure of a whopping $58 million in Series B funding – more than 10 times its previous investment rounds combined. “Despite still operating largely in stealth mode, we appreciate this strong show of support from strategic and VC investors who had confidential briefings about our plans and believe we have a ...

What's happing in the open silicon ecosystem around you? Planet LibreCores helps you to get the latest news from all corners of the community by aggregating blog posts.

All content here is unfiltered and uncensored, and represents the views of the post authors. Individual posts are owned by their authors; please see the original source for licensing information.

Subscribe to Planet LibreCores

In addition to reading the posts here, you can subscribe to Planet LibreCores in your favorite feed reader.

Planet Librecores Atom feed

Or get the subscription list through FOAF or OPML.

Last updated 15 January 2019 23:30 UTC