Planet LibreCores

CRU: RISC-V Security, GraphQL Foundation, lowRISC 0.6, and More

by Gareth Halfacree on FOSSi – AB Open
Esperanto Technologies, a company focused on developing energy-efficient many-core accelerators for artificial intelligence and machine learning applications, has announced the closure of a whopping $58 million in Series B funding – more than 10 times its previous investment rounds combined. “Despite still operating largely in stealth mode, we appreciate this strong show of support from strategic and VC investors who had confidential briefings about our plans and believe we have a ...

Getting Started with Zephyr RTOS v1.13.0 On RISC-V

by Nathaniel Graff on SiFive
teaser image Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architectures, and targets including SiFive's E-series CoreIP, and the HiFive 1 development board. I'm particularly excited about this release because it incorporates recent work making the RISC-V port of ...

Sipeed Launches Crowdfunder for RISC-V MAIX AI Dev Boards

by Gareth Halfacree on FOSSi – AB Open
Chinese electronics company Sipeed has launched a crowdfunding campaign for a range of development boards based on a Kendryte K210 dual-core 64-bit RISC-V processor, aiming to bring artificial intelligence (AI) processing to edge devices and with pricing starting at $5 per board. “Sipeed MAIX is the first RV64 AI board for edge computing,” the boards’ creator Sipeed explains. “It makes AI embedded to any IoT [Internet of Things] device possible. MAIX [boards] have tons of exciting features: ...

lowRISC 0.6 Release Brings Performance, Documentation, Ethernet Improvements

by Gareth Halfacree on FOSSi – AB Open
The lowRISC project has announced the release of version 0.6 of its open silicon offering, bringing improvements to performance, debugging, and network connectivity – alongside a pledge to add alternative RISC-V cores to the current Rocket option. Ten months after the release of lowRISC 0.5 brought initial support for Ethernet connectivity, lowRISC’s 0.6 milestone release offers a wealth of improvements. “This release includes an updated version of the Rocket RISC-V core, a higher core ...

El Correo Libre Issue 9

by Gareth Halfacree on LibreCores - Medium
teaser image ORConf 2018 Videos and Slides Now Available As detailed in our last El Correo Leibre newsletter, the recently-held ORConf 2018 event was a great success, with many fantastic talks, hallway discussions, and valuable insights into other projects relating to the free and open source silicon ecosystem. If you were unable to attend, if you need a refresher on how great the talks were, or if you are looking for archival copies for future reference, don’t despair: the videos and slides from the ...

lowRISC 0-6 milestone release

by LowRISC on lowRISC
The lowRISC 0.6 milestone release is now available. This release includes an updated version of the Rocket RISC-V core, a higher core clock frequency, JTAG debugging support, Ethernet improvements, and more. See the release notes, for full details. We’ve also taken the opportunity to re-organise our documentation, adding an easy to follow quick-start guide. Our next development focus is to add support for dropping in the Ariane RISC-V design (from ETH Zurich) as an alternative to ...

OTA: LimeNET Micro Improved, AfriCUBE, Reviving Analogue Cellphones, and More

by Gareth Halfacree on Myriad
The LimeNET Micro crowdfunding campaign continues, and has brought with it a welcome change to the design which will greatly increase the radio’s available bandwidth and sample rate while also adding support for camera and display accessories. Announced via a crowdfunding campaign late last month, the LimeNET Micro is the latest entry in the LimeNET family of open all-in-one software defined radio (SDR) basestation hardware. Based on the same technology as the LimeSDR, the LimeNET Micro ...

Hex Five, Andes, Gowin Collaborate on MultiZone Security Implementation

by Gareth Halfacree on FOSSi – AB Open
Hex Five Security, Andes Technology, and Gowin Semiconductor have jointly announced a collaboration which will see the former’s trusted execution environment added to the middle’s N(X)25 RISC-V cores on the latter’s GW-2A field programmable gate array (FPGA) family. “The cost of a robust security implementation on RISC-V is now negligible – the future of RISC-V is security by default,” claims Don Barnetson, co-founder of Hex Five Security, of the company’s MultiZone Security which it has ...

GCC Upstream for 9.0.0

by OpenRISC Community on OpenRISC
We are proud to announce that the OpenRISC port for gcc has been committed to upstream. Mainline OpenRISC support will be available in the upcoming 9.0.0 release of GCC. Note, this has been a clean room rewrite of the OpenRISC gcc port. The old port can still be found in the OpenRISC github repo. Pre-release toolchain binaries for the new toolchain can be found on Stafford’s github releases page. There are a few things still not supported in this new port which were available the ...

Videos and slides from ORConf 2018 now available!

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image ORConf 2018 was a great success, with many fantastic talks, hallway discussions, and valuable insights into other projects. If you couldn’t attend, or if you need a refresher on how great the talks were, don’t dispair: the videos and slides are now available online! Thanks to the hard work of Simon Cook who did all the video editing, you can watch (almost) all talks on our YouTube channel. The slides are also available online for most talks, find them next to the talk descriptions on the ...

RISC-V AI Accelerator Specialist Esperanto Closes $58m Funding Round

by Gareth Halfacree on FOSSi – AB Open
Esperanto Technologies, a company focused on developing energy-efficient many-core accelerators for artificial intelligence and machine learning applications, has announced the closure of a whopping $58 million in Series B funding – more than 10 times its previous investment rounds combined. “Despite still operating largely in stealth mode, we appreciate this strong show of support from strategic and VC investors who had confidential briefings about our plans and believe we have a ...

GNU Radio Foundation Launches Interest Check for London Symposium

by Gareth Halfacree on Myriad
GNU Radio Foundation president Ben Hilburn has launched a questionnaire to gauge interest in a UK event for GNU Radio users and developers, tentatively titled the GNU Radio Symposium, which would run along with the existing European GNU Radio Days and GNU Radio Conference events. Originally developed by Eric Blossom and first released in 2001, the open-source GNU Radio software development toolkit has become one of the most popular ways to develop for software defined radio (SDR) platforms ...

CRU: RISC-V Grows Apace, RTOS Vulnerabilities Patched, and More

by Gareth Halfacree on FOSSi – AB Open
The IIT Madras SHAKTI Project has celebrated a major milestone this month: the first boot of a RISC-V processor both designed and manufactured within its native India. Launched in 2014 with a focus on IBM’s Power instruction set architecture (ISA) before switching to the open-source RISC-V ISA, the Shakti Project has already celebrated a number of breakthroughs: First-boot on its homebrew silicon occurred back in July this year, having been manufactured by US semiconductor giant Intel on a ...

SiFive Launches New E7, S7, U7 RISC-V Cores

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneer SiFive has announced a new family of processor cores, the Core IP 7 Series, which it claims are “the highest performance commercially available RISC-V cores” and which come in hard-real-time, performance, and Linux-capable variants. “The SiFive Core IP 7 Series represents a major advancement in RISC-V. The 7 Series brings features to market that have been in-demand but unavailable to customers,” claims SiFive’s Jack Kang of his company’s latest launch. “SiFive offers the ...

Getting Started with Zephyr RTOS v1.13.0 On RISC-V

by Nathaniel Graff on SiFive
teaser image Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architectures, and targets including SiFive's E-series CoreIP, and the HiFive 1 development board. I'm particularly excited about this release because it incorporates recent work making the RISC-V port of ...

SHAKTI Project Boots Linux on Home-Grown 180nm RISC-V Silicon

by Gareth Halfacree on FOSSi – AB Open
The IIT Madras SHAKTI Project has celebrated a major milestone this month: the first boot of a RISC-V processor both designed and manufactured within its native India. Launched in 2014 with a focus on IBM’s Power instruction set architecture (ISA) before switching to the open-source RISC-V ISA, the Shakti Project has already celebrated a number of breakthroughs: First-boot on its homebrew silicon occurred back in July this year, having been manufactured by US semiconductor giant Intel on a ...

Verilator - Verilator 4.006 Released

by Wilson Snyder on Veripool: News
Verilator 4.006 2018-10-27 Add --pp-comments, msg2700. [Robert Henry] Add --dump-defines. For --trace-fst, save enum decoding information, bug1358. [Sergi Granell] (To visualize enumeration data you must use GTKwave 3.3.95 or newer.) For --trace-fst, instead of *.fst.hier, put data into *.fst. [Tony Bybell] Fix --trace-lxt2 compile error on MinGW, msg2667. [HyungKi Jeong] Fix Windows .exe not found, bug1361. [Patrick Stewart]

S3 Semi’s Edel Griffith Busts Custom Silicon Myths

by Gareth Halfacree on FOSSi – AB Open
S3 Semiconductors’ Edel Griffith has published a piece on Electronic Design busting 11 myths about custom silicon, from production of application-specific integrated circuits (ASICs) being too expensive for lower-volume projects and fear of a so-called “black-box design” process. Designed to encourage companies to look more closely at custom and semi-custom silicon design, whereby application-specific parts are designed and produced to vastly improve efficiency over general purpose ...

OTA: LimeNET Micro, OpenAirInterface, OsmoCon 2018 Videos, and More

by Gareth Halfacree on Myriad
Lime Microsystems has launched a crowdfunding campaign for the LimeNET Micro, an all-in-one device which combines the LMS7002M field-programmable radio frequency (FPRF) chip with a Raspberry Pi Compute Module 3, bringing the LimeNET family to its lowest price point yet. Designed with narrowband applications in mind, the LimeNET Micro operates from 10 MHz to 3.5 GHz – the same frequency range as the LimeSDR Mini – with a 1 MSPS sample rate at a 12-bit depth. Its transmit and receive channels ...

Last Week in RISC-V: October 12, 2018

by Palmer Dabbelt on SiFive
This week's entry is fairly short, but it does come with one major improvement: we now have a mailing list! I've decided to create a Google Group at SiFive, and while I understand that's not ideal it's the best I can figure out for now. The Google Groups interface is quick clunky, so if you're looking for archives it's probably still best to use GitHub. Hopefully this makes it easier for people to find the mailing list. I've copied this message to various RISC-V mailing lists, but won't ...

Last Week in RISC-V: October 12, 2018

by Palmer Dabbelt on SiFive
This week's entry is fairly short, but it does come with one major improvement: we now have a mailing list! I've decided to create a Google Group at SiFive, and while I understand that's not ideal it's the best I can figure out for now. The Google Groups interface is quick clunky, so if you're looking for archives it's probably still best to use GitHub. Hopefully this makes it easier for people to find the mailing list. I've copied this message to various RISC-V mailing lists, but won't ...

Last Week in RISC-V: October 19, 2018

by Palmer Dabbelt on SiFive
It's been another week, which means it's time to find another host for "Last Week in RISC-V". This week we're going to attempt a blog at riscv.org, which will hopefully be a good long-term home for this series of articles. As usual, you can find this week's entry on GitHub. glibc Floating-Point Test Suite As part of the RV32I glibc submission process, Zong from Andes has submitted a glibc patch set to fix a generic floating-point bug that crosses the boundary between GCC and glibc. ...

Last Week in RISC-V: October 19, 2018

by Palmer Dabbelt on SiFive
It's been another week, which means it's time to find another host for "Last Week in RISC-V". This week we're going to attempt a blog at riscv.org, which will hopefully be a good long-term home for this series of articles. As usual, you can find this week's entry on GitHub. glibc Floating-Point Test Suite As part of the RV32I glibc submission process, Zong from Andes has submitted a glibc patch set to fix a generic floating-point bug that crosses the boundary between GCC and glibc. ...

Last Week in RISC-V: Sept 28, 2018

by Palmer Dabbelt on SiFive
I spent too much time writing my single entry this week so it's all I have. The issue itself is somewhat complex, so I thought it warranted a deep dive. Relaxing R_RISCV_PCREL_* in the Presence of Addends Jim recently found an issue with our ELF relocation scheme. While technically it's a somewhat wide-ranging ABI bug, the actual set of cases in which the issue will manifest is somewhat restricted -- in other words: while I'm sure the proper long-term fix for this will be quite involved, ...

Last Week in RISC-V: Sept 28, 2018

by Palmer Dabbelt on SiFive
I spent too much time writing my single entry this week so it's all I have. The issue itself is somewhat complex, so I thought it warranted a deep dive. Relaxing R_RISCV_PCREL_* in the Presence of Addends Jim recently found an issue with our ELF relocation scheme. While technically it's a somewhat wide-ranging ABI bug, the actual set of cases in which the issue will manifest is somewhat restricted -- in other words: while I'm sure the proper long-term fix for this will be quite involved, ...

Dover Microsystems Brings Real-Time Chip Security to SiFive’s DesignShare

by Shafy Eltoukhy on SiFive
Boy have we been busy. Over the last few months, our DesignShare ecosystem has continued to expand, and, this week, we were excited to welcome Dover Microsystems into the program. Through DesignShare, developers now have access to Dover Microsystems’ CoreGuard Silicon IP, which enables processors to defend themselves in real-time from all network-based attacks. CoreGuard prevents illegal instructions from executing before any damage can be done. Its security rules define the difference ...

Dover Microsystems Brings Real-Time Chip Security to SiFive’s DesignShare

by Shafy Eltoukhy on SiFive
Boy have we been busy. Over the last few months, our DesignShare ecosystem has continued to expand, and, this week, we were excited to welcome Dover Microsystems into the program. Through DesignShare, developers now have access to Dover Microsystems’ CoreGuard Silicon IP, which enables processors to defend themselves in real-time from all network-based attacks. CoreGuard prevents illegal instructions from executing before any damage can be done. Its security rules define the difference ...

Analog Bits Clocks into the DesignShare Ecosystem

by Jack Kang on SiFive
Our DesignShare family is growing, and we’re thrilled to announce that Analog Bits, the industry’s leading provider of low-power mixed-signal IP solutions, is now a part of the ecosystem. System designers will have access to Analog Bits’ precision clocking macros such as PLLs and SERDES IP available for the SiFive Freedom platforms through DesignShare. Analog Bits has become an important supplier of differentiated IP embedded in SoC devices and has been instrumental in spawning the mobile ...

Analog Bits Clocks into the DesignShare Ecosystem

by Jack Kang on SiFive
Our DesignShare family is growing, and we’re thrilled to announce that Analog Bits, the industry’s leading provider of low-power mixed-signal IP solutions, is now a part of the ecosystem. System designers will have access to Analog Bits’ precision clocking macros such as PLLs and SERDES IP available for the SiFive Freedom platforms through DesignShare. Analog Bits has become an important supplier of differentiated IP embedded in SoC devices and has been instrumental in spawning the mobile ...

The DesignShare Ecosystem Expands Its Catalog of IP to include eMemory’s Logic NVM

by Jack Kang on SiFive
It’s been a fantastic few months for us with new initiatives and industry recognitions, and we’re excited to share more great news. Earlier this month, we welcomed eMemory, the IP provider of logic-based, non-volatile memory (Logic NVM), as the latest company to join the DesignShare movement! If you missed our previous blog post, DesignShare is a concept that opens a new range of applications and gives any company, inventor or maker the ability to harness the power of custom silicon. The ...

The DesignShare Ecosystem Expands Its Catalog of IP to include eMemory’s Logic NVM

by Jack Kang on SiFive
It’s been a fantastic few months for us with new initiatives and industry recognitions, and we’re excited to share more great news. Earlier this month, we welcomed eMemory, the IP provider of logic-based, non-volatile memory (Logic NVM), as the latest company to join the DesignShare movement! If you missed our previous blog post, DesignShare is a concept that opens a new range of applications and gives any company, inventor or maker the ability to harness the power of custom silicon. The ...

Last Week in RISC-V: Sept 21, 2018

by Palmer Dabbelt on SiFive
Introduction to Linux Kernel Development For those of you interested in getting involved in the RISC-V Linux kernel porting effort, I wrote a short email that links to the various sources of information that might help people get started. Developer Room at FOSDEM I submitted a proposal for a RISC-V developer room at FOSDEM next February. Last year our talk went great and a room was suggested, so I anticipate this will be accepted. We should officially hear back about the submission by the ...

Last Week in RISC-V: Sept 21, 2018

by Palmer Dabbelt on SiFive
Introduction to Linux Kernel Development For those of you interested in getting involved in the RISC-V Linux kernel porting effort, I wrote a short email that links to the various sources of information that might help people get started. Developer Room at FOSDEM I submitted a proposal for a RISC-V developer room at FOSDEM next February. Last year our talk went great and a room was suggested, so I anticipate this will be accepted. We should officially hear back about the submission by the ...

Last Week in RISC-V: Sept 7, 2018

by Palmer Dabbelt on SiFive
This is the last version of "Last Week in RISC-V" that I plan on sending to the various mailing lists, as we'll be posting the rest of them on SiFive's Blog. I didn't get any contributions, but I also haven't gotten through my email yet -- sorry if I missed anything that's been sent it, but I'm not too far behind so I should have everything read from this week by the end of next week. Linux 4.19-rc3 On Tuesday I tagged my pull request for Linux 4.19-rc3, which contains what I hope to be ...

Last Week in RISC-V: Sept 7, 2018

by Palmer Dabbelt on SiFive
This is the last version of "Last Week in RISC-V" that I plan on sending to the various mailing lists, as we'll be posting the rest of them on SiFive's Blog. I didn't get any contributions, but I also haven't gotten through my email yet -- sorry if I missed anything that's been sent it, but I'm not too far behind so I should have everything read from this week by the end of next week. Linux 4.19-rc3 On Tuesday I tagged my pull request for Linux 4.19-rc3, which contains what I hope to be ...

Last Week in RISC-V: August 31, 2018

by Palmer Dabbelt on SiFive
Welcome to the first issue of "Last Week in RISC-V", a weekly newsletter tracking the RISC-V community. This newsletter was born out of a discussion in SiFive's internal RISC-V software team and I'm compiling it so it'll have a somewhat heavy focus on the open source software community for now as that's where I spend most of my time. The general idea behind "Last Week in RISC-V" is that the RISC-V ecosystem is getting big enough that it's impossible for any single person to ...

Last Week in RISC-V: August 31, 2018

by Palmer Dabbelt on SiFive
Welcome to the first issue of "Last Week in RISC-V", a weekly newsletter tracking the RISC-V community. This newsletter was born out of a discussion in SiFive's internal RISC-V software team and I'm compiling it so it'll have a somewhat heavy focus on the open source software community for now as that's where I spend most of my time. The general idea behind "Last Week in RISC-V" is that the RISC-V ecosystem is getting big enough that it's impossible for any single person to ...

Last Week in RISC-V: Sept 14, 2018

by Palmer Dabbelt on SiFive
GNU Tools Cauldron Trip Report, Part 2 I was at the GNU tools cauldron last week. I summarized the two BoF sessions in last week's entry. While that was the extent of the RISC-V specific events at the cauldron, I attended the remainder of the cauldron where there were some great sessions. Vector ABI I attended the aarch64 BoF session, where one of the major issues at hand is to implement a system ABI that allows argument passing via SVE registers. This brought up a mirror in RISC-V land: ...

Last Week in RISC-V: Sept 14, 2018

by Palmer Dabbelt on SiFive
GNU Tools Cauldron Trip Report, Part 2 I was at the GNU tools cauldron last week. I summarized the two BoF sessions in last week's entry. While that was the extent of the RISC-V specific events at the cauldron, I attended the remainder of the cauldron where there were some great sessions. Vector ABI I attended the aarch64 BoF session, where one of the major issues at hand is to implement a system ABI that allows argument passing via SVE registers. This brought up a mirror in RISC-V land: ...

CRU: RISC-V Design Contest, Radio Spectrum Harmisation, Mbed Linux, and More

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has announced the launch of a design contest, in partnership with Google, Antmicro, and Microchip, which will see entrants competing to build the smallest and fastest RISC-V soft core implementations on field-programmable gate arrays (FPGAs). One of the biggest benefits of free and open source silicon (FOSSi) is that you are able to tweak and tailor its design to suit your own needs. To help demonstrate this, the RISC-V Foundation’s design contest is seeking engineers ...

SiFive Hosts Girl Geek X and Champions Custom Silicon For All

by Ali Sana on SiFive
teaser image On Wednesday, July 25th, SiFive had the pleasure of hosting Girl Geek X at our offices in San Mateo. Girl Geek X is a brilliant organization with the aim of connecting women across companies large and small for the purposes of networking and sharing career advice in the fast-paced tech industry. Over the past 10 years, Girl Geek X has grown from a 400-person dinner hosted by Google to a well-known Bay Area group with a membership base of more than 15,000. As the champions of innovation in ...

SiFive Hosts Girl Geek X and Champions Custom Silicon For All

by Ali Sana on SiFive
teaser image On Wednesday, July 25th, SiFive had the pleasure of hosting Girl Geek X at our offices in San Mateo. Girl Geek X is a brilliant organization with the aim of connecting women across companies large and small for the purposes of networking and sharing career advice in the fast-paced tech industry. Over the past 10 years, Girl Geek X has grown from a 400-person dinner hosted by Google to a well-known Bay Area group with a membership base of more than 15,000. As the champions of innovation in ...

Unleashing More Fun Under the Sun

by David Lee on SiFive
teaser image Good news, HiFive fans! A limited supply of HiFive Unleashed Development Kits are now available on CrowdSupply for purchase. Since the launch of HiFive Unleashed, many new capabilities are being enabled on the Freedom U540 SoC, the industry’s first RISC-V based, 64-bit quad-core application processor running Linux. The updated boards now support Debian and Fedora Linux, both of which enable developers to build a fully functional Linux PC with a modern desktop. Additionally, with the help of ...

Unleashing More Fun Under the Sun

by David Lee on SiFive
teaser image Good news, HiFive fans! A limited supply of HiFive Unleashed Development Kits are now available on CrowdSupply for purchase. Since the launch of HiFive Unleashed, many new capabilities are being enabled on the Freedom U540 SoC, the industry’s first RISC-V based, 64-bit quad-core application processor running Linux. The updated boards now support Debian and Fedora Linux, both of which enable developers to build a fully functional Linux PC with a modern desktop. Additionally, with the help of ...

A Look Back: 7th RISC-V Workshop

by Allen Leibovitch on SiFive
teaser image A new year brings new opportunities. Before we dive into 2018, we wanted to take some time to reflect on some of the excitement we experienced over the last couple of months. At the 7th RISC-V Workshop, we had the honor of partnering with some of the industry’s leading companies and announced the following at the workshop: An extended partnership with Microsemi: Microsemi and SiFive formed a strategic partnership to create and market a development board based on SiFive’s RISC-V based ...

A Look Back: 7th RISC-V Workshop

by Allen Leibovitch on SiFive
teaser image A new year brings new opportunities. Before we dive into 2018, we wanted to take some time to reflect on some of the excitement we experienced over the last couple of months. At the 7th RISC-V Workshop, we had the honor of partnering with some of the industry’s leading companies and announced the following at the workshop: An extended partnership with Microsemi: Microsemi and SiFive formed a strategic partnership to create and market a development board based on SiFive’s RISC-V based ...

The FE310 is in a Museum – Which is Pretty Cool

by Jack Kang on SiFive
teaser image It’s been quite busy the past month and change for SiFive and the RISC-V community. On May 4, we unveiled our RISC-V Core IP, radically redefining the process by which you can license and buy custom IP. The RISC-V Core IP launch was followed by a panel at Maker Faire Bay Area, where we got to chat with American computer engineering pioneer Dave Patterson and other panelists about RISC-V and the future of open-source hardware (pictured below). (From left to right: Dave Patterson, Jack Kang, ...

The FE310 is in a Museum – Which is Pretty Cool

by Jack Kang on SiFive
teaser image It’s been quite busy the past month and change for SiFive and the RISC-V community. On May 4, we unveiled our RISC-V Core IP, radically redefining the process by which you can license and buy custom IP. The RISC-V Core IP launch was followed by a panel at Maker Faire Bay Area, where we got to chat with American computer engineering pioneer Dave Patterson and other panelists about RISC-V and the future of open-source hardware (pictured below). (From left to right: Dave Patterson, Jack Kang, ...

An Ace Up Our Sleeve?

by Jack Kang on SiFive
teaser image In a recent post, Yunsup shared some of the successes and challenges we’ve faced in our first year as SiFive. Little did we know when that post went live, we’d be able to follow it up with yet another measure of success: Late last week, we learned that SiFive has been shortlisted as a finalist for UBM’s ACE Award for Startup of the Year! It is such an honor to receive this recognition of just how far our tightknit group has traveled since we first opened our doors in the summer of 2015. As ...

An Ace Up Our Sleeve?

by Jack Kang on SiFive
teaser image In a recent post, Yunsup shared some of the successes and challenges we’ve faced in our first year as SiFive. Little did we know when that post went live, we’d be able to follow it up with yet another measure of success: Late last week, we learned that SiFive has been shortlisted as a finalist for UBM’s ACE Award for Startup of the Year! It is such an honor to receive this recognition of just how far our tightknit group has traveled since we first opened our doors in the summer of 2015. As ...

Clifford Wolf launches Yosys Open Synthesis Suite 0.8

by Gareth Halfacree on FOSSi – AB Open
Developer Clifford Wolf has announced the release of Yosys 0.8, the latest version of the popular open synthesis suite framework, bringing with it a range of new improvements and bug fixes. Designed to ease register-transfer level (RTL) development, analysis, and formal verification for projects written in the Verilog hardware description language (HDL), Yosys – the Yosys Open Synthesis Suite – was first launched in 2012 as the first full-featured open-source package for Verilog HDL ...

Women in Open Source: You DO Belong Here

by Megan Wachs on SiFive
Hi. I’m Megan. And I’m a woman working on RISC-V hardware. The path that led me here is straightforward — I always pursued what sounded like the most fun and interesting path at the moment. I grew up in a family of engineers, with a mother who served as a wonderful role model. An engineer herself, she showed me that there’s nothing odd about a woman in tech. From a young age, my fascination with technology and how things work was deeply encouraged. I learned by osmosis because the tools ...

Why The Time is Right for Open Source Hardware and ‘Chips as a Service’

by Sander Arts on SiFive
The open source software movement has been credited as a key driver of the birth of the Internet Age. Without developments such as Linux; the free Apache Web-server platform; and tools such as Java, Perl and Ruby, the Web as we know it would likely not have been possible. Applying open source principles to hardware to develop new, disruptive systems isn’t a new concept. Garage hobbyists have long been reverse-engineering boards and devices for their home-grown projects. One of the most ...

Why Open Source is the New Way to Build Silicon

by Stefan Dyckerhoff on SiFive
It’s no secret the semiconductor industry is in a state of flux and consolidation. As a New York Times’ headline recently screamed, “Semiconductor Industry Shrinks Some More With Latest Deal.” In the month of July alone: Analog Devices snapped up Linear Technology; Cypress closed its acquisition of Broadcom’s IoT assets; Infineon bought Wolfspeed. And then there was the deal of all deals – SoftBank acquired ARM. This consolidation has made it even more difficult for system designers seeking ...

Welcome - The SiFive Download, Part III

by Jack Kang on SiFive
Earlier this month, we took a huge step in democratizing access to custom silicon when we unveiled our newest core, the U54-MC Coreplex - the industry’s first RISC-V based, 64-bit, quadcore application processor with support for full featured operating systems including Linux, Unix and FreeBSD. Check out the full newsletter [here]({{ page.external_link }})!

Welcome - The SiFive Download, Part II

by Jack Kang on SiFive
On August 15, we announced that regarded industry veteran Naveed Sherwani has joined SiFive as CEO. We invited him to share his vision for the company and his optimism for fomenting a revolution in the semiconductor industry. Check out the full newsletter [here]({{ page.external_link }})!

Welcome Aboard, Sunil Shenoy!

by Allen Leibovitch on SiFive
As our business continues to grow, the people we hire continue to impact and shape our business more and more. We had a chance to sit down our new VP of hardware engineering, Sunil Shenoy, to find out what attracted him to SiFive, how he hopes to grow the company and change the industry, and what his title really means. It’s been nearly a month since the announcement of your hiring. What is the most surprising thing you’ve seen/learned so far? It’s not so much a surprise, but what I am most ...

The SiFive Download - What's Up Next?

by Jack Kang on SiFive
We recently announced that Intel Capital participated in our Series C funding round! Our CEO, Naveed Sherwani, revealed the investment earlier this month at the Intel Capital Global Summit. Check out the full newsletter [here]({{ page.external_link }})!

The SiFive Download - The Next Revolution is Here!

by Jack Kang on SiFive
First, we are thrilled to have recently announced that we raised $50.6 million in our Series C funding round! We wanted to thank our existing and new investors - including Chengwei Capital, Huami, SK Telecom and Western Digital - for the continued support and new engagement, so we held a party to celebrate! Check out the full newsletter [here]({{ page.external_link }})!

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Last updated 19 November 2018 15:30 UTC