Planet LibreCores

Microsemi, SiFive Launch Linux-Compatible RISC-V PolarFire SoC

by Gareth Halfacree on FOSSi – AB Open
Microsemi has announced a new system-on-chip (SoC) architecture which combines the company’s PolarFire low-power field-programmable gate arrays (FPGAs) with a complete RISC-V processor implementation for use with Linux platforms. Developed in partnership with RISC-V pioneer SiFive, the PolarFire SoC includes an asymmetric coherent CPU cluster with four 64-bit RV46GC RISC-V cores and one RV64IMAC monitor core, connected to a 2MB Layer 2 memory subsystem via a coherent switch, then on to a ...

Western Digital Unveils Open SweRV RISC-V Core

by Gareth Halfacree on FOSSi – AB Open
Western Digital has unveiled its first in-house RISC-V core, dubbed SweRV, and it has confirmed plans to release it under an open source licence early next year. Part of a company initiative, started in 2017, to switch from proprietary instruction set architectures (ISAs) to the open RISC-V ISA across its storage processing products, Western Digital’s SweRV marks the company’s first public announcement of an in-house processing core. Based on the 32-bit RISC-V variant and designed for ...

PULP, OpenPiton Partner on OpenPiton+Ariane Design

by Gareth Halfacree on FOSSi – AB Open
The OpenPiton project has announced a partnership with the PULP Platform to combine the OpenPiton open-source research processor platform with the 64-bit Ariane RISC-V core, creating what is described as “the ideal permissive open-source RISC-V system.” The Parallel Ultra Low Power (PULP) Platform announced Ariane, a 64-bit application-class RISC-V design, back in February, while the OpenSPARC-based OpenPiton research processor reached Release 7 in June. Now, with Release 10, OpenPiton is ...

OpenISA Launches New, Free RISC-V VEGAboard

by Gareth Halfacree on FOSSi – AB Open
OpenISA has officially launched the VEGAboard microcontroller development board, based on the PULP Platform’s RI5CY and Zero-RI5CY RISC-V core, and it’s giving them away to encourage adoption of the free instruction set architecture (ISA). Developed in partnership with the Parallel Ultra Low Power (PULP) Platform, Express Logic, Foundries.io, Ashling, IAR Systems, and Segger, the OpenISA VEGAboard is powered by an NXP Semiconductors RV32M1 chip which combines Arm Cortex-M0 and Cortex-M4 ...

Verilator - Verilator 4.008 Released

by Wilson Snyder on Veripool: News
Verilator 4.008 2018-12-01 Support "ref" and "const ref" pins and functions, bug1360. [Jake Longo] In --xml-only show the original unmodified names, and add module_files and cells similar to Verilog-Perl, msg2719. [Kanad Kanhere] Add CONTASSREG error on continuous assignments to regs, bug1369. [Peter Gerst] Add PROCASSWIRE error on behavioral assignments to wires, msg2737. [Neil Turton] Add IMPORTSTAR warning on import::* inside $unit scope. Fix --trace-lxt2 ...

CRU: RISC-V Growth, Transprecision Funding, Reverse-Engineering, and More

by Gareth Halfacree on FOSSi – AB Open
Princeton University’s OpenPiton free and open source silicon (FOSSi) project has announced what is claimed to be the world’s first open-source, general-purpose, heterogeneous-ISA processor: JuxtaPiton. Built by combining the SPARC v9-based OpenPiton with Clifford Wolf’s PicoRV32 RISC-V core, JuxtaPiton is something unique. “JuxtaPiton inherits all of the capabilities of OpenPiton, with the added ability to instantiate chosen tiles with RISC-V cores, rather than the usual OpenSPARC T1 core, ...

RISC-V Foundation, Linux Foundation Join Forces for a “New Era of Open Architecture”

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation and the Linux Foundation have announced a joint initiative which they claim will “enable a new era of open architecture” and “accelerate open source development and adoption of the RISC-V ISA [Instruction Set Architecture].” “With the rapid international adoption of the RISC-V ISA, we need increased scale and resources to support the explosive growth of the RISC-V ecosystem. The Linux Foundation is an ideal partner given the open source nature of both organisations,” ...

Verilator - RISC-V Contest Chooses Verilator

by Wilson Snyder on Veripool: News
The 2018 RISC-V design contest has announced all submissions must be submitted only using Verilator. The contest is to design a RISC-V soft CPU core, run by the RISC-V Foundation, and is sponsored by Google, Antmicro, Lattice Semiconductor and Microsemi. For more details see https://riscv.org/2018contest/

Thales Joins RISC-V Foundation, Praises ISA’s Protection from “Cyber Threats”

by Gareth Halfacree on FOSSi – AB Open
Thales Group, best known for its work in aerospace, defence, transportation, and security, has announced it has joined the RISC-V Foundation, declaring its commitment to “free, open-source hardware architectures based on RISC-V processors.” Founded in 2000 as the next stage from 1968-founded Thomson-CSF, which in turn was an evolution of Compagnie Française Thomson-Houston (CFTH) founded in 1893, Thales’ primary work is in high-security markets. That security focus, the company has ...

The Retro-uC is death - long live the Retro-uC !

by Fatsie on Chips4Makers.io
teaser image Retro-uC's death ? Last month the Retro-uC crowdfunding campaign ended without reaching it's funding goal. I do regret that it did not reach it's goal but I did learn some things: The typical retro-computing guy is not very interested in Arduino type maker stuff. He wants to assemble and program a system with CPU, memory and peripherals. One chip with just GPIO outputs is not really getting him exciting. The prospect of an open silicon movement is not attractive enough for Arduino loving ...

JuxtaPiton Merges OpenSPARC, RISC-V Soft-cores

by Gareth Halfacree on FOSSi – AB Open
Princeton University’s OpenPiton free and open source silicon (FOSSi) project has announced what is claimed to be the world’s first open-source, general-purpose, heterogeneous-ISA processor: JuxtaPiton. Built by combining the SPARC v9-based OpenPiton with Clifford Wolf’s PicoRV32 RISC-V core, JuxtaPiton is something unique. “JuxtaPiton inherits all of the capabilities of OpenPiton, with the added ability to instantiate chosen tiles with RISC-V cores, rather than the usual OpenSPARC T1 core, ...

OTA: LimeNET Micro v2.0, mmWave-to-Optical Breakthrough, Satellite News, and More

by Gareth Halfacree on Myriad
The LimeNET Micro has received a few upgrades since its crowdfunding campaign, now in its last two weeks, launched, including considerably improved RF bandwidth, active Power-over-Ethernet (PoE), and both DSI and HDMI display connectivity. Designed to meld the LimeSDR with the Raspberry Pi Compute Module 3 to create a fully-standalone software defined radio (SDR) and general-purpose processing (GPP) platform, the LimeNET Micro as originally designed saw the LMS7002M field-programmable radio ...

CRU: RISC-V Security, GraphQL Foundation, lowRISC 0.6, and More

by Gareth Halfacree on FOSSi – AB Open
Esperanto Technologies, a company focused on developing energy-efficient many-core accelerators for artificial intelligence and machine learning applications, has announced the closure of a whopping $58 million in Series B funding – more than 10 times its previous investment rounds combined. “Despite still operating largely in stealth mode, we appreciate this strong show of support from strategic and VC investors who had confidential briefings about our plans and believe we have a ...

Getting Started with Zephyr RTOS v1.13.0 On RISC-V

by Nathaniel Graff on SiFive
teaser image Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architectures, and targets including SiFive's E-series CoreIP, and the HiFive 1 development board. I'm particularly excited about this release because it incorporates recent work making the RISC-V port of ...

Sipeed Launches Crowdfunder for RISC-V MAIX AI Dev Boards

by Gareth Halfacree on FOSSi – AB Open
Chinese electronics company Sipeed has launched a crowdfunding campaign for a range of development boards based on a Kendryte K210 dual-core 64-bit RISC-V processor, aiming to bring artificial intelligence (AI) processing to edge devices and with pricing starting at $5 per board. “Sipeed MAIX is the first RV64 AI board for edge computing,” the boards’ creator Sipeed explains. “It makes AI embedded to any IoT [Internet of Things] device possible. MAIX [boards] have tons of exciting features: ...

lowRISC 0.6 Release Brings Performance, Documentation, Ethernet Improvements

by Gareth Halfacree on FOSSi – AB Open
The lowRISC project has announced the release of version 0.6 of its open silicon offering, bringing improvements to performance, debugging, and network connectivity – alongside a pledge to add alternative RISC-V cores to the current Rocket option. Ten months after the release of lowRISC 0.5 brought initial support for Ethernet connectivity, lowRISC’s 0.6 milestone release offers a wealth of improvements. “This release includes an updated version of the Rocket RISC-V core, a higher core ...

El Correo Libre Issue 9

by Gareth Halfacree on LibreCores - Medium
teaser image ORConf 2018 Videos and Slides Now Available As detailed in our last El Correo Leibre newsletter, the recently-held ORConf 2018 event was a great success, with many fantastic talks, hallway discussions, and valuable insights into other projects relating to the free and open source silicon ecosystem. If you were unable to attend, if you need a refresher on how great the talks were, or if you are looking for archival copies for future reference, don’t despair: the videos and slides from the ...

lowRISC 0-6 milestone release

by LowRISC on lowRISC
The lowRISC 0.6 milestone release is now available. This release includes an updated version of the Rocket RISC-V core, a higher core clock frequency, JTAG debugging support, Ethernet improvements, and more. See the release notes, for full details. We’ve also taken the opportunity to re-organise our documentation, adding an easy to follow quick-start guide. Our next development focus is to add support for dropping in the Ariane RISC-V design (from ETH Zurich) as an alternative to ...

OTA: LimeNET Micro Improved, AfriCUBE, Reviving Analogue Cellphones, and More

by Gareth Halfacree on Myriad
The LimeNET Micro crowdfunding campaign continues, and has brought with it a welcome change to the design which will greatly increase the radio’s available bandwidth and sample rate while also adding support for camera and display accessories. Announced via a crowdfunding campaign late last month, the LimeNET Micro is the latest entry in the LimeNET family of open all-in-one software defined radio (SDR) basestation hardware. Based on the same technology as the LimeSDR, the LimeNET Micro ...

Hex Five, Andes, Gowin Collaborate on MultiZone Security Implementation

by Gareth Halfacree on FOSSi – AB Open
Hex Five Security, Andes Technology, and Gowin Semiconductor have jointly announced a collaboration which will see the former’s trusted execution environment added to the middle’s N(X)25 RISC-V cores on the latter’s GW-2A field programmable gate array (FPGA) family. “The cost of a robust security implementation on RISC-V is now negligible – the future of RISC-V is security by default,” claims Don Barnetson, co-founder of Hex Five Security, of the company’s MultiZone Security which it has ...

GCC Upstream for 9.0.0

by OpenRISC Community on OpenRISC
We are proud to announce that the OpenRISC port for gcc has been committed to upstream. Mainline OpenRISC support will be available in the upcoming 9.0.0 release of GCC. Note, this has been a clean room rewrite of the OpenRISC gcc port. The old port can still be found in the OpenRISC github repo. Pre-release toolchain binaries for the new toolchain can be found on Stafford’s github releases page. There are a few things still not supported in this new port which were available the ...

Videos and slides from ORConf 2018 now available!

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image ORConf 2018 was a great success, with many fantastic talks, hallway discussions, and valuable insights into other projects. If you couldn’t attend, or if you need a refresher on how great the talks were, don’t dispair: the videos and slides are now available online! Thanks to the hard work of Simon Cook who did all the video editing, you can watch (almost) all talks on our YouTube channel. The slides are also available online for most talks, find them next to the talk descriptions on the ...

RISC-V AI Accelerator Specialist Esperanto Closes $58m Funding Round

by Gareth Halfacree on FOSSi – AB Open
Esperanto Technologies, a company focused on developing energy-efficient many-core accelerators for artificial intelligence and machine learning applications, has announced the closure of a whopping $58 million in Series B funding – more than 10 times its previous investment rounds combined. “Despite still operating largely in stealth mode, we appreciate this strong show of support from strategic and VC investors who had confidential briefings about our plans and believe we have a ...

GNU Radio Foundation Launches Interest Check for London Symposium

by Gareth Halfacree on Myriad
GNU Radio Foundation president Ben Hilburn has launched a questionnaire to gauge interest in a UK event for GNU Radio users and developers, tentatively titled the GNU Radio Symposium, which would run along with the existing European GNU Radio Days and GNU Radio Conference events. Originally developed by Eric Blossom and first released in 2001, the open-source GNU Radio software development toolkit has become one of the most popular ways to develop for software defined radio (SDR) platforms ...

CRU: RISC-V Grows Apace, RTOS Vulnerabilities Patched, and More

by Gareth Halfacree on FOSSi – AB Open
The IIT Madras SHAKTI Project has celebrated a major milestone this month: the first boot of a RISC-V processor both designed and manufactured within its native India. Launched in 2014 with a focus on IBM’s Power instruction set architecture (ISA) before switching to the open-source RISC-V ISA, the Shakti Project has already celebrated a number of breakthroughs: First-boot on its homebrew silicon occurred back in July this year, having been manufactured by US semiconductor giant Intel on a ...

SiFive Launches New E7, S7, U7 RISC-V Cores

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneer SiFive has announced a new family of processor cores, the Core IP 7 Series, which it claims are “the highest performance commercially available RISC-V cores” and which come in hard-real-time, performance, and Linux-capable variants. “The SiFive Core IP 7 Series represents a major advancement in RISC-V. The 7 Series brings features to market that have been in-demand but unavailable to customers,” claims SiFive’s Jack Kang of his company’s latest launch. “SiFive offers the ...

Getting Started with Zephyr RTOS v1.13.0 On RISC-V

by Nathaniel Graff on SiFive
teaser image Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architectures, and targets including SiFive's E-series CoreIP, and the HiFive 1 development board. I'm particularly excited about this release because it incorporates recent work making the RISC-V port of ...

SHAKTI Project Boots Linux on Home-Grown 180nm RISC-V Silicon

by Gareth Halfacree on FOSSi – AB Open
The IIT Madras SHAKTI Project has celebrated a major milestone this month: the first boot of a RISC-V processor both designed and manufactured within its native India. Launched in 2014 with a focus on IBM’s Power instruction set architecture (ISA) before switching to the open-source RISC-V ISA, the Shakti Project has already celebrated a number of breakthroughs: First-boot on its homebrew silicon occurred back in July this year, having been manufactured by US semiconductor giant Intel on a ...

Verilator - Verilator 4.006 Released

by Wilson Snyder on Veripool: News
Verilator 4.006 2018-10-27 Add --pp-comments, msg2700. [Robert Henry] Add --dump-defines. For --trace-fst, save enum decoding information, bug1358. [Sergi Granell] (To visualize enumeration data you must use GTKwave 3.3.95 or newer.) For --trace-fst, instead of *.fst.hier, put data into *.fst. [Tony Bybell] Fix --trace-lxt2 compile error on MinGW, msg2667. [HyungKi Jeong] Fix Windows .exe not found, bug1361. [Patrick Stewart]

S3 Semi’s Edel Griffith Busts Custom Silicon Myths

by Gareth Halfacree on FOSSi – AB Open
S3 Semiconductors’ Edel Griffith has published a piece on Electronic Design busting 11 myths about custom silicon, from production of application-specific integrated circuits (ASICs) being too expensive for lower-volume projects and fear of a so-called “black-box design” process. Designed to encourage companies to look more closely at custom and semi-custom silicon design, whereby application-specific parts are designed and produced to vastly improve efficiency over general purpose ...

OTA: LimeNET Micro, OpenAirInterface, OsmoCon 2018 Videos, and More

by Gareth Halfacree on Myriad
Lime Microsystems has launched a crowdfunding campaign for the LimeNET Micro, an all-in-one device which combines the LMS7002M field-programmable radio frequency (FPRF) chip with a Raspberry Pi Compute Module 3, bringing the LimeNET family to its lowest price point yet. Designed with narrowband applications in mind, the LimeNET Micro operates from 10 MHz to 3.5 GHz – the same frequency range as the LimeSDR Mini – with a 1 MSPS sample rate at a 12-bit depth. Its transmit and receive channels ...

Last Week in RISC-V: October 12, 2018

by Palmer Dabbelt on SiFive
This week's entry is fairly short, but it does come with one major improvement: we now have a mailing list! I've decided to create a Google Group at SiFive, and while I understand that's not ideal it's the best I can figure out for now. The Google Groups interface is quick clunky, so if you're looking for archives it's probably still best to use GitHub. Hopefully this makes it easier for people to find the mailing list. I've copied this message to various RISC-V mailing lists, but won't ...

Last Week in RISC-V: October 12, 2018

by Palmer Dabbelt on SiFive
This week's entry is fairly short, but it does come with one major improvement: we now have a mailing list! I've decided to create a Google Group at SiFive, and while I understand that's not ideal it's the best I can figure out for now. The Google Groups interface is quick clunky, so if you're looking for archives it's probably still best to use GitHub. Hopefully this makes it easier for people to find the mailing list. I've copied this message to various RISC-V mailing lists, but won't ...

Last Week in RISC-V: October 19, 2018

by Palmer Dabbelt on SiFive
It's been another week, which means it's time to find another host for "Last Week in RISC-V". This week we're going to attempt a blog at riscv.org, which will hopefully be a good long-term home for this series of articles. As usual, you can find this week's entry on GitHub. glibc Floating-Point Test Suite As part of the RV32I glibc submission process, Zong from Andes has submitted a glibc patch set to fix a generic floating-point bug that crosses the boundary between GCC and glibc. ...

Last Week in RISC-V: October 19, 2018

by Palmer Dabbelt on SiFive
It's been another week, which means it's time to find another host for "Last Week in RISC-V". This week we're going to attempt a blog at riscv.org, which will hopefully be a good long-term home for this series of articles. As usual, you can find this week's entry on GitHub. glibc Floating-Point Test Suite As part of the RV32I glibc submission process, Zong from Andes has submitted a glibc patch set to fix a generic floating-point bug that crosses the boundary between GCC and glibc. ...

Last Week in RISC-V: Sept 28, 2018

by Palmer Dabbelt on SiFive
I spent too much time writing my single entry this week so it's all I have. The issue itself is somewhat complex, so I thought it warranted a deep dive. Relaxing R_RISCV_PCREL_* in the Presence of Addends Jim recently found an issue with our ELF relocation scheme. While technically it's a somewhat wide-ranging ABI bug, the actual set of cases in which the issue will manifest is somewhat restricted -- in other words: while I'm sure the proper long-term fix for this will be quite involved, ...

Last Week in RISC-V: Sept 28, 2018

by Palmer Dabbelt on SiFive
I spent too much time writing my single entry this week so it's all I have. The issue itself is somewhat complex, so I thought it warranted a deep dive. Relaxing R_RISCV_PCREL_* in the Presence of Addends Jim recently found an issue with our ELF relocation scheme. While technically it's a somewhat wide-ranging ABI bug, the actual set of cases in which the issue will manifest is somewhat restricted -- in other words: while I'm sure the proper long-term fix for this will be quite involved, ...

Dover Microsystems Brings Real-Time Chip Security to SiFive’s DesignShare

by Shafy Eltoukhy on SiFive
Boy have we been busy. Over the last few months, our DesignShare ecosystem has continued to expand, and, this week, we were excited to welcome Dover Microsystems into the program. Through DesignShare, developers now have access to Dover Microsystems’ CoreGuard Silicon IP, which enables processors to defend themselves in real-time from all network-based attacks. CoreGuard prevents illegal instructions from executing before any damage can be done. Its security rules define the difference ...

Dover Microsystems Brings Real-Time Chip Security to SiFive’s DesignShare

by Shafy Eltoukhy on SiFive
Boy have we been busy. Over the last few months, our DesignShare ecosystem has continued to expand, and, this week, we were excited to welcome Dover Microsystems into the program. Through DesignShare, developers now have access to Dover Microsystems’ CoreGuard Silicon IP, which enables processors to defend themselves in real-time from all network-based attacks. CoreGuard prevents illegal instructions from executing before any damage can be done. Its security rules define the difference ...

Analog Bits Clocks into the DesignShare Ecosystem

by Jack Kang on SiFive
Our DesignShare family is growing, and we’re thrilled to announce that Analog Bits, the industry’s leading provider of low-power mixed-signal IP solutions, is now a part of the ecosystem. System designers will have access to Analog Bits’ precision clocking macros such as PLLs and SERDES IP available for the SiFive Freedom platforms through DesignShare. Analog Bits has become an important supplier of differentiated IP embedded in SoC devices and has been instrumental in spawning the mobile ...

Analog Bits Clocks into the DesignShare Ecosystem

by Jack Kang on SiFive
Our DesignShare family is growing, and we’re thrilled to announce that Analog Bits, the industry’s leading provider of low-power mixed-signal IP solutions, is now a part of the ecosystem. System designers will have access to Analog Bits’ precision clocking macros such as PLLs and SERDES IP available for the SiFive Freedom platforms through DesignShare. Analog Bits has become an important supplier of differentiated IP embedded in SoC devices and has been instrumental in spawning the mobile ...

The DesignShare Ecosystem Expands Its Catalog of IP to include eMemory’s Logic NVM

by Jack Kang on SiFive
It’s been a fantastic few months for us with new initiatives and industry recognitions, and we’re excited to share more great news. Earlier this month, we welcomed eMemory, the IP provider of logic-based, non-volatile memory (Logic NVM), as the latest company to join the DesignShare movement! If you missed our previous blog post, DesignShare is a concept that opens a new range of applications and gives any company, inventor or maker the ability to harness the power of custom silicon. The ...

The DesignShare Ecosystem Expands Its Catalog of IP to include eMemory’s Logic NVM

by Jack Kang on SiFive
It’s been a fantastic few months for us with new initiatives and industry recognitions, and we’re excited to share more great news. Earlier this month, we welcomed eMemory, the IP provider of logic-based, non-volatile memory (Logic NVM), as the latest company to join the DesignShare movement! If you missed our previous blog post, DesignShare is a concept that opens a new range of applications and gives any company, inventor or maker the ability to harness the power of custom silicon. The ...

Last Week in RISC-V: Sept 21, 2018

by Palmer Dabbelt on SiFive
Introduction to Linux Kernel Development For those of you interested in getting involved in the RISC-V Linux kernel porting effort, I wrote a short email that links to the various sources of information that might help people get started. Developer Room at FOSDEM I submitted a proposal for a RISC-V developer room at FOSDEM next February. Last year our talk went great and a room was suggested, so I anticipate this will be accepted. We should officially hear back about the submission by the ...

Last Week in RISC-V: Sept 21, 2018

by Palmer Dabbelt on SiFive
Introduction to Linux Kernel Development For those of you interested in getting involved in the RISC-V Linux kernel porting effort, I wrote a short email that links to the various sources of information that might help people get started. Developer Room at FOSDEM I submitted a proposal for a RISC-V developer room at FOSDEM next February. Last year our talk went great and a room was suggested, so I anticipate this will be accepted. We should officially hear back about the submission by the ...

Last Week in RISC-V: Sept 7, 2018

by Palmer Dabbelt on SiFive
This is the last version of "Last Week in RISC-V" that I plan on sending to the various mailing lists, as we'll be posting the rest of them on SiFive's Blog. I didn't get any contributions, but I also haven't gotten through my email yet -- sorry if I missed anything that's been sent it, but I'm not too far behind so I should have everything read from this week by the end of next week. Linux 4.19-rc3 On Tuesday I tagged my pull request for Linux 4.19-rc3, which contains what I hope to be ...

Last Week in RISC-V: Sept 7, 2018

by Palmer Dabbelt on SiFive
This is the last version of "Last Week in RISC-V" that I plan on sending to the various mailing lists, as we'll be posting the rest of them on SiFive's Blog. I didn't get any contributions, but I also haven't gotten through my email yet -- sorry if I missed anything that's been sent it, but I'm not too far behind so I should have everything read from this week by the end of next week. Linux 4.19-rc3 On Tuesday I tagged my pull request for Linux 4.19-rc3, which contains what I hope to be ...

Last Week in RISC-V: August 31, 2018

by Palmer Dabbelt on SiFive
Welcome to the first issue of "Last Week in RISC-V", a weekly newsletter tracking the RISC-V community. This newsletter was born out of a discussion in SiFive's internal RISC-V software team and I'm compiling it so it'll have a somewhat heavy focus on the open source software community for now as that's where I spend most of my time. The general idea behind "Last Week in RISC-V" is that the RISC-V ecosystem is getting big enough that it's impossible for any single person to ...

Last Week in RISC-V: August 31, 2018

by Palmer Dabbelt on SiFive
Welcome to the first issue of "Last Week in RISC-V", a weekly newsletter tracking the RISC-V community. This newsletter was born out of a discussion in SiFive's internal RISC-V software team and I'm compiling it so it'll have a somewhat heavy focus on the open source software community for now as that's where I spend most of my time. The general idea behind "Last Week in RISC-V" is that the RISC-V ecosystem is getting big enough that it's impossible for any single person to ...

Last Week in RISC-V: Sept 14, 2018

by Palmer Dabbelt on SiFive
GNU Tools Cauldron Trip Report, Part 2 I was at the GNU tools cauldron last week. I summarized the two BoF sessions in last week's entry. While that was the extent of the RISC-V specific events at the cauldron, I attended the remainder of the cauldron where there were some great sessions. Vector ABI I attended the aarch64 BoF session, where one of the major issues at hand is to implement a system ABI that allows argument passing via SVE registers. This brought up a mirror in RISC-V land: ...

Last Week in RISC-V: Sept 14, 2018

by Palmer Dabbelt on SiFive
GNU Tools Cauldron Trip Report, Part 2 I was at the GNU tools cauldron last week. I summarized the two BoF sessions in last week's entry. While that was the extent of the RISC-V specific events at the cauldron, I attended the remainder of the cauldron where there were some great sessions. Vector ABI I attended the aarch64 BoF session, where one of the major issues at hand is to implement a system ABI that allows argument passing via SVE registers. This brought up a mirror in RISC-V land: ...

CRU: RISC-V Design Contest, Radio Spectrum Harmisation, Mbed Linux, and More

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has announced the launch of a design contest, in partnership with Google, Antmicro, and Microchip, which will see entrants competing to build the smallest and fastest RISC-V soft core implementations on field-programmable gate arrays (FPGAs). One of the biggest benefits of free and open source silicon (FOSSi) is that you are able to tweak and tailor its design to suit your own needs. To help demonstrate this, the RISC-V Foundation’s design contest is seeking engineers ...

SiFive Hosts Girl Geek X and Champions Custom Silicon For All

by Ali Sana on SiFive
teaser image On Wednesday, July 25th, SiFive had the pleasure of hosting Girl Geek X at our offices in San Mateo. Girl Geek X is a brilliant organization with the aim of connecting women across companies large and small for the purposes of networking and sharing career advice in the fast-paced tech industry. Over the past 10 years, Girl Geek X has grown from a 400-person dinner hosted by Google to a well-known Bay Area group with a membership base of more than 15,000. As the champions of innovation in ...

SiFive Hosts Girl Geek X and Champions Custom Silicon For All

by Ali Sana on SiFive
teaser image On Wednesday, July 25th, SiFive had the pleasure of hosting Girl Geek X at our offices in San Mateo. Girl Geek X is a brilliant organization with the aim of connecting women across companies large and small for the purposes of networking and sharing career advice in the fast-paced tech industry. Over the past 10 years, Girl Geek X has grown from a 400-person dinner hosted by Google to a well-known Bay Area group with a membership base of more than 15,000. As the champions of innovation in ...

Unleashing More Fun Under the Sun

by David Lee on SiFive
teaser image Good news, HiFive fans! A limited supply of HiFive Unleashed Development Kits are now available on CrowdSupply for purchase. Since the launch of HiFive Unleashed, many new capabilities are being enabled on the Freedom U540 SoC, the industry’s first RISC-V based, 64-bit quad-core application processor running Linux. The updated boards now support Debian and Fedora Linux, both of which enable developers to build a fully functional Linux PC with a modern desktop. Additionally, with the help of ...

Unleashing More Fun Under the Sun

by David Lee on SiFive
teaser image Good news, HiFive fans! A limited supply of HiFive Unleashed Development Kits are now available on CrowdSupply for purchase. Since the launch of HiFive Unleashed, many new capabilities are being enabled on the Freedom U540 SoC, the industry’s first RISC-V based, 64-bit quad-core application processor running Linux. The updated boards now support Debian and Fedora Linux, both of which enable developers to build a fully functional Linux PC with a modern desktop. Additionally, with the help of ...

A Look Back: 7th RISC-V Workshop

by Allen Leibovitch on SiFive
teaser image A new year brings new opportunities. Before we dive into 2018, we wanted to take some time to reflect on some of the excitement we experienced over the last couple of months. At the 7th RISC-V Workshop, we had the honor of partnering with some of the industry’s leading companies and announced the following at the workshop: An extended partnership with Microsemi: Microsemi and SiFive formed a strategic partnership to create and market a development board based on SiFive’s RISC-V based ...

A Look Back: 7th RISC-V Workshop

by Allen Leibovitch on SiFive
teaser image A new year brings new opportunities. Before we dive into 2018, we wanted to take some time to reflect on some of the excitement we experienced over the last couple of months. At the 7th RISC-V Workshop, we had the honor of partnering with some of the industry’s leading companies and announced the following at the workshop: An extended partnership with Microsemi: Microsemi and SiFive formed a strategic partnership to create and market a development board based on SiFive’s RISC-V based ...

The FE310 is in a Museum – Which is Pretty Cool

by Jack Kang on SiFive
teaser image It’s been quite busy the past month and change for SiFive and the RISC-V community. On May 4, we unveiled our RISC-V Core IP, radically redefining the process by which you can license and buy custom IP. The RISC-V Core IP launch was followed by a panel at Maker Faire Bay Area, where we got to chat with American computer engineering pioneer Dave Patterson and other panelists about RISC-V and the future of open-source hardware (pictured below). (From left to right: Dave Patterson, Jack Kang, ...

What's happing in the open silicon ecosystem around you? Planet LibreCores helps you to get the latest news from all corners of the community by aggregating blog posts.

All content here is unfiltered and uncensored, and represents the views of the post authors. Individual posts are owned by their authors; please see the original source for licensing information.

Subscribe to Planet LibreCores

In addition to reading the posts here, you can subscribe to Planet LibreCores in your favorite feed reader.

Planet Librecores Atom feed

Or get the subscription list through FOAF or OPML.

Last updated 10 December 2018 08:00 UTC