Planet LibreCores

Seeed Studio Stocks Sub-$18 RISC-V Sipeed Tang Primer FPGA Board

by Gareth Halfacree on FOSSi – AB Open
Internet of Things (IoT)-focused components provider Seeed Studio has begun stocking the Sipeed Tang Primer FPGA development board, a sub-$18 part which features an Anlogic EG4S20 FPGA running a RISC-V soft core. Designed to offer a full RISC-V implementation in a very small form factor, the Tang is based around the Anlogic EG4S20 field-programmable gate array (FPGA) with 20,000 logic units, around 130KB of SRAM, and 64Mb of SDRAM on a 32-bit bus. The board also includes 8Mb user-accessible ...

OTA: MarconISSta Deinstalled, LimeSDR 35km Barefoot Transmission, RPi CNI, and More

by Gareth Halfacree on MyriadRF
teaser image The MarconISSta mission, which saw a LimeSDR and Raspberry Pi installed on the International Space Station (ISS), has successfully completed its first phase and has been safely deinstalled and stowed. “MarconISSta was deinstalled on Saturday, February 9th 2019, by NASA astronaut Anne McClain,” writes project lead Martin Buscher in what is the last live mission update from phase one. “The system is stowed in a safe location and waits for MarconISSta phase II, which we currently plan for not ...

Hailey Lynne McKeefry on the Procurement Benefits of Open Source Hardware

by Gareth Halfacree on FOSSi – AB Open
EBN editor-in-chief Hailey Lynne McKeefry has penned a piece pointing to the considerable benefits of open hardware, and in particular the RISC-V instruction set architecture (ISA), to the procurement process. “It’s clear that open source hardware will have a ripple effect, not just on design, but also on procurement practices,” Hailey writes, citing industry experts including RISC-V Foundation executive director Rick O’Connor and Wave Computing’s Art Swift. “With so many organisations ...

“Arm’s Days Could Be Numbered,” Claims RISC-V Vendor

by Gareth Halfacree on FOSSi – AB Open
EE Times correspondent Nitin Dahad has pointed to growing troubles for embedded processing giant Arm, and the source should be of no surprise: the growing tide of free and open source silicon (FOSSi) designs, including RISC-V. That the ability to literally clone a GitHub repository and have a fully-working processor design ready to use or modify with no royalties or restrictive licensing is causing something of a revolution in the semiconductor industry is no secret – RISC-V pioneer ...

El Correo Libre Issue 12

by Gareth Halfacree on LibreCores - Medium
teaser image FOSSi Foundation Applies to Join Google Summer of Code 2019 The Free and Open Source Silicon Foundation has announced its application for a mentorship position in the Google Summer of Code (GSoC) programme, as part of its efforts towards expanding and improving the ecosystem. “In the Google Summer of Code, Google grants students a scholarship to contribute to open source projects over the summer,” explains Foundation director Stefan Wallentowitz. “The FOSSi Foundation applies as an umbrella ...

Building a RISC-V PC

by Andrew Back on FOSSi – AB Open
teaser image How we assembled a RISC-V desktop computer. (video at the bottom of this post.) While it’s clear that the most significant opportunities for RISC-V will be in democratising custom silicon for accelerating specific tasks and enabling new applications — and it’s already driving a renaissance in novel computer architectures, for e.g. IoT and edge processing — one question that people cannot help but ask is, so when can I have a RISC-V PC? The answer to which is, right now. The SiFive HiFive ...

CRU: Wuthering Bytes 2019 Planning, SweRV RISC-V Released, and More

by Gareth Halfacree on FOSSi – AB Open
AB Open is pleased to announce a call for participation (CFP) in Wuthering Bytes, the annual community technology festival it produces, seeking those interested in hosting a talk, workshop, roundtable, or other event between Friday the 30th of August and Sunday the 8th of September. Wuthering Bytes — produced by AB Open as part of its contribution to the community — has grown considerably from the first event, held at Hebden Bridge Town Hall, in 2013: Wuthering Bytes 2017 saw attendees ...

RISC-V Growth Showcased by Bumper Embedded World 2019 Showing

by Gareth Halfacree on FOSSi – AB Open
The free and open-source silicon (FOSSi) ecosystem continues to grow, and nowhere will that growth be more obvious than at the Embedded World 2019 conference this year where 17 companies will be exhibiting RISC-V implementations and supporting technologies alone. Due to take place at the NürnbergMesse, Germany, from Tuesday the 26th of February to Thursday the 28th of February, Embedded World 2019 is to play host to a booth from the RISC-V Foundation which will include pods from members ...

OTA: PiTop SDR Upgrade, Osmocom, srsLTE Updates, and More

by Gareth Halfacree on Myriad
A video demonstrating the integration of a LimeSDR Mini with the modular, Raspberry Pi-based PiTop laptop has been released – and all it took was a few laser-cut parts. “The PiTop is a rather cool modular laptop that you build yourself and which is based around the Raspberry Pi platform. Eminently hackable, we thought it would be fun to see if we could integrate a LimeSDR Mini for software-defined radio development on the move,” explains Andrew Back in the latest video update to the LimeSDR ...

RISC-V Foundation Announces OpenSBI 0.1 Release

by Gareth Halfacree on FOSSi – AB Open
An initial implementation of an open supervisor binary interface (SBI) for RISC-V, imaginatively dubbed OpenSBI v0.1, has been released with support for the HiFive Unleashed, Kendryte K210-based development boards, and QEMU virtual machines. “OpenSBI is an open source implementation of the RISC-V Supervisor Binary Interface (SBI). SBI serves a critical purpose, enabling an operating system to interact with the supervisor execution environment (SEE),” explains the RISC-V Foundation of the ...

OTA: PiTop SDR Upgrade, Osmocom, srsLTE Updates, and More

by Gareth Halfacree on MyriadRF
A video demonstrating the integration of a LimeSDR Mini with the modular, Raspberry Pi-based PiTop laptop has been released – and all it took was a few laser-cut parts. “The PiTop is a rather cool modular laptop that you build yourself and which is based around the Raspberry Pi platform. Eminently hackable, we thought it would be fun to see if we could integrate a LimeSDR Mini for software-defined radio development on the move,” explains Andrew Back in the latest video update to the LimeSDR ...

Verilator - Verilator 4.010 Released

by Wilson Snyder on Veripool: News
Verilator 4.010 2019-01-27 Removed --trace-lxt2, use --trace-fst instead. For --xml, add additional information, bug1372. [Jonathan Kimmitt] Add circular typedef error, bug1388. [Al Grant] Add unsupported for loops error, msg2692. [Yu Sheng Lin] Fix FST tracing of wide arrays, bug1376. [Aleksander Osman] Fix error when pattern assignment has too few elements, bug1378. [Viktor Tomov] Fix error when no modules in $unit, bug1381. [Al Grant] Fix missing too ...

Western Digital Releases SweRV RISC-V Core Source Code

by Gareth Halfacree on FOSSi – AB Open
Storage giant Western Digital has officially released the source code for its SweRV RISC-V core, under the permissive Apache 2.0 Licence, allowing anyone to run, experiment with, or modify its implementation. Announced back in December, SweRV is a RISC-V core implementation developed in-house as part of Western Digital’s aim to transition its storage processing products away from proprietary cores and onto the free and open instruction set architecture (ISA). “Our SweRV Core and the new ...

Embedded Intelligence Everywhere

by Jack Kang on SiFive
teaser image In 2018, we saw the rapid proliferation of the RISC-V architecture, with commercial deployments of SiFive Core IP in a broad range of applications ranging from wearables and edge devices to the enterprise core. Modern compute workloads are evolving rapidly and require the ability to scale performance on demand and very often have real-time, deterministic requirements. This diversity of workloads poses computational challenges that can be resolved only by domain-specific architectures. With ...

CRU: RISC-V’s Bumper Year, LoRaWAN Growth, cocotb 1.1, and More

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has released a video highlighting some of the key features of the 2018 RISC-V Summit, held in Santa Clara late last year and attended by over 1,100 community members. To say that the free and open source silicon (FOSSi) movement in general and RISC-V in particular had a banner year is no exaggeration: in 2018 we saw Ethernet support added to lowRISC, Future ship its first RISC-V FPGA dev board, Esperanto announce its 4,112-core RISC-V AI accelerator, SiFive announce ...

Verilog-Perl - Verilog-Perl 3.454 Released

by Wilson Snyder on Veripool: News
Verilog::Language 3.454 2018-08-21 Support parsing around Cadence protected meta-comments. Fix define argument stringification (`"), broke since 3.446. [Joe DErrico] Fix to ignore Unicode UTF-8 BOM sequences, msg2576. [HyungKi Jeong]

Cocotb Testbench Hits 1.1, Promises More Rapid Release Schedule

by Gareth Halfacree on FOSSi – AB Open
Cocotb, the Coroutine-based Cosimulation TestBench for verifying Verilog or VHDL register-transfer level (RTL) designs using Python, has reached its version 1.1 release – and brings with it the promise of a more rapid and streamlined release schedule for the future. “This release is the culmination of work done by 50 contributors over a little less than four years,” explains Philipp Wagner of the release. “During that time we merged 242 pull requests, resulting in 257 files changed, with ...

Chisel/FIRRTL Digest: 2018 Year-in-review

by Schuyler Eldridge on Chisel
Contributors We’re extremely grateful for the growth of the developer community over the past year. We’ve seen 20 new contributors across 9 projects 1 in the Chisel/FIRRTL ecosystem. In addition, 17 previous contributors contributed again in 2018. Chisel, FIRRTL, and the broader ecosystem of projects is impossible without your involvement! Thank you! New ...

Semiconductor Engineering on RISC-V, FOSSi’s Growing Potential

by Gareth Halfacree on FOSSi – AB Open
Semiconductor Engineering’s Brian Bailey has published a piece on the growth of RISC-V, including comment from industry experts including SiFive’s Krste Asanovic and Microsemi’s Ted Speers – and the conclusion that 2019 will be a year of major design wins for the open instruction set architecture. Beginning with a look at the troubles besetting those clinging to Moore’s Law – the observation turned mandated development target by Intel co-founder Gordon Moore that the number of transistors ...

OTA: LimeSCAN Demo, GRCon18 Videos, Google Assistant via Ham, and More

by Gareth Halfacree on Myriad
The LimeNET Micro campaign has posted a demonstration of an alpha-status project dubbed LimeSCAN, taking advantage of the ability to run software defined radio and general purpose processing tasks on a single standalone unit to scan for radio spectrum usage data and share it via a private Ethereum blockchain. “The intention is for LimeSCAN to become a public resource for crowdsourced radio spectrum information, where anyone is free to operate a probe that uploads data, and to make use of ...

OTA: LimeSCAN Demo, GRCon18 Videos, Google Assistant via Ham, and More

by Gareth Halfacree on MyriadRF
The LimeNET Micro campaign has posted a demonstration of an alpha-status project dubbed LimeSCAN, taking advantage of the ability to run software defined radio and general purpose processing tasks on a single standalone unit to scan for radio spectrum usage data and share it via a private Ethereum blockchain. “The intention is for LimeSCAN to become a public resource for crowdsourced radio spectrum information, where anyone is free to operate a probe that uploads data, and to make use of ...

RISC-V Summit 2018 Highlight Video Celebrates a Banner Year

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has released a video highlighting some of the key features of the 2018 RISC-V Summit, held in Santa Clara late last year and attended by over 1,100 community members. To say that the free and open source silicon (FOSSi) movement in general and RISC-V in particular had a banner year is no exaggeration: in 2018 we saw Ethernet support added to lowRISC, Future ship its first RISC-V FPGA dev board, Esperanto announce its 4,112-core RISC-V AI accelerator, SiFive announce ...

CRU: Raspberry Pi Goes RISC-V, New FOSS Business Model, KiCon 2019, and More

by Gareth Halfacree on FOSSi – AB Open
Wave Computing has announced the MIPS Open initiative, under which it plans to make the instruction set architecture (ISA) available free of charge with no licensing or royalty payments required – a clear response to the growing popularity of the open RISC-V ISA. Wave Computing, which acquired MIPS from Imagination Technologies in June last year, has confirmed that MIPS Open will allow both 32-bit and 64-bit variants of the MIPS ISA to be adopted for research and commercial use with no ...

Design News Picks 2019 as “The Year of Open Source”

by Gareth Halfacree on FOSSi – AB Open
Design News’ Chris Wiltz has predicted that 2019 will be “the year of open source,” and while it’s hard to imagine the impact of open source software getting any greater than it already has it’s clear that the impetus behind open hardware is growing at an exponential pace. In the piece, which begins as a retrospective of the big moves in the world of free and open source software (FOSS) and open hardware throughout 2018, Chris points to what appears to have been an inflection point for open ...

El Correo Libre Issue 11

by Gareth Halfacree on LibreCores - Medium
teaser image The Year of Free and Open Source Silicon We wish all our readers a happy new year, and we hope you had some relaxing holidays. Looking back at 2018, it’s clear to see a further rise of Free and Open Source Silicon projects. We have, for example, seen many great things coming from the RISC-V ecosystem, as well as the SymbiFlow project, just to mention some of the most popular. Last year’s ORConf was another great success, and we were thrilled to host so many brilliant speakers and support ...

chisel 3.1.6

by Jim Lawson on Chisel
We’ve recently published Chisel v3.1.6 and FIRRTL v1.1.6 and compatible updates to the rest of the BIG6 Chisel projects – chisel-testers v1.2.8, firrtl-interpreter v1.1.6, treadle v1.0.4, and dsptools v1.1.7. This release of the tool set consists of bug fixes. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is welcome.

Raspberry Pi Foundation Announces RISC-V Foundation Membership

by Gareth Halfacree on FOSSi – AB Open
The Raspberry Pi Foundation has announced its membership of the RISC-V Foundation at the Silver Member tier, offering support for the instruction set architecture on a software – though not yet hardware – level. The original Raspberry Pi launched in February 2012 as a low-cost single-board computer (SBC) primarily targeting the hobbyist and educational market and based around a Broadcom BCM2835 single-core Arm system-on-chip. Originally developed for set-top box use, the Broadcom chip ...

OTA: SatNOGS Dashboard, Tempest Tutorial, Es’Hail 2 Update, and More

by Gareth Halfacree on Myriad
The 35th Chaos Communication Congress (35c3) played host to antenna engineer Friederike Maier, whose talk on software defined radio basics and modulation theory serves as a great introduction to the concepts for beginners. “Encoding or decoding random radio-waveforms doesn’t need incredible expensive hardware any more, which offers new possibilities for building up over-the-air communication systems,” Friederike explains. “There are Software Defined Radios providing affordable cellular ...

OTA: SatNOGS Dashboard, Tempest Tutorial, Es’Hail 2 Update, and More

by Gareth Halfacree on MyriadRF
The 35th Chaos Communication Congress (35c3) played host to antenna engineer Friederike Maier, whose talk on software defined radio basics and modulation theory serves as a great introduction to the concepts for beginners. “Encoding or decoding random radio-waveforms doesn’t need incredible expensive hardware any more, which offers new possibilities for building up over-the-air communication systems,” Friederike explains. “There are Software Defined Radios providing affordable cellular ...

VerilogCreator Tunes QtCreator IDE for FPGA Project Use

by Gareth Halfacree on FOSSi – AB Open
Engineers working on field-programmable gate array (FPGA) projects and looking for a friendly development environment to add to their toolchain now have a new option: the VerilogCreator plugin for QtCreator. Written by Rochus Keller and brought to our attention by Hackaday, VerilogCreator is designed to turn the QtCreator integrated development environment (IDE) into one suitable for working on Verilog 2005 projects, complete with syntax highlighting, code warnings and errors, jump-to ...

You Will Not Get Fired for Choosing RISC-V

by Camille Kokozaki on SiFive
teaser image Published by SemiWiki. These were the closing words Yunsup Lee, CTO, SiFive used at one of the December RISC-V Summit Keynotes entitled ‘Opportunities and Challenges of Building Silicon in the Cloud’. Fired up was more the mood among the 1000+ attendees of the RISC-V Summit held at the Santa Clara Convention Center and SiFive was among the companies showcasing their latest offerings, providing an update among the increasingly active and productive ecosystem blending open-source initiatives ...

Welcome - The SiFive Download, Part III

by Jack Kang on SiFive
Earlier this month, we took a huge step in democratizing access to custom silicon when we unveiled our newest core, the U54-MC Coreplex - the industry’s first RISC-V based, 64-bit, quadcore application processor with support for full featured operating systems including Linux, Unix and FreeBSD. Check out the full newsletter here!

Welcome - The SiFive Download, Part II

by Jack Kang on SiFive
On August 15, we announced that regarded industry veteran Naveed Sherwani has joined SiFive as CEO. We invited him to share his vision for the company and his optimism for fomenting a revolution in the semiconductor industry. Check out the full newsletter here!

The SiFive Download - What's Up Next?

by Jack Kang on SiFive
We recently announced that Intel Capital participated in our Series C funding round! Our CEO, Naveed Sherwani, revealed the investment earlier this month at the Intel Capital Global Summit. Check out the full newsletter here!

The SiFive Download - The Next Revolution is Here!

by Jack Kang on SiFive
First, we are thrilled to have recently announced that we raised $50.6 million in our Series C funding round! We wanted to thank our existing and new investors - including Chengwei Capital, Huami, SK Telecom and Western Digital - for the continued support and new engagement, so we held a party to celebrate! Check out the full newsletter here!

The SiFive Download - Ringing in 2018 with Fresh Faces and Big Resolutions

by Jack Kang on SiFive
Before we dive into our newsletter, we want to take a moment to talk about the vulnerabilities around Meltdown and Spectre. First off -- and most fortunately -- SiFive’s RISC-V Core IP offerings are not affected by Meltdown and Spectre. Secondly, as the RISC-V Foundation’s statement on these vulnerabilities notes, now is the time for open architecture and open hardware designs to shine. Check out the full newsletter here!

The SiFive Download - Are you ready to UNLEASH your genius?

by Jack Kang on SiFive
We’re heading to the Embedded Linux Conference next week, March 12-14, to hold our first hackathon. Developers will be among the first to run code on the HiFive Unleashed board with a chance to take home a board of their own and win a $1,000 cash prize. Check out the full newsletter here!

The SiFive Download: A Year in Review

by Jack Kang on SiFive
Welcome to the first iteration of our bi-monthly newsletter, The SiFive Download! On a regular cadence, we will plan to give you a download on all things SiFive – from the events we will be attending to the articles we’ve been featured in. This newsletter is intended to give you a glimpse under the SiFive hood. Check out the full newsletter here!

RISC-V 101 Webinar

by Jack Kang on SiFive
This one-hour webinar is for Embedded Developers who are interested in learning more about the RISC-V architecture. It covers areas such as the Register File, Instruction Types, Modes, Interrupts, and Control and Status Registers. Prior knowledge of RISC-V is not necessary, but having a basic understanding of Computer Architecture is beneficial. Check out the webinar recording here!

OTA: LimeNET Micro Files, a Serial Adapter SDR Hack, Origami Filters, and More

by Gareth Halfacree on Myriad
The board design files for the LimeNET Micro v2.0, which includes expanded bandwidth for the radio portion as well as making more features of the Raspberry Pi Compute Module 3 available, have now been published to the Myriad-RF GitHub repository. First announced back in October, the LimeNET Micro v2.0 design’s primary change is to switch from the Serial Peripheral Interface (SPI) bus to USB for connectivity between the controlling Raspberry Pi Compute Module 3 and the LMS7002M ...

OTA: LimeNET Micro Files, a Serial Adapter SDR Hack, Origami Filters, and More

by Gareth Halfacree on MyriadRF
The board design files for the LimeNET Micro v2.0, which includes expanded bandwidth for the radio portion as well as making more features of the Raspberry Pi Compute Module 3 available, have now been published to the Myriad-RF GitHub repository. First announced back in October, the LimeNET Micro v2.0 design’s primary change is to switch from the Serial Peripheral Interface (SPI) bus to USB for connectivity between the controlling Raspberry Pi Compute Module 3 and the LMS7002M ...

2018.1 Release: Linux, Debugging, Automation, and Tons of Fixes

by OpTiMSoC on OpTiMSoC
Woohoo! After more than two years of work and 479 git commits later we are very proud to present the all-new 2018.1 release of OpTiMSoC! A look at the statistics gives a first impression of how large this release is: diffstat tells us about 973 files changed, 133,697 lines inserted and 58,806 lines deleted. Or in other words, the code size increased by 74,891 lines! How do those lines of code translate into functionality, you may ask? Let’s have a closer look. Debug Infrastructure The ...

Thales, IIT Madras Partner for Fault-Tolerant SHAKTI RISC-V Processors

by Gareth Halfacree on FOSSi – AB Open
Thales, which recently became a member of the RISC-V Foundation, has announced a joint project with IIT Madras to develop a fault-tolerant version of the SHAKTI Project RISC-V CPU. “After the two successful fabrication and booting of SHAKTI with two technology nodes, 22nm (Intel Fab, Oregon USA) and 180nm (SCL Chandigarh fab, India), this tie-up with Thales is very exciting and certainly is a big step towards taking SHAKTI family to the global technology ecosystem,” claims Professor ...

Linux on OpTiMSoC: How many small steps unlock a whole new world

by OpTiMSoC on OpTiMSoC
teaser image Some projects we take upon ourselves are done quickly: start, do the work, profit. Others take a bit longer. And then there are these projects which seem to linger forever in an “almost done” state. Just one more small thing and we’ll be done. A small fix here. An extension to a module there. A new component elsewhere. And so it goes on, and on, and on. For days, for weeks, for years. Adding Linux support to OpTiMSoC is such a story. But there’s a happy end: Linux support has finally ...

Open Standards Work!

by Naveed Sherwani on SiFive
We are really excited to see Wave Computing announce the open MIPS ISA and R6 processor core. SiFive would like to congratulate and welcome MIPS to the open-source community with its MIPS Open Initiative. The addition of the MIPS 32 and 64-bit open ISA will provide more options freely available to SoC designers. The open-source processor community, based on the RISC-V ISA, is thriving, and the addition of MIPS underscores the fact that the world is indeed becoming more open. Open ISA ...

Wave Computing Announces MIPS Open Initiative

by Gareth Halfacree on FOSSi – AB Open
Wave Computing has announced the MIPS Open initiative, under which it plans to make the instruction set architecture (ISA) available free of charge with no licensing or royalty payments required – a clear response to the growing popularity of the open RISC-V ISA. Wave Computing, which acquired MIPS from Imagination Technologies in June this year, has confirmed that MIPS Open will allow both 32-bit and 64-bit variants of the MIPS ISA to be adopted for research and commercial use with no ...

Code with Confidence: OpTiMSoC Always Works!

by OpTiMSoC on OpTiMSoC
teaser image OpTiMSoC is a highly complex system. If all goes to plan, software, hardware and tooling work together to form a well-integrated SoC (framework). But as so often, the reality is less gloomy: changing a single line of code anywhere could lead to trouble anywhere else. Finding out about breakages only weeks of months after the fact makes debugging a nightmare. [1] Not any more. After multiple years of despair and a lot of work we can finally say with confidence: “OpTiMSoC always works!” In ...

Bluespec Launches Commercially-Supported Flute RISC-V Cores

by Gareth Halfacree on FOSSi – AB Open
RISC-V specialist Bluespec Inc. has announced its second RISC-V processor design, Flute, which it is making available as basic cores ahead of future releases which will include additional instructions for Linux and FreeRTOS compatibility. The follow-up to Bluespec’s existing Piccolo core, Flute is currently available in RV32IMU and RV64IMASU implementations with a floating-point and compressed-instruction variant supporting Linux and FreeRTOS operating systems to follow. The core uses a ...

chisel 3.1.5

by Jim Lawson on Chisel
Well, that was quick. We’ve discovered a regression in FIRRTL 1.1.4 (FIRRTL issue 972) The issue is fixed with FIRRTL v1.1.5 and we’ve published Chisel v3.1.5 and and compatible updates to the rest of the BIG6 Chisel projects – chisel-testers v1.2.7, firrtl-interpreter v1.1.5, treadle v1.0.3, and dsptools v1.1.6.  

chisel 3.1.4

by Jim Lawson on Chisel
We’ve just published Chisel v3.1.4 and FIRRTL v1.1.4 and compatible updates to the rest of the BIG6 Chisel projects – chisel-testers v1.2.6, firrtl-interpreter v1.1.4, treadle v1.0.2, and dsptools v1.1.5. This release of the tool set consists of bug fixes, performance improvements and some new features. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is ...

CRU: Free RISC-V Boards, Security in the FOSSi Era, and More

by Gareth Halfacree on FOSSi – AB Open
OpenISA has officially launched the VEGAboard microcontroller development board, based on the PULP Platform’s RI5CY and Zero-RI5CY RISC-V core, and it’s giving them away to encourage adoption of the free instruction set architecture (ISA). Developed in partnership with the Parallel Ultra Low Power (PULP) Platform, Express Logic, Foundries.io, Ashling, IAR Systems, and Segger, the OpenISA VEGAboard is powered by an NXP Semiconductors RV32M1 chip which combines Arm Cortex-M0 and Cortex-M4 ...

Round-Table Discusses RISC-V, FOSSi Impact on Hardware Security

by Gareth Halfacree on FOSSi – AB Open
Semiconductor Engineering’s Ed Sperling has published extracts of a round-table with Rambus’ Helena Handschuh, Microsemi’s Richard Newell, and Galois’ Joseph Kiniry on the impact the open RISC-V instruction set architecture (ISA) can have on security. “With open source, you have the opportunity to review it and come up with comments, feed it back to the community, and as a group you can advance maybe not faster but better,” explains Handschuh. “You have more hands. Everybody is available to ...

El Correo Libre Issue 10

by Gareth Halfacree on LibreCores - Medium
teaser image RISC-V Foundation Names Summit SoftCPU Contest Winners The RISC-V Foundation has named the four winners of the SoftCPU Contest, held as part of the RISC-V Summit, with the Free and Open Source Silicon Foundation’s Olof Kindgren receiving the Creativity Prize for a RISC-V implementation dubbed SERV. “The RISC-V ISA is ushering in a new era of innovation, empowering companies and designers around the world to develop a wide variety of implementations that solve today’s most complex design ...

Tom Verbeure on the VexRiscV CPU: “A New Way to Design”

by Gareth Halfacree on FOSSi – AB Open
Engineer Tom Verbeure has written up an analysis of the VexRiscV CPU, a RISC-V design implemented using the novel SpinalHDL hardware description language (HDL) – an approach he describes as being “as efficient as the most optimised Verilog, yet at the same time extremely configurable.” First-prize winner in the recent RISC-V Soft-Core CPU Contest, VexRiscV eschews traditional development methodologies in favour of using the novel SpinalHDL language – a Scala library providing hardware ...

OTA: A Mysterious Signal, FPV Antenna Gimbals, Fox-1Cliff, and More

by Gareth Halfacree on Myriad
Popular software package SDR-Console is set to get transmit support on the LimeSDR range, from version 3.0.4 onwards – once beta testing is complete. The new feature of SDR-Console v3.0.4 was teased by Jason Fairfax on Twitter late last month. “Calling CQ SSB on 144.300 MHz from IO81rk,” he wrote. “Hint: SDR-Console v3.0.4 beta now has TX support for the LimeSDR.” During testing, Jason found the LimeSDR’s internal clock suitable for use on FT8/WSJT with no need for an external clock ...

OTA: A Mysterious Signal, FPV Antenna Gimbals, Fox-1Cliff, and More

by Gareth Halfacree on MyriadRF
Popular software package SDR-Console is set to get transmit support on the LimeSDR range, from version 3.0.4 onwards – once beta testing is complete. The new feature of SDR-Console v3.0.4 was teased by Jason Fairfax on Twitter late last month. “Calling CQ SSB on 144.300 MHz from IO81rk,” he wrote. “Hint: SDR-Console v3.0.4 beta now has TX support for the LimeSDR.” During testing, Jason found the LimeSDR’s internal clock suitable for use on FT8/WSJT with no need for an external clock ...

Microsemi, SiFive Launch Linux-Compatible RISC-V PolarFire SoC

by Gareth Halfacree on FOSSi – AB Open
Microsemi has announced a new system-on-chip (SoC) architecture which combines the company’s PolarFire low-power field-programmable gate arrays (FPGAs) with a complete RISC-V processor implementation for use with Linux platforms. Developed in partnership with RISC-V pioneer SiFive, the PolarFire SoC includes an asymmetric coherent CPU cluster with four 64-bit RV64GC RISC-V cores and one RV64IMAC monitor core, connected to a 2MB Layer 2 memory subsystem via a coherent switch, then on to a ...

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Last updated 19 February 2019 06:30 UTC