Planet LibreCores

LowRISC 0.5 Brings First Ethernet Support

by Gareth Halfacree on FOSSi – AB Open
The lowRISC project has officially announced the launch of lowRISC 0.5, a milestone release of the popular RISC-V implementation which brings with it open-source Ethernet support. Built upon a RISC-V implementation from the University of California at Berkeley (UC Berkeley), lowRISC 0.5 marks a major milestone release on the road to a completely open-source RISC-V based system-on-chip (SoC) design. By far the biggest change in this revision is the addition of open-source intellectual ...

FPGA-based disk controller for Apple II

by DP on FPGA – Dangerous Prototypes
teaser image Steve Chamberlin over at Big Mess o’Wires has been working on an FPGA-based disk controller for Apple II, which he call Yellowstone: Apple II disk controller cards are weird, there are a crazy number of different types, and many are rare and expensive. Can an FPGA-based solution save the day for retro collectors? You bet! Nearly all the existing disk controllers connect the same 8-bit bus to the same 19-pin disk interface, so a universal clone is merely a question of replacing the vintage ...

eeNews Europe: Dresden Firm Takes FDSOI Down To 0.4V

by Carmen Soh on RISC-V Foundation
The IP is available through makeChip, Racyics’ hosted design service platform targeted at startups, small companies, research institutes and universities. Racyics has executed power-performance-area (PPA) studies for both Cortex and RISC-V based microcontrollers (MCUs) operating at supply voltages down to 0.4V on 22FDX and in Decmeber 2017 it taped out a Cortex-based test chip for silicon validation of its adaptive body bias (ABB) design approach and to show the potential for MCU ...

lowRISC 0-5 milestone release

by LowRISC on lowRISC
The lowRISC 0.5 milestone release is now available. The various changes are best described in our accompanying documentation, but the main focus is the integration of open-source Ethernet IP. The tutorial demonstrates how to use Ethernet support to boot with an NFS root, as well as with a rootfs on SD card. Our main development focus currently is migrating to a newer version of the upstream Rocket chip design and reintegrating our changes on top of that, but we felt that the integration of ...

CRU: RISC-V, LoRa, Movidius, and More

by Gareth Halfacree on FOSSi – AB Open
The rise of low-power long-range radio technologies like LoRaWAN has been a boon for the Internet of Things (IoT), but working in radio brings unique challenges – as demonstrated by Embedded.com’s new guide to optimising the performance of embedded radios. Written by Chris Lamb and Rod Williams, the guide introduces the core concepts of radio work with a view to addressing the difficulties of balancing the two key aspects involved: the performance of the radio versus the amount of power it ...

AB Open Article: Future Ships Avalanche FPGA Dev Board With RISC-V Core

by Carmen Soh on RISC-V Foundation
“The Avalanche board is the newest addition to our family of development boards. Avalanche is the lowest cost board available in the market for this innovative PolarFire technology,” claims Future Electronics’ Martin Bernier of the release. “We believe industrial, medical, defense and communication customers will be excited about PolarFire FPGA’s ability to deliver up to 50 percent lower power than other mid-range density devices.” Featuring 300,000 logic element (LE) FPGA, Wi-Fi, gigabit ...

Call for Proposals: GSoC 2018

by FOSSi Foundation on FOSSi Foundation - News & Posts
We are applying for Google Summer of Code (GSoC) again this year. In the last two years we had the honor to be part of GSoC as an umbrella organization. You find the projects here: 2016, 2017 As an umbrella organization we provide all projects related to open source silicon design, open source EDA tools and the related ecosystem the opportunity to participate with their project proposals. Google Summer of Code is an excellent opportunity for you to grow your community. You basically ...

New Electronics Article: Avalanche Board Featuring Microsemi’s PolarFire FPGAs

by Carmen Soh on RISC-V Foundation
Microsemi and Future Electronics have announced the Avalanche board, featuring a PolarFire FPGA. The board includes a RISC-V-based soft central processing unit pre-programmed to the kit. The Avalanche development board also features serial flash memory, double data rate type three DRAM and a Microsemi VSC8531 triple speed PHY powered by Microsemi’s LX7167 2.4A hysteretic step-down regulator. To read more, please ...

Future Ships Avalanche FPGA Dev Board with RISC-V Core

by Gareth Halfacree on FOSSi – AB Open
Future Electronics has announced the launch of the Avalanche development board, powered by Microsemi’s PolarFire field programmable gate array (FPGA) and shipping with a pre-loaded RISC-V CPU core. “The Avalanche board is the newest addition to our family of development boards. Avalanche is the lowest cost board available in the market for this innovative PolarFire technology,” claims Future Electronics’ Martin Bernier of the release. “We believe industrial, medical, defense and ...

Sensors Online Article: Dev Board Supports PolarFire FPGAs

by Carmen Soh on RISC-V Foundation
Microsemi and Future Electronics announce availability of the Avalanche board featuring a Microsemi PolarFire non-volatile field programmable gate array (FPGA). As the lowest cost entry development board available today for designing with Microsemi’s lowest power, cost-optimized mid-range PolarFire FPGAs, Future’s Avalanche board lowers the barrier to entry for PolarFire FPGAs and helps expand Microsemi’s market opportunities for the device. The Avalanche development board includes a ...

Reduced Energy Microsystems Joins FDXcelerator Program To Bring RISC-V IP To GLOBALFOUNDRIES’ 22FDX Technology Process

by Carmen Soh on RISC-V Foundation
teaser image Reduced Energy Microsystems (REM) announced today that it has joined GLOBALFOUNDRIES’ FDXcelerator Partner Program, and will be making RISC-V CPU IP available for GF’s 22FDX® process. Based around the open source RISC-V ISA, REM’s IP will offer a low-power core to be integrated into future SoCs to be used across a range of verticals. https://www.design-reuse.com/news/43234/reduced-energy-microsystems-fdxcelerator-risc-v-ip-globalfoundries-22fdx.html The post Reduced Energy Microsystems ...

Forbes Article: Western Digital Gives A Billion Unit Boost To Open Source RISC-V CPU

by Carmen Soh on RISC-V Foundation
Many (likely most) of you have not heard of RISC-V. It’s a new instruction set intellectual property  (IP) that is open sourced and offers an alternative to licensed IP from Arm and MIPS. As instruction sets go, RISC-V is relatively new, having just exited the University of California, Berkeley and entered the market in 2014 and is now managed by the RISC-V Foundation. But in those last 3 years, the instruction set has gained momentum largely due to its simplicity of design and business ...

Tom’s Hardware Article: RISC-V Foundation Trumpets Open-Source ISAs In Wake Of Meltdown, Spectre

by Carmen Soh on RISC-V Foundation
The RISC-V Foundation says that no currently announced RISC-V CPU is vulnerable to Meltdown and Spectre and, in the wake of those bugs, stressed the importance of open-source development and a modern ISA in preventing vulnerabilities. In consumer computing, we usually only hear about two instruction set architectures (ISA): x86 and ARM. Classified as a complex instruction set, x86 dominates the desktop and server space. Since the rise of smartphones, however, reduced-instruction-set (RISC) ...

OTA: LimeSDR Mini on Android, Quantum Radio, 5G and More

by Gareth Halfacree on Myriad
QRadioLink developer Adrian Musceac has shown off how the LimeSDR Mini can be connected to a smartphone for on-the-go software-defined radio reception and transmission, in the latest demonstration update to the Crowd Supply campaign. Using the GNU Radio-based QRadioLink running on an Android smartphone, a USB battery pack, and a USB On-The-Go (OTG) adaptor cable, Adrian shows how the compact LimeSDR Mini can be used portably. During the video demonstration, which is also available on ...

OSDDI: Elkim Roa, OnChip UIS

by Andrew Back on FOSSi – AB Open
A modern microntroller or system-on-chip is much more than simply a processor and some digital peripherals, typically integrating a selection of analogue IP also. In this latest episode of Open Source Digital Design Insights we speak with Professor Elkim Roa, Head of the OnChip Group at UIS Colombia, who are building on the RISC-V architecture and working to address the lack of free and open source silicon (FOSSi) analogue IP, such as LDO, power on reset, ADC and DAC etc. The post OSDDI: ...

Building a More Secure World with the RISC-V ISA

by Rick O'Connor on RISC-V Foundation
teaser image Krste Asanović, Chairman, RISC-V Foundation Rick O’Connor, Executive Director, RISC-V Foundation Recent articles in the media have raised awareness around the processor security vulnerabilities named Meltdown and Spectre. These vulnerabilities are particularly troubling as they are not due to a bug in a particular processor implementation, but are a consequence of the widespread technique of speculative execution. Many generations of processors with different ISAs and from several different ...

SiFive Statement on Meltdown and Spectre

by Andrew Waterman, Co-Founder and Chief Engineer at SiFive on SiFive
The recently disclosed speculation-based timing attacks Meltdown and Spectre have received much attention this week—and rightly so. The vulnerabilities these attacks exploit are not limited to a particular instruction-set architecture, nor are they restricted to a single vendor’s implementations. Many processors that rely upon speculation to improve performance are affected, even some that do not use out-of-order execution. Fortunately, SiFive’s RISC-V Core IP offerings are not affected ...

AB Open Article: Esperanto Announces 4,112-Core RISC-V AI Chip

by Carmen Soh on RISC-V Foundation
Detailed in full on WikiChip Fuse, Esperanto’s aim is to produce three intellectual property (IP) core families based on the open RISC-V architecture: ET-Maxion, a high-performance core designed as an alternative to Arm; ET-Minion, a high-efficiency core; and ET-Graphics, the first RISC-V-based graphics processor. Each will be implemented on Taiwan Semiconductor (TSMC)’s 7nm process node, the company has claimed, and will be available in hardware and licensable IP forms. To read more, ...

Semiconductor Engineering Article: Reflection On 2017: Design And EDA

by Carmen Soh on RISC-V Foundation
People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. We see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but most have this year. (Part one looked at the predictions associated with semiconductor manufacturing and end markets. If there was one key aspect to the predictions for ...

Seeking Alpha Article: Benchmark: WDC, NVDA Adding Fuel To RISC-V Movement

by Carmen Soh on RISC-V Foundation
A new innovation in computer chip architecture is taking hold, Benchmark notes, and it could be “disruptive” for traditional processors (and a possible boon to companies getting on board). RISC-V is the latest version of the “reduced instruction set” architecture, a more modifiable system allowing for more customer tailoring of silicon, and a note from Benchmark’s Gary Mobley highlights what’s going on in the area. To read more, please ...

Barron’s Article: Western Dig, Nvidia On Board with ‘RISC-V,’ So Pay Attention, Says Benchmark

by Carmen Soh on RISC-V Foundation
If you like semiconductors, you should really check out this “RISC-V” thing, according to a missive today from Gary Mobley of The Benchmark Company. RISC-V, in case you don’t know, is the latest incarnation of the “reduced instruction set computing” architecture, devised by Professor David Patterson of U.C. Berkeley about 40 years ago. I interviewed Patterson about RISC-V last summer for Barron’s print magazine. The notion is that by making the “instruction-set architecture,” or ISA, of a ...

Electronic Design Article: These 2017 Embedded Trends Will Thrive in 2018

by Carmen Soh on RISC-V Foundation
Trends rarely follow yearly boundaries, and many significant trends hang around for a long time. What follows are those that emerged last year, and continue to grow in importance in the embedded space. RISC-V is an instruction-set architecture. That’s important because RISC-V requires a hardware implementation to be usable, but it doesn’t define an implementation. The standard actually defines a set of features that can be combined and implemented in hardware, allowing portability of ...

Esperanto Announces 4,112-Core RISC-V AI Chip

by Gareth Halfacree on FOSSi – AB Open
Esperanto, a company run by The Case for RISC co-authors Dave Ditzel and Dave Patterson, has announced its first RISC-V products – including a 4,112-core processor aimed at high-performance artificial intelligence (AI) applications. Detailed in full on WikiChip Fuse, Esperanto’s aim is to produce three intellectual property (IP) core families based on the open RISC-V architecture: ET-Maxion, a high-performance core designed as an alternative to Arm; ET-Minion, a high-efficiency core; and ...

A Look Back: 7th RISC-V Workshop

by Allen Leibovitch, Marketing, SiFive on SiFive
teaser image A new year brings new opportunities. Before we dive into 2018, we wanted to take some time to reflect on some of the excitement we experienced over the last couple of months. At the 7th RISC-V Workshop, we had the honor of partnering with some of the industry’s leading companies and announced the following at the workshop: An extended partnership with Microsemi: Microsemi and SiFive formed a strategic partnership to create and market a development board based on SiFive’s RISC-V ...

Verilator - Verilator 3.918 Released

by Wilson Snyder on Veripool: News
Verilator 3.918 2018-01-02 Workaround GCC/clang bug with huge compile times, bug1248. Support DPI open arrays, bug909, bug1245. [David Pierce, Victor Besyakov] Add INFINITELOOP warning, bug1254. [Alex Solomatnikov] Support > 64 bit decimal $display. Support DPI time and svLogicVal. [Victor Besyakov] Note older version incorrectly assumed svBitVal even for logicals. Support string len() method. [Victor Besyakov] Add error if always_comb has sensitivity ...

Semiconductor Engineering Article: Reflections On 2017: Manufacturing And Markets

by Carmen Soh on RISC-V Foundation
People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. To see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but many have this year. This is the first of two parts that looks at the predictions associated with semiconductor manufacturing and end markets. The second part will cover ...

EETimes Article: 8 Top Innovations Of 2017

by Carmen Soh on RISC-V Foundation
A few crack grad students and professors at Berkeley have done a lot in the past few years to spawn a new microprocessor architecture unencumbered by royalties. Their efforts also sparked new possibilities for open source hardware. Even the veteran co-founders of this movement are amazed this could happen given the consolidation and maturity of today’s semiconductor industry. This is arguably an award that could be held until next year given the first RISC-V SoCs to run Linux — a major ...

Fuse Article: Esperanto Exits Stealth Mode, Aims At AI With A 4,096-core 7nm RISC-V Monster

by Carmen Soh on RISC-V Foundation
You have probably never heard about Esperanto before and there’s a good reason for that. The startup has been cloaked in secrecy, at least until recently that is. At the 7th RISC-V Workshop Esperanto finally gave us some glimpse into what they were up to. Esperanto Technologies was founded in 2014 and have pretty significant backing from companies such as Western Digital. Esperanto president and CEO is none other than Dave Ditzel. And yes, we mean that Ditzel. The the co-author of the “The ...

A Quick Introduction to the ZipCPU Instruction Set

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image Fig 1: The ZipCPU If you aren’t familiar with the ZipCPU, then you should know that it is my attempt at improving the publicly available softcore CPU architectures. It has been designed from the ground up to be a truly Reduced instruction set computer, or RISC machine, to have a simple pipeline implementation, and yet to be able to run a multi-tasking operating system if desired. Unlike many of the other more common soft-core CPUs, such as MicroBlaze or the NiosII, the ZipCPU has been ...

Top 10 ZipCPU blog posts for 2017

by ZipCPU on The ZipCPU by Gisselquist Technology
Happy New Year everyone! It’s now 2018. Shall we take a quick look at the top 10 posts from 2017? In case you missed them, here’s a recap: How to eliminate button bounces with digital logic This page, showing how to handle debouncing buttons, received 1,178 hits in 2017. Building a high speed Finite Impulse Response Digital Filter This page may have been the first real introduction to FIR filtering on ZipCPU.com, offering more details than the initial, ...

The Buzzword Article Part 3: Makers

by Fatsie on Chips4Makers.io
In the third blog post in the discussion on buzzwords related to the Chips4Makers projects I will be talking about one that part of the name of the project. The Hype The two biggest movements that can be seen as the forefront of the maker movement are the Arduino and the Raspberry Pi. These two pieces have sold by the millions and have grown much bigger than expected. With both tools users can do things themselves and not buy an of the shelf part. When looking at the history of both ...

A better filter implementation for slower signals

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image Fig 1. A Generic filter implementation We’ve slowly been working through several DSP filter implementations on this blog. Each of these implementations includes the logic necessary to evaluate a typical convolution, such as the one shown in Fig 1 on the right. We’ve presented both a fairly generic FIR filter implementation for high rate data signals, as well as a simple modification to that implementation that uses fewer resources but has a higher fanout. We’ve also discussed a generic ...

Mystery post: The ugliest bug I've ever encountered

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image I’ve been working with software most of my life–since long before I ever went to college. Now, after several decades of working with software, I’d like to think I may have learned something about fixing bugs in software. I’ve learned to debug bugs by their patterns, and the more often I see the same error lead to the same bug the more these patters are enforced in my mind. Hence, any time the symptoms of a bug match a pattern I’ve seen before, I know exactly where to look for the bug. ...

BML USB 3.0 FPGA interface over PMOD

by DP on FPGA – Dangerous Prototypes
teaser image An open-source-hardware USB 3.0 to FPGA PMOD interface design from Black Mesa Labs: Black Mesa Labs is presenting an open-source-hardware USB 3.0 to FPGA PMOD interface design.  First off, please lower your expectations. USB 3.0 physical layer is capable of 5 Gbps, or 640 MBytes/Sec. This project can’t provide that to your FPGA over 2 PMOD connectors – not even close. It does substantially improve PC to FPGA bandwidth however, 30x for Writes and 100x for Reads compared to a standard FTDI ...

OTA: RAN Competition, ScratchRadio Updates, a Ham Watch, and More

by Gareth Halfacree on Myriad
BT and Lime Microsystems have launched a competition for all LimeSDR, LimeSDR Mini, and LimeNET users: build a radio access project and pick yourselves up a LimeSDR with official aluminium case plus the potential to publish your creation in the LimeNET app store. Designed to encourage the development of software-defined radio access applications – cellular network base stations, Wi-Fi access points, Bluetooth, LoRa, TETRA, or platforms as-yet unexplored – the competition calls for the use ...

chisel 3.0.1

by Jim Lawson on Chisel
We’ve just released the 3.0.1 release of chisel3. Please check out the release notes for the changes incorporated in this release.  

RISC-V QEMU Part 1: Privileged ISA v1.10, HiFive1 and VirtIO

by Michael Clark on SiFive
This post covers recent development in RISC-V QEMU, the open source machine emulator and virtualizer. We’ve been playing a game of catch-up with the hardware folks so that we can match the capabilities of the Freedom U500 SDK. We’re not quite there yet, but we’ve made some important improvements that will allow for a more usable emulator. First, some background on software emulation of Instruction Set Architectures. There are several forms of emulators and they fall broadly into these ...

Arrow's Max-1000: A gem for all the wrong reasons

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image I’ll have to admit, I can be jealous of the CPU world. When I consider the fact that I can purchase a Teensy LC board with an ARM Cortex-M0+ processor running at 48MHz, 62K of flash and 8K of RAM for for only $12 from my local hardware convenience store, it makes me wonder at times why I am working in an FPGA world where the cheapest FPGA designs sell for around $75 or so. Ok, so the Black ICE board is a touch cheaper at $50, but this is still a far cry from the $12 Teensy. Fig 1. The ...

Sensors Online: Extendable Platform Kit Drives FPGA-Based RISC-V Designs

by Carmen Soh on RISC-V Foundation
Microsemi and Imperas Software Ltd. launch the Extendable Platform Kit for Microsemi Mi-V RISC-V soft central processing units (CPUs). The collaboration delivers the first commercially available instruction set simulator (ISS) for Microsemi’s Mi-V ecosystem, a program designed to increase adoption of Microsemi’s RISC-V soft CPU product family utilizing RISC-V open instruction set architectures (ISAs). To read more, please ...

AnandTech Article: Western Digital To Use RISC-V For Controllers, Processors, Purpose-Built Platforms

by Carmen Soh on RISC-V Foundation
Western Digital recently announced plans to use the RISC-V ISA across its existing product stack as well as for future products that will combine processing and storage. The company plans to develop RISC-V cores internally and license them from third parties to use in its own controllers and SoCs, along with using third-party RISC-V based controllers. To develop the RISC-V ecosystem, Western Digital has already engaged in partnerships and investments in various companies working on RISC-V ...

EE Journal Article: Visualizing Real-Time Issues Swedish Company Gives Developers Better Insight

by Carmen Soh on RISC-V Foundation
I had planned this piece some months ago, but suddenly it has become tied into a major breaking news story. In the last ten or so years, the RTOS (Real-Time Operating System) has moved from being a relatively rare beast to becoming almost commonplace, as applications, particularly those built as embedded systems, have demanded communication and, particularly in the Internet of Things (IoT), have added sensing. To manage the complexities of such a system, the developer divides all the ...

eeNews Europe Article: Extendable Platform Kit To Ease Adoption Of FPGA-Based RISC-V Designs

by Carmen Soh on RISC-V Foundation
Microsemi Corporation and Imperas Software partnered on the development of what they believe to be the first commercially available instruction set simulator (ISS) for Microsemi’s Mi-V ecosystem, the Extendable Platform Kit for Microsemi Mi-V RISC-V soft central processing units (CPUs). The program is designed to boost the adoption of Microsemi’s RISC-V soft CPU product family utilizing RISC-V open instruction set architectures (ISAs). Imperas’ Virtual Extendable Platform Kit provides a ...

BML HDMI video for FPGAs over PMOD

by DP on FPGA – Dangerous Prototypes
teaser image Here are two open-source-hardware HDMI  video boards for adding digital video to FPGA platforms with standard PMOD connectors from Black Mesa Labs: The BML 3bit HDMI over single-PMOD uses 7 of 8 available LVCMOS 3.3 pins on a single PMOD to provide 3bit color ( R,G,B 100% On or Off ). Example Verilog design drives 800×600 using a 40 MHz dot clock. The TI TFP410 is very versatile in the resolutions it can generate and is really just limited by the clock that the FPGA can provide and the data ...

Electronics Weekly Article: Microsemi And Imperas Develop RISC-V ISS

by Carmen Soh on RISC-V Foundation
The collaboration delivers the first commercially available instruction set simulator (ISS) for Microsemi’s Mi-V ecosystem, a program designed to increase adoption of Microsemi’s RISC-V soft CPU product family utilizing RISC-V open instruction set architectures (ISAs). “The Imperas EPK allows for rapid software development and debugging of corner cases when using Mi-V soft CPUs on Microsemi field programmable gate array (FPGA) products. We look forward to working with Imperas and other Mi-V ...

CRU: PULP Interview, HiFive Unleashed, 3D Printed Sensors, and More

by Gareth Halfacree on FOSSi – AB Open
The IoT and sensor network focused Parallel Ultra Low Power (PULP) platform is described as a “silicon-proven parallel platform for ultra-low power computing targeting high energy efficiencies,” and project lead Davide Rossi has been kind enough to walk us through it in our latest Open Source Digital Design Insights (OSDDI) interview. As Davide, Assistant Professor at the University of Bologna, explains, Pulp is organised in clusters of RISC-V cores which share tightly coupled data memory. ...

LimeSDR Made Simple Part 9: It’s a VNA Too

by Karl Woodward on Myriad
teaser image Welcome to the ninth episode in the LimeSDR Made Simple series. Since the first we’ve been gradually adding more tools to the SDR toolbox and if you have followed the series along, by now the operation of the LimeSDR should be well and truly demystified. Last time we looked at C code and how to make a simple frequency scanner. This time we will look at pyLMS7002M, a python library for the LimeSDR. Rather than try to make something this time we will look at a poorly understood example, the ...

Building a Simple Logic PLL

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image There’s one signal processing component that has always felt like a black art to me, and that is a Phase Locked Loop or PLL. If you aren’t familiar with PLLs, a PLL is a closed loop control system designed to match an incoming sine wave with a reconstructed sine wave that tracks both the phase and (optionally) the frequency of an incoming sine wave. PLLs are important parts of many Digital Signal Processing (DSP) systems, including (but not limited to): Recovering the implicit (or ...

Embedded Computing Design Podcast: Five Minutes With…Jack Kang, VP Of Product And Business Development, SiFive

by Carmen Soh on RISC-V Foundation
RISC-V has caused a slew of start-ups. One of those, SiFive, is composed of some of the folks behind the original spec, derived at Berkeley. Jack Kang, SiFive’s Vice President of Product and Business Development, had a great perspective on the RISC-V instruction set architecture, and cleared up some of the misconceptions. On this week’s Five Minutes with…interview, Jack went through everything from the latest silicon announcements to the all-important ecosystem. To listen, please ...

Embedded Computing Design Article: Inflection Point For RISC-V: The 7th RISC-V Workshop In Silicon Valley

by Carmen Soh on RISC-V Foundation
The 7th RISC-V Workshop was held in Silicon Valley last week, hosted by RISC-V Foundation founding member Western Digital (WD). Each workshop has a different feel to it, and this one seems to be the inflection point in RISC-V maturity. Whereas past workshops felt a bit like a revival tent meeting, with most everyone caught up in the religion of RISC-V, at this workshop there was also a strong sense of turning this into a business. To read more, please ...

Product Design and Development Article: SiFive, Microsemi Collaborate On RISC-V Development

by Carmen Soh on RISC-V Foundation
SiFive, developer of the RISC-V based Freedom Unleashed (U500) platform, has partnered with Microsemi to build a development board featuring Microsemi’s PolarFire FPGAs. The deal was announced at the RISC-V Workshop hosted by Western Digital, Nov. 28 – 30. “[This collaboration] represents to me a movement of ways of thinking about how we’re going to build design, how we’re going to do hardware in much more collaborative ways and ways that allow hardware to move much faster,” SiFive VP of ...

ElectronicDesign Article: Getting “Creative” With RISC-V

by Carmen Soh on RISC-V Foundation
RISC-V is on the rise, as highlighted by the RISC-V Workshop. Multicore, 64-bit versions of RISC-V are available, and there’s support for FPGA and eFPGA versions. I’ve been following the RISC-V movement almost since its inception, and had a chance to try out SiFive’s Arduino-compatible HiFive1 board earlier. It contains a 32-bit, SiFive E310 RISC-V-compatible processor. I say compatible because RISC-V defines an instruction set architecture (ISA), not a processor architecture like one of ...

All Aboard, Part 9: Paging and the MMU in the RISC-V Linux Kernel

by Palmer Dabbelt on SiFive
This entry will cover the RISC-V port of Linux’s memory management subsystem. Since the vast majority of the memory management code in Linux is architecture-independent, the vast majority of our memory management code handles interfacing with our MMU, defining our page table format, and interfacing with drivers that have memory allocation constraints. I will refrain from discussing the RISC-V memory model in this blog, both because it isn’t yet finished and because it’s complicated ...

7th RISC-V Workshop Recap

by Alicia Daleiden on RISC-V Foundation
teaser image Click HERE to Join the RISC-V Foundation Mail Lists   Workshop Proceedings & Recap Thanks to everyone who attended the 7th RISC-V Workshop! With 515 attendees this was our biggest event yet, showcasing the incredible growth and momentum of the RISC-V ecosystem. To view the Workshop proceedings, including the slides and video from every session, please visit: https://riscv.org/2017/12/7th-risc-v-workshop-proceedings/ We were excited to see the news unveiled by member companies announcing new ...

7th RISC-V Workshop Proceedings

by Rick O'Connor on RISC-V Foundation
teaser image 7th RISC-V Workshop Proceedings November 28-30, 2017 Our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set. Tuesday and Wednesday November 28-29, 2017 – These two days followed our traditional two day format used at previous workshops with presentations covering various RISC-V projects underway within the ...

Building a Numerically Controlled Oscillator

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image Many signal processing applications require a sine wave at some point. If the phase or frequency of this sine wave is controlled within the design, then it is often called a Numerically Controlled Oscillator (NCO). Let’s spend some time today looking into how you might build one of these within an FPGA. We’ll also present a C++ implementation at the end as well, which may be used in embedded embedded applications. Since we’ve already studied how to generate a sine wave on an FPGA, most ...

SEGGER Presents RTOS, Stacks, Middleware For RISC-V

by Alicia Daleiden on RISC-V Foundation
In addition to embOS, SEGGER offers emWin to construct user interfaces, emFile file system, emSSL, emSSH and emSecure to secure internet communications, cryptographic and security libraries for encryption, code signing and authentication (digital signatures), embOS/IP, emModbus, emUSB-Host and emUSB-Device communication stacks for Internet and industrial applications, and emLoad to enable firmware updates from portable storage or delivered over the ...

RISC-V At EmbeddedWorld 2018

by Carmen Soh on RISC-V Foundation
Join us at the EmbeddedWorld 2018 Exhibition & Conference in Nuremberg, Germany on Feb. 27 to March 3, 2018 at the NürnbergMesse to learn more about the RISC-V Foundation and the new products and implementations from its expansive membership. The full-day RISC-V track is scheduled for Tuesday, Feb. 27, made up of 10 30-minute presentations from member companies. During the RISC-V track, speakers will discuss the role of the RISC-V ecosystem in advancing innovation and growth in the ...

OTA: LimeSDR Minis, Active Cooling, Sunny Interference, and More

by Gareth Halfacree on Myriad
teaser image Campaign backers eagerly awaiting their LimeSDR Mini boards have something to whet their appetite in the form of a demonstration using SDRangel, the open-source signal analyser and general-purpose transceiver application. In a video posted to the Crowd Supply campaign page and visible to all, Andrew Back demonstrates how Edouard Griffiths’ popular SDRangel software is capable of interacting with the LimeSDR Mini – on top of the host of other demos previously posted including Osmocom, ...

What's happing in the open silicon ecosystem around you? Planet LibreCores helps you to get the latest news from all corners of the community by aggregating blog posts.

All content here is unfiltered and uncensored, and represents the views of the post authors. Individual posts are owned by their authors; please see the original source for licensing information.

Subscribe to Planet LibreCores

In addition to reading the posts here, you can subscribe to Planet LibreCores in your favorite feed reader.

Planet Librecores Atom feed

Or get the subscription list through FOAF or OPML.

Last updated 16 January 2018 20:30 UTC