Planet LibreCores

Building a prefetch module for the ZipCPU

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image Fig 1: Fundamental CPU loop At its most basic level, any CPU works by fetching instructions from memory, acting upon those instructions, and repeating the process over and over again as shown in Fig 1. The ZipCPU is no different. It also needs to fetch instructions from memory and then act upon them in a tight loop. However, while the ZipCPU accomplishes this same basic loop, the pipelining within the CPU might render these steps a touch more difficult to recognize. Indeed, the ZipCPU ...

CRU: RISC-V, OpenRISC, LoRaWAN, and More

by Gareth Halfacree on FOSSi – AB Open
The Internet Engineering Task Force (IETF) has received a proposal for a cross-vendor standard designed to offer a solid and secure mechanism for updating the firmware of Internet of Things (IoT) devices in the field. Written by Arm engineers Brendan Moran, Milosch Meriac, and Hannes Tschofenig, the draft – titled “A Firmware Update Architecture for Internet of Things Devices – proposes an architecture which allows firmware images to be safely and secure transferred across any available ...

LimeSDR Made Simple Part 8: C Examples and SoapySDR API

by Karl Woodward on Myriad
teaser image Welcome to the eighth instalment of the LimeSDR Made Simple series. Very early on in episode 1, we promised to work from SDR novice to API programming examples in small, bite sized chunks. Having done many of those steps it’s now time to take the final one and start programming. For those who have read the whole series we have touched on programming before with GNU Octave, and in a way Pothos and GNU radio — so moving to direct API access should be a tiny step. Programming in Linux ...

OpenRISC, RISC-V Merges Accepted into the Linux Kernel

by Gareth Halfacree on FOSSi – AB Open
Support for free and open source silicon in the Linux kernel took a jump this week with the merging of contributions for OpenRISC symmetric multiprocessing (SMP) and the first upstream RISC-V port. Support for symmetric multiprocessing on the OpenRISC platform comes courtesy of developer Stafford Horne, based on patches originally written in 2014. Visible in a merge commit message, the pull by Linux creator Linus Torvalds adds support for running multiple OpenRISC cores in a single Linux ...

RISC-V Themed Evening of Talks (London, UK)

by Andrew Back on FOSSi – AB Open
On Thursday 23rd November the Open Source Hardware User Group and BCS Open Source Specialist User Group will host an evening of RISC-V themed talks. Playfully entitled, “RISC-V, RISC-V, RISC-V“, the joint meeting of OSHUG and BCS OSSG will play host to talks on Bringing up cycle-accurate models of RISC-V cores and FreeBSD/RISC-V and Device Drivers, with a third talk to be confirmed. The first will be given by Edward Jones of Embecosm, who will a present a report of their experience bringing ...

Rambus Selects Codasip Studio for SDK Development of RISC-V Processor

by Carmen Soh on RISC-V Foundation
Codasip, Ltd., the leader in RISC-V embedded processor IP cores, today announced that Rambus selected Codasip Studio for developing its next-generation RISC-V security products. Codasip Studio provides fully automated generation of the Software Design Kit (SDK) for RISC-V processors. Codasip Studio utilizes a high-level design flow based on a proprietary modeling language called CodAL that significantly reduces the amount of engineering time and resources required to create, verify, and ...

Inside Secure Unveils Industry’s First Root-of-Trust Solution Based on RISC-V Processor

by Carmen Soh on RISC-V Foundation
Inside Secure (Euronext Paris: INSD), at the heart of security solutions for mobile and connected devices, today announces the launch of its Silicon IP Programmable Root-of-Trust Engine, the industry’s first RISC-V -based platform security solution. https://www.insidesecure.com/Company/Press-releases/Inside-Secure-Unveils-Industry-s-First-Root-of-Trust-Solution-based-on-RISC-V-Processor The post Inside Secure Unveils Industry’s First Root-of-Trust Solution Based on RISC-V Processor ...

Inside Secure Joins RISC-V Foundation

by Carmen Soh on RISC-V Foundation
Inside Secure (Euronext Paris: INSD), at the heart of security solutions for mobile and connected devices, today announced that it has joined the RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the open, free RISC-V instruction set architecture (ISA) forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of ...

Awards Season Brings Big Surprises

by Jack Kang, vice president of product and business development, SiFive on SiFive
It’s that time of year again–awards season, the time when companies submit their best-of-year products and initiatives for consideration by industry watchers and judging panels. It’s a familiar, fairly predictable cycle, but sometimes it can take one by surprise. When UBM announced the finalists for the Annual Creativity in Engineering (ACE) awards earlier this month everyone at SiFive was proud to see that the team behind our HiFive1 development board was shortlisted as a finalist for ...

Analog Bits Joins SiFive’s DesignShare Platform

by Gareth Halfacree on FOSSi – AB Open
Open silicon specialist SiFive has announced another win for its DesignShare platform with Analog Bits, provider of low-power mixed signal intellectual property, adding its precision clocking macros into the mix. Designed to make it simpler for start-ups to build custom silicon by bringing together as much of the IP required to design a system-on-chip (SoC) as possible, DesignShare has enjoyed some high-profile success of late. Earlier this month Flex Logix announced it was adding its ...

UltraSoC Selected by Microsemi for Growing RISC-V Product Range

by Carmen Soh on RISC-V Foundation
UltraSoC today announced that Microsemi, a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, has licensed UltraSoC’s universal analytics and embedded intelligence platform for use in an expanding range of Microsemi products based on the RISC-V open source processor architecture. https://www.ultrasoc.com/ultrasoc-selected-by-microsemi-for-growing-risc-v-product-range/  The post UltraSoC Selected by Microsemi for Growing RISC-V ...

Generating more than one bit at a time with an LFSR

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image This is now our third post on Linear Feedback Shift Registers (LFSRs). Our first post examined how to generate a Linear Feedback Shift Register (LFSR) in Verilog, and our second post walked through an example of a 5-bit LFSR. However, neither of these developments have solved the problem I had initially. Fig 1: System Identification Setup As you may recall, I wanted to use an LFSR to do channel estimation. My intention was to use a setup like Fig 1 to the right. My plan is to transmit ...

The Buzzword Article Part 1: Open Source

by Fatsie on Chips4Makers.io
We live in a world with mass production and consumption of goods. In order to stand out from the pack and to sell a lot of things the marketing of the goods is an important part of doing business in this setting. For this marketing often buzzwords are used to attract people. We all like to think we are special and different than the rest. In reality we are mostly gregarious animals being part of herds in our work environment, sports club, church community, etc. Some of the really special ...

An example LFSR

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image Some time ago, we examined Linear Feedback Shift Registers (LFSR)s and particularly how to create the logic necessary to implement two different forms of an LFSR: a Fibonacci and a Galois form. Today, let’s go back to the Fibonacci form of a shift register and examine one particular set of coefficients, called TAPS in the code, to see what sort of sequence it produces. Fig 1: An example 5-stage LFSR In particular, let’s look at a 5-stage LFSR with the TAPS register given by 00101. You ...

OTA: LimeSDR Mini Success, Biconic Dipoles, RadFxSat, and More

by Gareth Halfacree on Myriad
teaser image The LimeSDR Mini crowdfunding campaign has come to its close with almost three times its target raised, meaning production is now on-track for the first units to ship to backers by the end of the year. A post-campaign update from Andrew and the LimeSDR Mini team provides thanks for all those who have backed the project, and the promise of more to come. “We are by no means finished with LimeSDR Mini and LMS8001 Companion demoes,” explains Andrew, “and you can expect to see more of these over ...

A Configurable Signal Delay Element

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image It’s always fun to design something simple every now and then–something that doesn’t take too much thought, yet still fits a needed place in something you are building. Fig 1: A Signal Delay Element Today, let’s look at a delay element. This is a fundamental signal processing operation that takes a single stream and creates two streams–with the second stream delayed by some programmable amount of samples from the first one. This is actually a very common signal processing need. ...

FactorDaily Article: Meet The Brains Behind India’s Ambitious Processor Project From IIT, Madras

by Alicia Daleiden on RISC-V Foundation
teaser image Shakti is a part of India’s homegrown program to develop its own processors, ranging from IoT to high-end servers, AI and ML processors. Physical manufacturing of chips – slated for first quarter of 2018 – could be the beginning of competition against traditional processor chipmakers. It piggybacks on the open source RISC-V instruction set architecture, an alternative to the existing closed and costly designs. To read the full article, please ...

RISC-V Shakti Project Targets Early 2018 Manufacturing

by Gareth Halfacree on FOSSi – AB Open
The creators of the Shakti Processor Project, which aims to build a RISC-V design capable of scaling from embedded to high-performance compute (HPC) tasks, have announced they are to begin chip manufacture in the first half of 2018. During a detailed interview with Factor Daily held at the Indian Institute of Technology, Madras, Professor V. Kamakoti and project advisor G.S. Madhusudan revealed that the five-year-and-counting project is heading to manufacturing next year in the form of the ...

RISC-V Ecosystem Surpasses 100 Members Globally, Paving the Way for the Next 50 Years of Computing Design and Innovation

by Alicia Daleiden on RISC-V Foundation
teaser image RISC-V Foundation Continues Ecosystem Growth with 120 Percent Increase in Membership Since November 2016 Berkeley, Calif. – Nov. 7, 2017 – The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the open, free RISC-V instruction set architecture (ISA) forward, today announced that the Foundation’s membership has exceeded more than 100 organizations, individuals, academics and universities from 19 countries and six continents ...

Building Formal Assumptions to Describe Wishbone Behaviour

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image No part of any system is as critical as the bus that connects all of the components together. One misbehaving peripheral, or one tyrannical master, and the bus can be locked up until the next power cycle or internal reset. Making matters worse is the fact that it is very difficult to create a test bench for every possible bus interaction. Questions like, what happens if the bus request is abandoned, what happens if there’s a reset in the middle of the request, what happens if … are all ...

The Interface to a Generic Filtering Testbench

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image We’ve now presented several approaches to filtering within an FPGA on this blog. We talked about two of the simplest filters, a generic filter implementation, a cheaper version of the same, and even how to build a moving average filter. What we haven’t discussed is how to test these filters. Just to make matters worse, these filters are only the tip of the iceberg of the filters we’d like to test. Not only do we have the current set of filters to test, but I’d also like to present ...

CRU: RISC-V Growth, FPGAs, Radio, and More

by Gareth Halfacree on FOSSi – AB Open
Microsemi has announced it is to help push RISC-V adoption through Mi-V, a new ecosystem which gives those developing on the open architecture full tier-one vendor support from the top down. “As a leader in RISC-V, we are pleased Microsemi is the first tier one vendor to build out a complete open RISC-V ecosystem which not only supports our needs but contributes to the entire development community,” says Jim Aralis, chief technology officer and vice president of advanced development at ...

SemiAccurate Article: FlexLogix Joins SiFive’s DesignShare Program

by Alicia Daleiden on RISC-V Foundation
SiFive and FlexLogix have teamed up to offer embedded FPGAs in the DesignShare development program. This is the third IP vendor that SemiAccurate knows of to join that program and it is an interesting idea. To read the full article, please visit: https://www.semiaccurate.com/2017/11/02/flexlogix-joins-sifives-designshare-program/   The post SemiAccurate Article: FlexLogix Joins SiFive’s DesignShare Program appeared first on RISC-V Foundation.

WM #2: The LimeSDR and LMS7002

by Andrew Back on Myriad
The second video in the Wireless Masterclass series has been published to YouTube and in this Dr Danny Webster introduces the LimeSDR and takes a look at the LMS7002 FPRF architecture, covering the analogue and digital halves of the chip for both transmit and receive chains. The highly integrated and incredibly flexible LMS7002 is at the heart of the LimeSDR, and understanding its operation and how best to configure it is absolutely key to getting the most out of the platform. Indeed, where ...

SiFive adds Flex Logix eFPGAs to DesignShare

by Gareth Halfacree on FOSSi – AB Open
RISC-V pioneer SiFive has announced that Flex Logix is adding its EFLX embedded field-programmable gate array (FPGA) to the DesignShare platform, adding yet another string to the ecosystem’s system-on-chip (SoC) design bow. “There is a critical need in the chip industry to provide a faster, cheaper way for innovative companies to rapidly prototype new, advanced chip architectures,” says Geoff Tate, chief executive of Flex Logix, of his company’s newest partnership. “Through DesignShare, ...

Flex Logix to Provide Embedded FPGA IP to ‘DesignShare’ for SiFive Freedom Platform

by Alicia Daleiden on RISC-V Foundation
SiFive, the first fabless provider of customized, open-source-enabled semiconductors, and Flex Logix™, a leader in embedded FPGA IP and software, today announced they will partner to make Flex Logix EFLX® embedded FPGA available for the SiFive Freedom Platform as part of the DesignShare program. https://www.sifive.com/posts/2017/10/31/flex-logix-to-provide-embedded-fpga-ip-to-designshare-for-sifive-freedom-platform/ The post Flex Logix to Provide Embedded FPGA IP to ‘DesignShare’ for SiFive ...

chisel 3.0.0-RC1

by Jim Lawson on Chisel
We would like to announce the preliminary 3.0.0-RC1 release of Chisel3.  Chisel3 is the Chisel version used by the RISC-V Rocket Chip Generator and is what we will be supporting and developing moving forward.  As such, we highly encourage you all to move over to it.  In order to do so, please import chisel3._ instead of Chisel._ in your Chisel designs. See migration from Chisel2 to Chisel3 for additional guidance. Chisel3 is a significant upgrade from the 2.x releases of Chisel (Chisel2). ...

Good Software Engineering Principles Apply to Students Too

by ZipCPU on The ZipCPU by Gisselquist Technology
Trust me, I get it. I’ve been there. You’ve got a project due and you are struggling to get it to work. It just needs to work. It doesn’t need to look good. The instructor isn’t going to grade how well (or poorly) you created your assignment. That’s not the requirement. The requirement is only that it works, and the deadline is approaching. So … why do you need to practice good software engineering? Let’s look at a couple examples, shall we? Magic Numbers Principle: Don’t use ...

OSDDI: Clifford Wolf, Yosys

by Andrew Back on FOSSi – AB Open
Over the last couple of years the maker movement has seen a significant growth in interest in FPGA development, with a great deal of activity being focused around the Lattice iCE40 platform, thanks in no small part to the availability of a fully open source FPGA toolchain to use with it. Of course, there are many benefits to open toolchains and opportunities exist all the way from learning environments, right up to use in advanced platforms that can be reconfigured more easily and often. In ...

OTA: LMS8001, LimeSDR Mini Demos, DARPA Hackfest, and More

by Gareth Halfacree on Myriad
The LimeSDR family now has a new accessory in the LMS8001 Companion Board, an add-on designed to extend the frequency coverage up to 10GHz. To launch alongside the LimeSDR Mini later this year, the LMS8001 Companion Board features a four-channel frequency shifter compatible with any version of the LimeSDR family. When connected, the accessory board will allow the frequency range to be extended up to 10GHz – and, depending on task, potentially beyond. Full details on using the LMS8001 ...

FireSim Brings RISC-V to Amazon’s AWS Platform

by Gareth Halfacree on FOSSi – AB Open
Researchers at the University of California at Berkeley RISE Lab have released FireSim, an open-source cloud instance of RocketChip RISC-V processors running on the Amazon Web Services (AWS) platform. “FPGA-accelerated hardware simulation is by no means a new concept. However, previous attempts to use FPGAs for simulation have been fraught with usability, scalability, and cost issues. FireSim takes advantage of EC2 F1 and open-source hardware to address the traditional problems with ...

Generating Pseudo-Random Numbers on an FPGA

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image At some point or other, when working with FPGAs, you will need a pseudorandom number sequence. Trust me, it’s just going to happen. In my case it happened this last week. I needed to do some channel estimation, and I reasoned that a pseudorandom sample stream would make a nice input to the channel. Specifically, my ultimamte plan is to transmit pseudorandom bits out of an FPGA output pin at the fastest speed I can: 950 Mbps on my Artix-7 Arty FPGA board. I can then receive the bits at ...

Microsemi Launches Mi-V Ecosystem

by Gareth Halfacree on FOSSi – AB Open
Microsemi has announced it is to help push RISC-V adoption through Mi-V, a new ecosystem which gives those developing on the open architecture full tier-one vendor support from the top down. “As a leader in RISC-V, we are pleased Microsemi is the first tier one vendor to build out a complete open RISC-V ecosystem which not only supports our needs but contributes to the entire development community,” says Jim Aralis, chief technology officer and vice president of advanced development at ...

SemiWiki.com Article: Open Source RISC-V ISA Brings A New Wrinkle To The Processor Market

by Alicia Daleiden on RISC-V Foundation
By now most people are quite comfortable with the idea of using an open source operating system for many computing tasks. It speaks volumes that Unix, and Linux in particular, is used in the vast majority of engineering, financial, data base, machine learning, data center, telecommunications and many other applications. It was not always so. To read the full article, please visit: https://www.semiwiki.com/forum/content/7089-open-source-risc-v-isa-brings-new-wrinkle-processor-market.html The ...

Andes 32-bit CPU IP Cores Implemented on GLOBALFOUNDRIES 22FDX® Process Technology

by Mariah Hallacy on RISC-V Foundation
Andes Technology Corporation (TWSE: 6533) and GLOBALFOUNDRIES (GF) today jointly announced that Andes’ 32-bit CPU IP cores have been implemented on GF’s 22nm FD-SOI (22FDX®) technology. GF’s 22FDX technology offers the optimum combination of performance, power consumption and cost for IoT, mainstream mobile, RF connectivity and networking applications. http://www.andestech.com/news-d.php?cls=1&id=462 The post Andes 32-bit CPU IP Cores Implemented on GLOBALFOUNDRIES 22FDX® Process ...

Lauterbach and SiFive Bring TRACE32 Support for High-Performance RISC-V Cores

by Mariah Hallacy on RISC-V Foundation
Lauterbach, the leading manufacturer of microprocessor development tools, and SiFive, the first fabless provider of customized, open-source-enabled semiconductors, announced the availability of Lauterbach’s TRACE32 toolset to provide debug capabilities for SiFive’s E31 and E51 RISC-V Core IP, based on the free and open RISC-V ISA. https://www.sifive.com/posts/2017/10/24/lauterbach-and-sifive-bring-trace32-support-for-high-performance-risc-v-cores/   The post Lauterbach and SiFive Bring ...

EE Journal Article: The People’s Processor, Microsemi Rolls Out “Mi-V” RISC-V Ecosystem

by Alicia Daleiden on RISC-V Foundation
The capitalist computing bourgeoisie want to enslave us all with proprietary processing architectures, but the proletariat eventually produces its own processor alternative – an ISA for and by the people, where instruction sets aren’t subject to the whim of the royalty-driven class, and where licensing fees don’t oppress the workers’ BOMs. RISC-V is that ISA – the people’s processor, the unmoving, unwavering instruction set whose implementation carries no fees or encumbrances, whose ...

Electronic Design Article: RISC-V FPGA Design Leaps Forward with Mi-V

by Mariah Hallacy on RISC-V Foundation
A longtime supporter of the RISC-V (pronounced RISC Five) instruction set architecture (ISA), Microsemi provides tools and RISC-V soft cores for its various FPGA lines, including the recently unveiled Mi-V (pronounce My Five) ecosystem. Mi-V further streamlines RISC-V development by giving software developers a starting point that’s able to bypass the FPGA design process, while offering FPGA developers an easier starting point for RISC-V-based designs. To read the full article, please ...

LimeSDR Made Simple Part 7: More Than One Way – Continued

by Karl Woodward on Myriad
teaser image Receiving and transmitting ASK/OOK signals in GNU Radio Welcome to the seventh instalment of LimeSDR Made Simple. In this post we pick up where we left off in the previous, trying to mimic the simplest of radio devices. In the last instalment we got to a point where we could receive the bit stream, but the number of bits per symbol was incorrect. In this post we plan on finishing our ASK receiver and providing a transmitter to replay the data! To facilitate this we need to have both a ...

All Aboard, Part 7: Entering and Exiting the Linux Kernel on RISC-V

by Palmer Dabbelt on SiFive
Continuing our journey into the RISC-V Linux kernel port, this week we’ll discuss context switching. Context switching is one of the more important parts of an architecture port: it is all but impossible to completely abstract away the details of entering and exiting the kernel, Since this is on many critical paths (system calls and scheduling) it must go fast, but since it’s the one line of protection the kernel has from userspace it must also be secure. Traps on RISC-V Systems One of ...

Announcing Architecture Revision 1.2

by OpenRISC Community on OpenRISC
We are pleased to announce that a new OpenRISC architecture specification revision 1.2 has been released. This release formalizes a few items which have already been implemented into our toolchains and Linux as well as describes the multicore OpenRISC architecture. See the full details on the release page. Update on Upstreaming Effort In order for the new features to be useful to most users they must be available in OpenRISC software. Stafford is working on submitting multicore ...

Start of a new blog

by Fatsie on Chips4Makers.io
teaser image Inspired by the LibreCores talk of Philipp Wagner at ORConf 2017 I now decided to start a blog for the Chips4Makers project. Overall the ORConf 2017 conference was inspiring and it was nice to meet real hackers, makers and open source EDA enthousiasts. When I was heading to the conference on a morning I saw this sign in a window: I found it fit for the ORConf conference in general as there a lot of people who are contaminated with the open source virus and wanting to bring what has started ...

RISC-V E-Newsletter October 2017

by Alicia Daleiden on RISC-V Foundation
teaser image Click HERE to Join the RISC-V Foundation Mail Lists As we are gearing up for the 7th RISC-V Workshop, hosted by Western Digital in Milpitas, Calif. from Nov. 28 to Nov. 30, 2017, we have been thrilled to see the influx of submissions for talks and poster presentations. We are excited to unveil the full agenda which you can view here. The first two days of the event are packed with compelling presentations on RISC-V projects underway and keynotes from technology leaders Martin Fink, CTO at ...

CRU: LMS8001 Companion, Security Alerts, 14nm RISC-V, and More

by Gareth Halfacree on FOSSi – AB Open
The LimeSDR open-source software defined radio (SDR) project has received a boost, quite literally, in the form of the frequency-extending LMS8001 Companion Board, announced as part of the LimeSDR Mini crowdfunding campaign. Built around a Lime Microsystems LMS8001 frequency shifter chip, the Companion Board allows any LimeSDR module – from the upcoming low-cost LimeSDR Mini through to the original LimeSDR and LimeSDR PCIe and also QPCIe designs – to boost their upper frequency range from ...

Some Simple Clock-Domain Crossing Solutions

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image In many ways, metastability is the big boogeyman within FPGA design. It is hard to see when desk-checking a design, it doesn’t show up on all simulations (certainly not with Verilator), your synthesis tool can’t solve it, and timing analysis often just gets in the way of dealing with it. Metastability, though, can make your design unreliable. If your design has a problem with metastability, then it might never work. It might work today and not tomorrow. It might work perfectly for ...

Papers from the First Workshop on Computer Architecture Research with RISC-V (CARRV 2017)

by Carmen Soh on RISC-V Foundation
On Oct. 14, 2017, researchers in fields related to computer architecture, compilers, and systems gathered for the First Workshop on Computer Architecture Research with RISC-V (CARRV) for a technical exchange on using RISC-V in computer architecture research. To read the papers from the sessions, please visit: https://carrv.github.io/. The post Papers from the First Workshop on Computer Architecture Research with RISC-V (CARRV 2017) appeared first on RISC-V Foundation.

Microsemi Launches Mi-V Ecosystem to Accelerate Adoption of RISC-V

by Alicia Daleiden on RISC-V Foundation
Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the company’s new Mi-V™ ecosystem with industry leaders, to increase adoption of its RISC-V soft central processing unit (CPU) product family. https://investor.microsemi.com/2017-10-19-Microsemi-Launches-Mi-V-Ecosystem-to-Accelerate-Adoption-of-RISC-V The post Microsemi Launches Mi-V Ecosystem to Accelerate Adoption of RISC-V ...

My first experience with Formal Methods

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image Clifford Wolf has written a nice tool, yosys-smtbmc, based upon his yosys synthesys tool, that allows you to apply formal methods to your Verilog code. The promise of formal methods is that you can then mathematically prove that your code works, or if not then the formal solver should be able to tell you where your code is failing. I’ve only been working with these methods for a week or so, but already there are some things I can share. The first project I tried applying these formal ...

7th RISC-V Workshop Showcases Breadth of the RISC-V Ecosystem with More Than 45 Sessions Featuring Technology Leaders

by Carmen Soh on RISC-V Foundation
Attendees will learn about notable RISC-V updates, projects and implementations across the globe WHAT: 7th RISC-V Workshop WHERE: Western Digital, 951 Sandisk Dr., Milpitas, Calif. 95035, Building 2 WHEN: Tuesday, Nov. 28 to Thursday, Nov. 30, 2017 DETAILS: The RISC-V Foundation is hosting the 7th RISC-V Workshop, bringing its expansive, international ecosystem together to discuss current and prospective RISC-V projects and implementations, as well as collectively drive the future evolution ...

Just some notes to new readers of the ZipCPU blog

by ZipCPU on The ZipCPU by Gisselquist Technology
If you’ve just recently started reading this blog, then welcome! I’ve now been blogging for only five months. I’ve hit quite a few topics, but I’ve still got a lot more to present—many of them fun and fundamental topics that I think everyone will enjoy. While I have your attention, let me point out two things: The ZipCPU blog is funded entirely by donations. I hate pledge drives. I really do. We haven’t had one here, and I’d like to avoid them. If you like the blog, ...

Implementing the Moving Average (Boxcar) filter

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image When we first examined filtering, we looked at the two simplest digital filters I knew of: a filter that averages adjacent values, and a filter that recursively averages multiple numbers together. These two simple filters required only a few FPGA resources, and so they were easy to implement. Sadly, they weren’t very configurable and so their filtering capability was quite limited. We then came back to the topic and discussed how to create a generic Finite Impulse Response (FIR) filter. ...

Verilator - Verilator 3.914 Released

by Wilson Snyder on Veripool: News
Verilator 3.914 2017-10-14 Added new examples/ directory with appropriate examples. This replaces the old test_c and test_sc directories. Add --getenv option for simplifying Makefiles. Add --x-initial option for specifying initial value assignment behavior. Add --no-relative-cfuncs and related default optimization, bug1224. [John Coiner] Add /*verilator tag*/ for XML extraction applications. [Chris Randall] The internal test_verilated test directory is ...

OTA: Masterclass Videos, RFI, C-Band Reuse and More

by Gareth Halfacree on Myriad
If you’re looking for an in-depth deep dive into digital radio and the inner workings of the LMS7002M and LimeSDR you’ll want to look out for Dr. Danny Webster’s Wireless Masterclass series, the first of which has been uploaded to YouTube. Based on presentations from the LimeSDR Workshop held back in March in partnership with the BCS Open Source Specialist Group and the Open Source Hardware User Group, Danny’s videos begin with an introduction to core digital radio concepts and will move on ...

FPGAs vs ASICs

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image I’ve now been developing on Field Programmable Gate Arrays (FPGA)’s for about seven or eight years. I have heard of Application-specific integrated circuit (ASIC) development, but I’ve never done any work with ASIC’s. So I thought I’d ask some folks about them: is ASIC development the same as FPGA development? Is it just a matter of using a different set of tools? Indeed, how hard would it be to present my own designs as ASIC capable designs? As I started to ask around, I got quite the ...

A Core By Any Other Name…

by Jack Kang, vice president of product and business development, SiFive on SiFive
With all apologies to Shakespeare, would a core by any other name still hit the sweet spot in the market for those looking for cost-effective custom silicon? Based on feedback from some friendly chaps in the industry, today we are announcing a new naming scheme for our products. We’ve updated our product names to reflect that we build and provide IP for RISC-V cores–and not any other ISA. To ease the transition, we’ve kept part numbers – like the U54-MC unveiled last week at the Linley ...

Welcome - The SiFive Download, Part III

by Jack Kang, vice president of product and business development, SiFive on SiFive
Earlier this month, we took a huge step in democratizing access to custom silicon when we unveiled our newest core, the U54-MC Coreplex - the industry’s first RISC-V based, 64-bit, quadcore application processor with support for full featured operating systems including Linux, Unix and FreeBSD. Check out the full newsletter here!

Wireless Masterclass Video Series

by Andrew Back on Myriad
Back in March we hosted a 1-day LimeSDR workshop in London, in partnership with the BCS Open Source Specialist Group and Open Source Hardware User Group. For this Principle RF Design Engineer at Lime Micro, Dr Danny Webster, put together a series of presentations that provide an introduction to digital radio concepts, before moving on to LimeSDR and LMS7002M RFIC internals, radio link considerations and then finally, advanced digital radio. The presentations have since been updated and ...

All Aboard, Part 6: Booting a RISC-V Linux Kernel

by Palmer Dabbelt on SiFive
This post begins a short detour into Linux land, during which we’ll be discussing the RISC-V Linux kernel port. SiFive has recently announced the Linux-capable U54-MC RISC-V Core IP, and our Linux port was recently submitted to linux-next, Linux’s staging branch, so assuming that everything goes smoothly we should be merged at the end of the next merge window. Along with Linux we should soon have the full suite of core system components upstream, both for embedded systems (via binutils, ...

7th RISC-V Workshop Preliminary Agenda

by Rick O'Connor on RISC-V Foundation
teaser image 7th RISC-V Workshop Preliminary Agenda November 28-30, 2017 Our preliminary agenda is posted below and registration for the 7th RISC-V Workshop, hosted by Western Digital in Milpitas California on November 28-30, 2017 remains open.  As with past workshops, we expect this workshop will sell out, so please register today. Our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, ...

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Last updated 20 November 2017 13:30 UTC