Planet LibreCores

Six more weeks of Ibex development - what's new?

by LowRISC on lowRISC on lowRISC
teaser image In the past months, we have invested considerable effort in improving our RISC-V core Ibex. This 2-stage, in-order, 32-bit microcontroller-class CPU core was contributed to us by ETH Zürich in December 2018, with activity really ramping up since May. Having been taped out multiple times (as zero-riscy) in a mix of academic and industry projects, it came to us as a relatively mature code base. Despite this, we have continued to invest in improving its design and maintainability. Changes ...

OTA: LimeRFE Schematics, LimeNET Micro Fan Control, Signals and Bits Podcast, and More

by Gareth Halfacree on MyriadRF
Schematics for the LimeRFE software-definable front-end module for LimeSDR and LimeNET devices have been released, as part of Lime Microsystems’ pledge that it will be fully open hardware. “We’ve had a number of requests to share the LimeRFE schematic diagrams, and we’re pleased to report that they are now available on our new LimeRFE hardware design repository,” writes Andrew Back in a Crowd Supply campaign update announcing availability of the preliminary schematics. “As with all MyriadRF ...

OpenPiton’s JuxtaPiton Processor to get Open-Source i486 Core

by Gareth Halfacree on FOSSi – AB Open
Kunal Gulati, working with the OpenPiton Project’s Jonathan Balkind and Katie Lim under the Free and Open Source Silicon Foundation (FOSSi) Google Summer of Code, has announced a project to expand the JuxtaPiton heterogeneous research processor with a third core: ao486. Announced back in November 2018, JuxtaPiton is the merging of the SPARC v9-based OpenPiton with Clifford Wolf’s PicoRV32 RISC-V core in a single open-source research processor design. “When implemented on FPGA, JuxtaPiton ...

The Design Revolution in APAC and Australia

by Aijaz Qaisar on SiFive
teaser image Highlights From the SiFive Tech Symposiums In its endeavor to educate the tech world about the benefits of the RISC-V ISA, SiFive just completed its APAC and Australia series of tech symposiums. Throughout the month of June, symposiums were held in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney. The audience included academia, the business industry, and many RISC-V ecosystem partners. On average, in all seven cities, 60% of the audience came from the tech industry and 40% belonged to ...

RISC-V Foundation Launches Security-Focused Soft-Core CPU Contest

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation, in partnership with Microchip Technology and Thales, has announced its second soft-core CPU competition – time time focusing on security. Following on from its first soft-core CPU contest late last year, the RISC-V Foundation has announced its second. Where the first focused on performance and smart use of available resources, though, the second has a very different focus: security. “With the proliferation of connected devices, security is one of the key challenges in ...

Large-scale RISC-V LLVM testing with Buildroot

by LowRISC on lowRISC on lowRISC
A few years ago lowRISC started developing a new LLVM backend targeting RISC-V. Rather than copying and modifying an existing backend, in an ad hoc fashion, we started from scratch and proceeded systematically. This approach proved successful in producing a high-quality codebase. We recently announced on the llvm-dev mailing list that the backend is now reaching stability and could be promoted from its current status of experimental to an official target. This post explains how our testing ...

The RISC-V LLVM backend in Clang/LLVM 9.0

by LowRISC on lowRISC on lowRISC
On Monday I proposed promoting the upstream RISC-V LLVM backend from “experimental” to “official” for the LLVM 9.0 release. Responses so far are extremely positive, and we’re working to ensure this is a smooth process. This means that from 9.0, the RISC-V backend will be built by default for LLVM, making it usable out of the box for standard LLVM/Clang builds. As well as being more convenient for end users, this also makes it significantly easier for e.g. Rust/Julia/Swift and other ...

El Correo Libre Issue 17

by Gareth Halfacree on LibreCores - Medium
teaser image ORCONF 2019 Three-Month Countdown Begins It’s that time of year again. Following on from the FOSSi Foundation’s Latch-Up and WOSH events, ORConf is now less than three months away and if you haven’t heard, we’re hosting it in beautiful Bordeaux, France over the weekend of September 27th to the 29th. ORConf is now in its eight year of bringing the open source silicon community together for a weekend of presentations, ideas, and discussions. We hope many of our fine past attendees will make ...

Introducing Sam

by LowRISC on lowRISC on lowRISC
teaser image On June 1st, Sam Elliott followed Laura and Pirmin in becoming lowRISC’s newest employee. A few weeks into his new role, he shares why he joined lowRISC and what he’s been doing since he started. “I joined lowRISC CIC as a Compiler Developer, working on the RISC-V LLVM backend, and so far I’m enjoying working on the team! Prior to lowRISC, I worked as a compilers and programming languages researcher at the University of Washington, where I completed my Masters degree. “I worked for ...

OTA: LimeRFE, LimeNET CrowdCell Crowdfunding, Field Reports, and More

by Gareth Halfacree on MyriadRF
The crowdfunding campaign for the LimeRFE, a software-definable front-end module designed for use with LimeSDR hardware, has blown past its funding goal – with over a month left on the clock. Designed to be used with LimeSDR and LimeNET hardware, the LimeRFE is an open-hardware design with open-source software and adds multi-band power amplification (PA) and low-noise amplification (LNA) alongside filtering. Programmable using the Arduino IDE, the LimeRFE is customisable and suitable for ...

Three New Core Series Now Available in SiFive Core Designer

by Amy Lindburg on SiFive
teaser image SiFive Core Designer (SCD) unlocks new possibilities by enabling engineers to explore the architectural design space of a CPU. With our Software-as-a Service (SaaS) application, customers can create and customize RISC-V core IP -- from their laptops. Working within a Core Series (a “class” of Core paired with a specific microarchitecture) customers can rapidly create a range of cores at different design points, run software applications on FPGA bitstreams, simulate with RTL, and ultimately ...

Shakti RISC-V Processor Project Releases Public Software Development Kit

by Gareth Halfacree on FOSSi – AB Open
The Shakti Processor Project, which has produced India’s first natively-manufactured processor, has publicly released the Shakti Software Development Kit (SDK) – meaning application development for the RISC-V based chips can now begin. Featured in one of AB Open’s Open Source Digital Design Insights (OSDDI) interviews, the Shakti Processor Project from IIT Madras has been going from strength to strength: after targeting early 2018 for initial manufacturing of the RISC-V-based parts, the ...

FOSSi Foundation Announces ORConf Three-Month Countdown

by Gareth Halfacree on FOSSi – AB Open
The Free and Open Source Silicon (FOSSi) Foundation has announced the three-month countdown to ORConf, the conference for anyone interested in open-source silicon and the tool chains behind it. “ORConf is in its 8th year of bringing the open source silicon community together for a weekend of presentations, ideas and discussions,” writes FOSSi Foundation director Julius Baxter of the event, which this year is being held in Bordeaux, France on the 27th to 29th of September. “We hope many of ...

OpenROAD Project Accepting Nominations for Open-Source Community Contribution Awards

by Gareth Halfacree on FOSSi – AB Open
The OpenROAD project, the University of California at San Diego’s initiative to reduce the cost, expertise, and risk barriers to hardware design through open-source, has opened nominations for Open-Source Community Contribution Awards. “The OpenROAD project is pleased to announce the establishment of its Open-Source Community Contribution Awards,” the organisation explains of its launch, which brings with it the promise of financial recompense for open-source and open-hardware developers. ...

ORConf 2019 Announcement

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image It’s that time of year again. Following on from the FOSSi Foundation’s Latch-Up and WOSH events, ORConf is now less than 3 months away and if you haven’t heard, we’re hosting it in beautiful Bordeaux, France over the weekend of September 27 to 29. ORConf is in its 8th year of bringing the open source silicon community together for a weekend of presentations, ideas and discussions. We hope many of our fine past attendees will make the trip to France to join us again for what should be ...

CRU: Digital FOSSils, RISC-V Growth, Embench Benchmark, and More

by Gareth Halfacree on FOSSi – AB Open
AB Open’s Open Source Digital Design Insights (OSDDI) series has expanded with the launch of its first long-form article: Digital FOSSils, a look at the storied history of the free and open-source silicon movement. Today, while the term “free and open source silicon” might not be heard around every water cooler, it’s certainly becoming more common. Projects like RISC-V, which aim to create instruction set architectures which can be used in processors from ultra-low-power microcontrollers ...

Semi Engineering Highlights Growing Industry Interest in Open-Source EDA

by Gareth Halfacree on FOSSi – AB Open
Semiconductor Engineering’s Kevin Fogarty has penned a piece on the industry’s increasing interest in open-source electronic design automation (EDA) tools, thanks in no small part to the growth of open hardware projects including RISC-V. “Open-source EDA is back on the semiconductor industry’s agenda, spurred by growing interest in open-source hardware,” Fogarty writes in the article, entitled ‘Will Open-Source EDA Work?’ “But whether the industry embraces the idea with enough enthusiasm to ...

When Hardware Roadmaps Look Like Software Roadmaps

by Drew Barbier on SiFive
The traditional cadence for microarchitecture updates is usually tied to process technology nodes or ground-up redesigns. The SiFive Core IP portfolio offers scalable microarchitectures from efficient application multi-core processors capable of running Linux, to tiny, power-sipping cores suitable for the most area constrained design points. The SiFive quarterly update program delivers key improvements, new features, and more capabilities to SiFive Core IP in a measured, methodical way. ...

Silicon At The Speed of Software

by James Prior on SiFive
The Information age transformed the world, fueled by silicon chips that became more powerful and more cost-effective every 18 months. The thinking of silicon design was led by engineers in the pursuit of faster, smaller transistors. As the Experience Age transcends the Information Age, the law underneath the technology changes from what’s possible, to what’s needed. Now, the ability to create purpose-built processors – secure, fast, efficient, and cost-effective – is the defining ...

Freedom in Software and in the Metal

by Drew Barbier on SiFive
With the move to a quarterly release program (see: Silicon At Speed Of Software), SiFive is innovating in the hardware space at an unprecedented pace. In the SiFive Core Designer update and the Core IP update we learned about new features being added to SiFive Core IP and the ability to quickly access those features via SiFive Core Designer, SiFive's Software-as-a Service (SaaS) application. We have also been hard at work making sure that our software enablement is just as configurable, and ...

Digital FOSSils: A History of Free and Open Source Silicon

by Gareth Halfacree on FOSSi – AB Open
teaser image Today, while the term “free and open source silicon” might not be heard around every water cooler, it’s certainly becoming more common. Projects like RISC-V, which aim to create instruction set architectures which can be used in processors from ultra-low-power microcontrollers all the way up to many-core high-performance computing products, have become big news – and big business – thanks to the fact that anyone is free to use, hack, create, experiment, and release products on them without ...

OTA: QO-100 Field Report, DAB via ODR-mmBTools, the RadioInstigator, and More

by Gareth Halfacree on MyriadRF
The first of the LimeSDR Field Reports has been published, courtesy of community member Daniel Estévez: a look at his LimeSDR Mini-powered satellite ground station project. “My project uses a LimeSDR Mini as the basis for a ground-station for the amateur radio transponders on the geostationary satellite ‘Es’hail 2’ (known as ‘QO-100’ by the amateur radio community),” Daniel writes. “The uplink to the satellite is on the 2.4 GHz band. Many people are using an upconverter to translate a ...

Western Digital Partners with SiFive, PlatformIO for Extended Open-Source Dev Toolset

by Gareth Halfacree on FOSSi – AB Open
Western Digital has announced a partnership with SiFive and PlatformIO Labs which will see the latter’s embedded development platform extended in order to provide a vendor-agnostic, end-to-end open environment with full RISC-V support. Western Digital’s interest in embedded development in general and the open RISC-V instruction set architecture (ISA) specifically isn’t new: the company has long offered data processing products, and in December 2018 unveiled its in-house SweRV Core RISC-V ...

Work Continues on Debian Linux RISC-V Port, Documentation Efforts

by Gareth Halfacree on FOSSi – AB Open
The Debian Linux distribution’s Manuel Montezelo has written of the progress in porting the distribution to the 64-bit RISC-V architecture, boasting of around a 90 percent package compatibility milestone. Announced back in April 2018, the Debian Linux RISC-V port had a long road ahead of it. At launch, around 70 percent of the packages available in the Debian software repositories – which includes everything from core operating system software to third-party applications and even games – ...

X-FAB, Efabless Announces RISC-V-Based Raven Mixed-Signal SoC

by Gareth Halfacree on FOSSi – AB Open
X-FAB Silicon Foundries and Efabless Corporation have announced the creation of a new mixed-signal system-on-chip (SoC) reference design boasting a RISC-V core: Raven. Designed, its creators claim, in just three months, the open-source mixed-signal Raven SoC was built using an open-source tool set put together by Efabless. Its PicoRV32 32-bit RISC-V processing core runs at 100MHz in bench testing, with simulations suggesting its clock rate could be boosted to 150MHz. Wedded to Efabless’ ...

Verilator - Verilator 4.016 Released

by Wilson Snyder on Veripool: News
Verilator 4.016 2016-06-16 Add --quiet-exit, bug1436. [Todd Strader] Error continuation lines no longer have %Error prefix. Support logical equivalence operator <->. Support VerilatedFstC set_time_unit, bug1433. [Pieter Kapsenberg] Support deferred assertions, bug1449. [Charles Eddleston] Mark infrequently called functions with GCC cold attribute. Fix sign-compare warning in verilated.cpp, bug1437. [Sergey Kvachonok] Fix fault on $realtime with %t, bug1443. ...

OpTiMSoC wins the Eurolab4HPC Open Source Project Award!

by OpTiMSoC on OpTiMSoC
teaser image How exciting! At the Week of Open Source Hardware (WOSH) in Zürich, OpTiMSoC co-won the Eurolab4HPC Open Source Project Award! We’re very excited and honored to see the efforts we put into OpTiMSoC being more widely recognized. Thanks a lot to the sponsors of this award! The other prices went to Nyuzi, a processor for highly parallel and GPGPU applications, and FuseSoC, a hardware package manager and build tool which we use in OpTiMSoC! You can find OpTiMSoC, Nyuzi, FuseSoC, and many ...

Embench Embedded Benchmark Project Calls for Aid

by Gareth Halfacree on FOSSi – AB Open
A call-to-arms has been raised by the Embench team for assistance in developing a new, fully-open benchmark suite designed to offer embedded developers an alternative to the products of the Embedded Microprocessor Benchmark Consortium (EMBC). As detailed in an article on EE Times, the Embench team is working to produce an open-source benchmark for embedded developers which distils performance metrics from around 20 real-world applications into a single score. This score will be relative to ...

lowRISC at Week of Open Source Hardware

by LowRISC on lowRISC on lowRISC
teaser image Pretty much the whole team is in Zurich this week for the RISC-V Workshop and inaugural Week of Open Source Hardware, with a packed programme that got off to a start today and which runs all the way through to Friday afternoon. This morning lowRISC board member, Professor Luca Benini, gave a RISC-V Workshop keynote entitled, Energy efficient computing from Exascale to MicroWatts: The RISC-V playground. Our friends and close collaborators at PULP Platform are giving a number of talks this ...

El Correo Libre Issue 16

by Gareth Halfacree on LibreCores - Medium
teaser image WOSH and the Google Summer of Code Kick Off It’s finally here: the Week of Open Source Hardware starts today with two days of RISC-V workshops followed by two days of presentations and tutorials all around free and open source silicon topics. For those not attending, you’ll be able to read more about the event in next month’s El Correo Libre! In other great news, the FOSSi Foundation has been accepted into the Google Summer of Code (GSOC) programme. In GSOC Google pays selected students a ...

European Processor Initiative Delivers First Architectural Designs

by Gareth Halfacree on FOSSi – AB Open
The European Processor Initiative (EPI) has announced the delivery of its first architectural designs to the European Commission, marking the first steps in its efforts to create a made-in-Europe processor family for high-performance and automotive computing. Launched in December 2018, the European Processor Initiative boasts 26 industry partners – up from 23 at foundation – and has three primary goals on its roadmap: the creation of a general-purpose processor (GPP) with a focus on high ...

The RISC-V Revolution is Sweeping Across the APAC Region and Australia

by Swamy Irrinki on SiFive
Join SiFive Tech Symposiums in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney As we make our way around the world meeting and engaging with others in the semiconductor and hardware design community, we are seeing an increased interest in RISC-V based hardware innovation. This is due in large part to the emergence of market-ready RISC-V core IP, development tools and silicon solutions based on cloud-based design platforms that facilitate the creation of custom SoC solutions for edge ...

El Correo Libre - Issue 16

by FOSSi Foundation on FOSSi Foundation - News & Posts
The FOSSi Foundation’s monthly roundup of all things Open Source semiconductor design, including an overview about our Google Summer of Code, can be found here: El Correo Libre Issue 16 - LibreCores - Medium

An update on Ibex, our microcontroller-class CPU core

by LowRISC on lowRISC on lowRISC
teaser image At the beginning of many chips projects, there’s a dream. Could we create a more future-proof chip by embedding an FPGA fabric into it? Could we measure glucose levels more accurately by integrating a small bio lab onto a chip? Could we more reliably recognize kittens in a set of pictures by implementing neural network inference in hardware? In implementation, this dream becomes a piece of hardware, with digital or analog logic, sensors, actuators, and much more. Let’s get it produced and ...

OpenPiton Release 12

by Jonathan Balkind on OpenPiton Blog
teaser image OpenPiton release 12 (19-06-06-r12) is now available. This release brings several improvements to bring feature parity to Ariane alongside a number of smaller bug fixes and improvements that you can see on our GitHub repository. Addition of Ariane FPU on FPGA: With the addition of the Ariane FPU by default, OpenPiton+Ariane is now Linux distribution capable First-class simulation simulation support for Verilator: This enables fast, fully open-source simulation of all of our supported ...

OpenHW Group Announced

by FOSSi Foundation on FOSSi Foundation - News & Posts
Today the OpenHW Group was announced. This is yet another great step for Free and Open Source Silicon. With the rise of RISC-V we have seen some great momentum beyond the processor cores itself. We now see groups growing from and around the RISC-V ecosystem with big players involved. This strongly confirms our story and we look forward to the next months of continuous growth of the FOSSi community. The OpenHW Group is backed for example by Alibaba, NXP, Thales and Silicon Labs, with a ...

Announcing Architecture Version 1.3

by OpenRISC Community on OpenRISC
It has been been a few years since the release of OpenRISC version 1.2. But, it’s been a busy few years of getting GDB and GCC ports upstream. Now with the GCC port upstream we are able to make progress and this new architecture revision does just that bringing in a handful of new instructions: New instruction lf.stod.d for converting floats from single precision to double prevision New instruction lf.dtos.d for converting floats from double precision to single precision New ...

Introducing Pirmin & Laura

by LowRISC on lowRISC on lowRISC
teaser image Pirmin Vogel and Laura James both joined lowRISC on May 1st this year. A few weeks in to their new roles, they each share thoughts on what attracted them to work at lowRISC. Pirmin: “After having traveled around the world for 6 months, I finally started my new position as hardware/software engineer at lowRISC C.I.C. in Cambridge at the beginning of May. At lowRISC, we are working on open-source hardware/software ecosystems with a fully open-sourced, Linux-capable, RISC-V-based SoC being ...

Google Summer of Code 2019 - Kickoff

by FOSSi Foundation on FOSSi Foundation - News & Posts
The Google Summer of Code (GSoC) has started and we are happy to announce that we have seven students working for projects related to FOSSi Foundation: Analysis of WARP-V on FireSim with RocketChip, Alaa Salman The WARP-V RISC-V core generator was developed in 2018 as a configurable, adaptable open-source RISC-V CPU core generator, taking advantage of advanced digital design features of TL-Verilog. It can be configured as a low-power, slow-clock, single stage pipeline, a high-frequency ...

The Design Revolution in Europe: Highlights From the SiFive Tech Symposiums

by Purvi Shenoy on SiFive
teaser image We just wrapped up our six-city tour in Europe, which included Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam. Together with our co-hosts, Qamcom, Syntacore, Imagination Technologies and Mentor; and ecosystem partners, Rambus, IAR Systems, UltraSoC, Antmicro, SecureRF, Credo and lowRISC, we engaged with over 500 responses/registrations throughout the tour. One of the highlights was having people from the audience come onto the stage and use SiFive's Core Designer to build ...

Google Summer of Code 2019

by OpenRISC Community on OpenRISC
The Google Summer of Code is a yearly event which teams open source projects with college students. Students learn about technology and the open source community and projects benefit from new contributions. As in previous years this year OpenRISC is participating as part of the FOSSi foundation project. We have teamed up with librecores-ci, also of FOSSi, to work with Nancy Chauhan on improving the mor1kx’s continuous integration pipeline. You can read the details of the project on ...

OTA: LimeSDR WSPR, Angle of Arrival Experiments, DSPs without Maths, and More

by Gareth Halfacree on MyriadRF
Community member Kiril Miloshev has been interviewed for the Lime Micro Community Hub, on his experiments with Weak Signal Propagation Reporting (WSPR) using the LimeSDR Mini. “Software defined radios got my attention as they are very universal, and you can do whatever you can imagine with them. Especially ones like the LimeSDR Mini, which are inexpensive yet powerful at the same time,” Kiril explains. “I love the huge frequency range. The full duplex makes it possible to use the device as ...

Antmicro Launches Renode 1.7 with TSN, PTP Support, PicoRV32, Murax SoC

by Gareth Halfacree on FOSSi – AB Open
Antmicro has announced the release of Renode 1.7 – quickly followed by version 1.7.1 – with the framework’s first support for time-sensitive networking (TSN) and precision time protocol (PTP) on RISC-V platforms. An open-source simulation framework popular among those working within the proprietary Arm and open RISC-V ecosystems, and recently praised by Dover Microsystems for helping to significantly shorten the company’s design cycle, the latest release of Antmicro’s Renode brings with it ...

BML S7-Mini FPGA Module

by kevinhub88 on Black Mesa Labs
teaser image 2019.05.19 : This blog posting is about the open source S7 Mini FPGA module designed by Black Mesa Labs and professionally manufactured and distributed by Trenz Electronics.  In short, it is a Xilinx Spartan7 7S25 on a 1″x2″ module with 64 Mbits of DRAM, Config PROM, 5V single supply solution and provides either 32 user I/Os on a 0.100″ (2.54mm) DIP grid or 64 user I/Os on a 0.050″ (1.27mm) grid at LVCMOS33 levels. This posting isn’t complete, but a work in progress and central point for ...

CRU: ‘Unhackable’ Chips, Grove AI HAT, RISC-V Drones, and More

by Gareth Halfacree on FOSSi – AB Open
Researchers from the University of Michigan have announced a new RISC-V processor design with a strong focus on security, using ‘churn’ to keep attackers from exploiting vulnerabilities. “Today’s approach of eliminating security bugs one by one is a losing game,” claims Todd Austin, professor of computer science and engineering at the University of Michigan and one of the developers behind the design, dubbed Morpheus. “People are constantly writing code, and as long as there is new code, ...

Western Digital’s Zvonimir Bandić Offers an Intro to SweRV Core

by Gareth Halfacree on FOSSi – AB Open
Western Digital’s Zvonimir Bandić has published an introduction to the company’s open SweRV Core, which it has released to the public following its efforts to move to the RISC-V instruction set architecture (ISA) for its future storage processing products. Western Digital unveiled the SweRV Core late last year, making the source code available in late January under a permissive licence. Based on the RISC-V ISA, the SweRV Core has seen what Western Digital chief technical officer Martin Fink ...

Onwards and upwards at lowRISC

by LowRISC on lowRISC on lowRISC
If you haven’t checked it out yet, be sure to take a look at our press release and the corresponding Google blog post. This industry support and growth of our board is a huge step forwards for lowRISC. As Royal Hansen, vice president of Security, Google, said: "Google believes that open source is good for everyone. To further our commitment, we are investing both capital and engineering resources to create a sustainable open source hardware ecosystem. In addition to engineering resources, ...

lowRISC Expands and Appoints New Members to the Board of Directors from Google and ETH Zurich

by LowRISC on lowRISC on lowRISC
teaser image London, England - lowRISC C.I.C., the open source system on a chip (SoC) organisation, today announced that Prof. Luca Benini (ETH Zurich), Dominic Rizzo (Google) and Ron Minnich (Google) have joined its board of directors. The announcement coincides with a new phase of hiring by lowRISC with the goal of significantly increasing the size of its Cambridge-based engineering team during 2019. lowRISC is a not-for-profit, community-driven organisation working to provide a high quality, ...

PULP Platform Partners with GreenWaves, Bitcraze for RISC-V AI Drone Controller

by Gareth Halfacree on FOSSi – AB Open
The Parallel Ultra-Low Power (PULP) Platform has announced a partnership between ETH Zurich, Greenwaves Technology, and Bitcraze to develop a PULP-powered and wireless artificial intelligence module for drone use: the AI Deck. Based on the earlier PULP-Shield, built as part of the PULP-DroNet project, the AI Shield is designed to control a Crazyflie 2.0 micro-drone. The original design partnered GreenWaves’ GAP8 RISC-V system-on-chip with two off-chip memories, a QVGA ultra-low-power ...

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part I

by Camille Kokozaki on SiFive
teaser image SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing, Calista Redmond was just appointed the new CEO of the RISC-V Foundation). He shared a slide showing the growing RISC-V ecosystem from tools vendors, to IP/semi chip ...

El Correo Libre Issue 15

by Gareth Halfacree on LibreCores - Medium
teaser image Catch-Up and Latch-Up: FOSSi Foundation’s First US Multi-Day Event Latch-Up in Portland, Oregon last weekend marked the first multi-day FOSSi Foundation event we’ve held outside Europe. What transpired surpassed even our best expectations. We cannot thank everyone involved enough, and it’ll be difficult for this write-up to do justice to the quality of the presenters and the enthusiasm for open source hardware in the room and, later, in the bars of Portland. A soft opening to the weekend ...

OpenPiton+Ariane Workshops Scheduled for WOSH, ISCA in June

by Gareth Halfacree on FOSSi – AB Open
The OpenPiton project has announced a pair of workshops centred around its OpenPiton+Ariane platform, taking place in Zurich during the Week of Open Source Hardware (WOSH) and Arizona as part of International Symposium on Computer Architecture (ISCA). Created in partnership with the Parallel Ultra-Low Power (PULP) Platform, OpenPiton+Ariane combines the former’s 64-bit application-class RISC-V processor design with the OpenSPARC-based OpenPiton research processor – designed, its creators ...

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part II

by Camille Kokozaki on SiFive
teaser image During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded Processors, and E Cores 32-bit Embedded Processors. Embedded intelligence allows mixing of application cores with embedded cores, extensible custom instructions, ...

The SiFive Tech Symposiums are Heading to Six Cities in Europe in May!

by Swamy Irrinki on SiFive
Hello Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam Our 2019 global symposiums and workshops have been hugely successful in promoting the RISC-V ISA and fostering expansive collaboration within the open-source community. It's invigorating to see how the worldwide semiconductor ecosystem is energized and mobilized by the open ISA. One of the areas receiving the most attention is embedded intelligence. The RISC-V ISA is enabling designers and innovators to actively pursue ...

lowRISC at the SiFive Symposium in Cambridge

by LowRISC on lowRISC on lowRISC
teaser image Several lowRISC team members attended the SiFive Symposium in our home town of Cambridge on May 13th 2019, a lovely sunny day. Imagination Technologies were co-hosting with SiFive, and we heard from both companies. Krste Asanovic, chairman of the board at the RISC-V Foundation, gave a great introduction to RISC-V and progress so far. Naveed Sherwani, CEO of SiFive, talked us through their silicon design platform and future services. We also heard from SecureRF and IAR Systems. Alex gave a ...

OpenPiton+Ariane Tutorials in June

by Jonathan Balkind on OpenPiton Blog
teaser image We are excited to announce two OpenPiton+Ariane tutorials this June! Now is your chance to get hands-on with the RISC-V hardware research platform. The first tutorial is part of the Week of Open Source Hardware (WOSH) in conjunction with the RISC-V Workshop Zurich. It is a half-day tutorial on Thursday afternoon, June 13th, at ETH Zurich, Switzerland. Interested attendees can register here. The second tutorial is in conjunction with ISCA/FCRC 2019 in Phoenix, Arizona. It is a half-day ...

OTA: DAB/DAB+ via ODR-mmbTools, IQ Server for a Pi, LimeSDR on a Nintendo Switch, and More

by Gareth Halfacree on MyriadRF
Community member Godfrey L has published a multi-part series on using a LimeSDR and the ODR-mmbTools software bundle to transmit Digital Audio Broadcasting (DAB) signals. “My journey on the reason to use LimeSDR and ODR-mmbTools for DAB/DAB+ transmission started from the announcement that Raspberry Pi could transmit FM station all by itself,” Godfrey explains. “I said alright, let me try with LimeSDR then since it can transimit and receive almost everything. Well on that front it took me to ...

Seeed Studio Opens Pre-Orders for RISC-V-based Grove AI HAT Board

by Gareth Halfacree on FOSSi – AB Open
Seeed Studio has begun taking pre-orders for its Grove AI HAT for Edge Computing, an artificial intelligence-focused accelerator add-on for the Raspberry Pi which is based on the RISC-V Kendryte K210 processor. Based on the Sipeed MAIX M1 module, a development board for which the company crowdfunded late last year, the Grove AI HAT features a dual-core 64-bit RISC-V CPU running at 600MHz along with a 16-bit neural network co-processor dubbed the Kendryte Processing Unit (KPU), a dedicated ...

Verilator - Verilator 4.014 Released

by Wilson Snyder on Veripool: News
Verilator 4.014 2019-05-08 Add --trace-fst-thread. Support '#' comments in $readmem, bug1411. [Frederick Requin] Support "'dx" constants, bug1423. [Udi Finkelstein] For FST tracing use LZ4 compression. [Tony Bybell] Add error when use parameters without value, bug1424. [Peter Gerst] Auto-extend and WIDTH warn on unsized X/Zs, bug1423. [Udi Finkelstein] Fix missing VL_SHIFTL_ errors, bug1412, bug1415. [Larry Lee] Fix MinGW GCC 6 printf formats, bug1413. ...

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Last updated 21 July 2019 15:00 UTC