Planet LibreCores

Verilator - Verilator 3.912 Released

by Wilson Snyder on Veripool: News
Verilator 3.912 2017-09-23 Verilated headers no longer "use namespace std;" User's code without "std::" prefixes may need "use namespace std;" to compile. Support or/and/xor array intrinsic methods, bug1210. [Mike Popoloski] Support package export, bug1217. [Usuario Eda] Fix ordering of arrayed cell wide connections, bug1202 partial. [Mike Popoloski] Support module port parameters without defaults, bug 1213. [Mike Popoloski] Add performance information ...

Become a contributor or contractor

by FOSSi Foundation on FOSSi Foundation - News & Posts is a modern portal for Free and Open Source Silicon (FOSSi). Our aim is that it becomes the entry point to find and promote high quality free and open source digital IP blocks, free and open source platforms and free and open EDA tools. The focus is on user collaboration, for example by recommendations, and providing a simple interface to understand the fitness of a project. is currently under development and needs constant improvement. In the next future we ...

Major changes in Open SoC Debug ahead!

by Open SoC Debug on
Over the last roughly two years, Open SoC Debug has grown into a reliable debugging tool for the needs of lowRISC and OpTiMSoC. A lot of effort went into fixing small bugs to improve reliability and to add some features such as the emulated UART device, UART-DEM. And it was worth the effort, as we’ve seen over the summer when we added Linux support to OpTiMSoC. Control flow traces generated by the CTM modules, as well as the UART-DEM module were major enablers for this work. This work has ...

What's going on at OpTiMSoC?

by OpTiMSoC on OpTiMSoC
Each year in September or early October the OpTiMSoC team attends ORConf, and this year was no exception. In addition to exchanging a lot of ideas with friends and other open source enthusiasts, ORConf presents itself as a good opportunity to reflect on what has happened in OpTiMSoC land over the last year. As it turns out, there’s a lot we forgot to talk about before! OpTiMSoC got initial Linux support, thanks to the great work of Pedro during his Google Summer of Code. See this blog ...

lowRISC tagged memory OS enablement

by LowRISC on lowRISC
This summer, we were fortunate enough to have Katherine Lim join the lowRISC team at the University of Cambridge Computer Laboratory as an intern. Katherine’s focus was on operating system and software enabled for lowRISC’s tagged memory, building upon our most recent milestone release. As Katherine’s detailed write-up demonstrates, it’s been a very productive summer. The goal of this internship was to take the lowRISC hardware release, and demonstrate kernel support and software support ...

We're hiring! Work on making open source hardware a reality

by LowRISC on lowRISC
We are looking for a talented hardware engineer to join the lowRISC team and help make our vision for an open source, secure, and flexible SoC a reality. Apply now! lowRISC C.I.C. is a not-for-profit company that aims to demonstrate, promote and support the use of open-source hardware. The lowRISC project was established in 2014 with the aim of bringing the benefits of open-source to the hardware world. It is working to do this by producing a high quality, secure, open, and flexible ...

Clocks for Software Engineers

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image If you have a software background and you want to pick up digital design, then one of the first things you need to learn about early on is the concept of the clock. To many software engineers turned beginning Hardware Description Language (HDL) designers, the concept of a clock is an annoyance. Without using a clock, they can turn HDL into a programming language–with $display’s, if’s, and for loops like any other programming language. Yet the clock that these beginning designers ignore ...

All Aboard, Part 5: Per-march and per-mabi Library Paths on RISC-V Systems

by Palmer Dabbelt on SiFive
A previous blog described how the -march and -mabi command-line arguments to GCC can be used to control code generation for the sources you compile as a user, but most programs require linking against system libraries in order to function correctly. Since users generally don’t want to compile every library along with their program, either because they’re too complicated or because they’re meant to be shared, a mechanism is needed for linking against the correct set of system libraries to ...

Demonstrating the improved PWM waveform

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image This post follows our prior post titled Reinventing PWM. A reader has commented to me that I hadn’t posted any test bench or other method to prove that this module works. Since I also think that such a test would be beneficial, I’ve created a test bench and demonstration which we will examine below. Most of the parts and pieces of our test code, and certainly the methodology, could easily be applied to test just about any Digital Signal Processing (DSP) system. In short, we’ll put a test ...

OTA: LimeSDR Mini, GNU Octave, SDR on a Watch and More

by Gareth Halfacree on Myriad
Lime Microsystems has officially opened a crowdfunding campaign for the LimeSDR Mini, a reduced-size and reduced-cost version of the LimeSDR which offers one TX and one RX channel for just $99 for Early Bird backers and $139 thereafter. Taking place on Crowd Supply over the next month – the same platform used to launch the original LimeSDR – the campaign seeks to raise $100,000 to produce the LimeSDR Mini, but those who already own a LimeSDR needn’t worry about their device becoming ...

Building a high speed Finite Impulse Response (FIR) Digital Filter

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image Some time ago, an individual posted on Digilent’s forum that he wasn’t able to get Xilinx’s Finite Impulse Response (FIR) filter compiler generated code to work. While I can understand that there are good reasons for using a FIR compiler, this individual was attempting to low-pass filter a signal with less than a handful of taps. No wonder why he was getting frustrated when he didn’t see much difference in the filtered signal. He’s not alone. Indeed, I was answering forum posts from a ...

Even I get stuck in FPGA Hell

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image This site is dedicated to keeping students and other digital design developers out of FPGA Hell: that state in the design process where your design doesn’t work, and you have absolutely no clue why not. I’d like to present myself as immune from ever having that problem. How else shall I be respected as a teacher of others who can teach students how to avoid this problem? Today, though, I have a confession to make: I get stuck in FPGA Hell from time to time as well. By the grace of the ...

ORConf 2017 Round-up

by FOSSi Foundation on FOSSi Foundation - News & Posts
ORConf 2017 came to a close last Sunday, and on behalf of the FOSSi Foundation I’d like to thank all who attended, presented and sponsored the event! Hebden Bridge was a fantastic setting; a beautiful northern English town nestled in a valley, complete with gushing river, canals with narrowboats, verdant hillsides and northern stone buildings. The Hebden Bridge town hall was a great venue, recently renovated, we were hosted in the Waterfront Hall which provided the sound of the river ...

LimeSDR Made Simple Part 5: Putting Software in SDR

by Karl Woodward on Myriad
teaser image This is the fifth instalment of LimeSDR Made Simple and in the last we explored the software side of the software-defined radio, using the relatively simple to use dataflow programming environment, Pothos. Quite a break from the previous articles where we went into detail of the input stages of the LimeSDR. This time we will try to look a little deeper under the hood at some code based examples. A quick recap Software-defined radio (SDR) is defined on Wikipedia as: “a radio communication ...

Glad I went to ORCONF

by ZipCPU on The ZipCPU by Gisselquist Technology
Just a quick post today to thank the individuals who made ORCONF this year such a great success! The staff did a wonderful job setting up the conference, and I learned a lot from all those present with whom I had a chance to talk. When it came my turn, I presented both an update on the ZipCPU, as well as telling everyone about AutoFPGA. I’ve also posted the final slides for both projects on line, in case you weren’t able to go and would like to see what I presented. The ZipCPU ...

RISC-V 101 Webinar

by Jack Kang, vice president of product and business development, SiFive on SiFive
This one-hour webinar is for Embedded Developers who are interested in learning more about the RISC-V architecture. It covers areas such as the Register File, Instruction Types, Modes, Interrupts, and Control and Status Registers. Prior knowledge of RISC-V is not necessary, but having a basic understanding of Computer Architecture is beneficial. Check out the webinar recording here!

All Aboard, Part 4: The RISC-V Code Models

by Palmer Dabbelt on SiFive
The RISC-V ISA was designed to be both simple and modular. In order to achieve these design goals, RISC-V minimizes one of the largest costs in implementing complex ISAs: addressing modes. Addressing modes are expensive both in small designs (due to decode cost) and large designs (due to implicit dependencies). RISC-V only has three addressing modes: PC-relative, via the auipc, jal and br* instructions. Register-offset, via the jalr, addi and all memory instructions. Absolute, via the ...

7th RISC-V Workshop Registration

by Rick O'Connor on RISC-V Foundation
teaser image 7th RISC-V Workshop November 28-30, 2017 Registration for the 7th RISC-V Workshop, hosted by Western Digital in Milpitas California on November 28-30, 2017 is now open.  As with past workshops, our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set. This will be a three day event broken down as ...

Off to ORCONF-2017!

by ZipCPU on The ZipCPU by Gisselquist Technology
After a year of waiting, it’s time for ORCONF. If you are not familiar with ORCONF, then allow me to encourage you to examine their web-page, and look over the abstracts of the presentations that will be given this year. Looks like it will be quite the lineup. This year, I’ll be giving two presentations. My first presentation will be a quick update on the ZipCPU. Since last year, the ZipCPU has been updated so as to support … 8-bit byte-level access across the 32-bit bus. ...

Building upstream RISC-V GCC+binutils+newlib: the quick and dirty way

by LowRISC on lowRISC
There are a number of available options for building a RISC-V GCC toolchain. You might use the build system from the riscv/riscv-tools repository, or investigate toolchain generators such as crosstool-ng. However in the case of riscv-tools, it’s not always clear how this corresponds to the code in the relevant upstream projects. When investigating a potential bug, you often just want to build the latest upstream code with as little fuss as possible. For distribution purposes you’d probably ...

Reinventing PWM

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image A common beginners FPGA task is to build a Pulse Width Modulated (PWM) signal. Such signals, when fed into an appropriately modified amplifier, can be used to create an audio signal that can then be heard. Indeed, you might think of this as a poor man’s digital to analog converter, since the circuitry required to turn a PWM signal into an audio signal is quite minimal. Likewise, PWM audio hardware ($10 USD) can be cheaper than the corresponding I2S based Digital to Analog Converter ($15 ...

GSoC 2017 Project: Integration of the OpenRISC Linux Port into OpTiMSoC

by OpTiMSoC on OpTiMSoC
teaser image Linux was ported to OpTiMSoC during the 2017’s Google Sumer of Code. This blog post details the work that was accomplished during the project; and as well the work that was left to be tackled. To port Linux to OpTiMSoC, a new manycore configuration with a Host Tile was designed and implemented. The Host Tile runs OpenRISC Linux and communicates with applications running on Computing Tiles via message-passing through the Network-on-Chip (NoC). Overall, the communication infrastructure is ...

Big Money Engineering Integrity

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image Every now and then, the ZipCPU blog includes a short discussion on engineering ethics. Our last post challenged you with the question, what would cause you to lie? Below is a discussion from some of my own experience, illustrating the extent to which an integrity problem can destroy the foundation of solid engineering. Before I started Gisselquist Technology, I had my own moral strength and integrity challenged. Many years ago, I was asked to join the government team managing ...

CORDIC part two: rectangular to polar conversion

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image We’ve now discussed three methods of generating sine waves: a simple table lookup approach, a quarter wave table lookup approach, and most recently a CORDIC approach. Today, let’s take another look at the CORDIC approach. In particular, the CORDIC algorithm can also be used in “reverse”–not to rotate a vector by some amount, but rather to find out what angular rotation that vector has as in Fig 1. Fig 1: Using a CORDIC for rectangular to polar conversion This “reverse” CORDIC can be ...

Verilog-Perl - Verilog-Perl 3.440 Released

by Wilson Snyder on Veripool: News
Verilog::Language 3.440 2017-08-31 Support for buses and concats in Netlist, msg1626. [by Stefan Tauner] Support pragma protect begin_protected/end_protected, msg2313. [George Cuan]

OTA: Beginner’s Guides, PocketEPC, GRAVES and More

by Gareth Halfacree on Myriad
Karl Woodward’s LimeSDR Made Simple series continues on the Myriad-RF blog with two new hands-on posts: a simple practical example and implementing an FM radio receiver through Pothos. Following on from the first and second entries in the series, Karl’s latest posts are designed to take the theory into the realm of practice. The third entry covers the use of the self-test example to practice creating a functional application without the need for external hardware like antennas; the fourth ...

Happy sixth birthday FuseSoC

by Olof Kindgren on Tales from Beyond the Register Map
teaser image Today FuseSoC is turning six years old. That is probably something like 35 in software years. It has had a colourful past with some breakups and an identity crisis, but has now settled down and realized that it will not change the world in the same way that it used to think. It has spawned a few child projects which are not yet able to handle themselves in the world and still need their loving parent project. Being 35 also means that we can expect a FuseSoC middle-age crisis in a few years ...

Using a CORDIC to calculate sines and cosines in an FPGA

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image We’ve now presented two separate algorithms that can be used for calculating a sine wave: a very simple sinewave table lookup, and a more complicated quarter-wave table lookup method. Both of these approaches used only a minimum number of clocks, although their precision was somewhat limited. Today, let’s look at how to implement a COordinate Rotation DIgital Computer (CORDIC) algorithm within an FPGA. Fig 1: The CORDIC problem description If you’ve never worked with ...

LimeSDR Made Simple Part 4: to Pothos and Beyond

by Karl Woodward on Myriad
teaser image It’s time again for another bite sized chunk of LimeSDR. This is the fourth post in the series and while this will be our second practical exercise, it does build upon the whole series and so if you have not read the first three articles, you are advised to take a look now (Part 1 – Part 2 – Part 3) Last time we went though the self-test.ini and pretty much broke the example in most ways possible. This time we’ll try to use what we have learnt to improve a signal and create our very first ...

Verilator - Verilator 3.908 Released

by Wilson Snyder on Veripool: News
Verilator 3.908 2017-08-28 Support x in $readmem, bug1180. [Arthur Kahlich] Support packed struct DPI imports, bug1190. [Rob Stoddard] Fix GCC 6 warnings. Fix compile error on unused VL_VALUEPLUSARGS_IW, bug1181. [Thomas J Whatson] Fix undefined VL_POW_WWI. [Clifford Wolf] Fix internal error on unconnected inouts, bug1187. [Rob Stoddard]

Welcome - The SiFive Download, Part II

by Jack Kang, vice president of product and business development, SiFive on SiFive
On August 15, we announced that regarded industry veteran Naveed Sherwani has joined SiFive as CEO. We invited him to share his vision for the company and his optimism for fomenting a revolution in the semiconductor industry. Check out the full newsletter here!

Adieu, Google Summer of Code 2017

by Hatim Kanchwala on
The Google Summer of Code 2017 is now in its final stages, and I’d like to take a moment to look back at what goals I accomplished, what remains to be realised and what I learned. The EDSAC Museum on FPGA project is part of a broader movement to revive interest in the early first generation British computer, the Electronic Delay Storage Automatic Calculator. 2017 will mark the 60th anniversary of the British Computing Society (BCS) whose founder, Maurice Wilkes, is the designer of the ...

GSoC Project Report : Quality Metrics for Projects listed on

by Amitosh Swain Mahapatra on The CharStream
teaser image lists free and open source “IP Cores” on the website for the community to view and use. Currently the website extracts the project readme and license and renders them on the project page, along with links to the project homepage and git repository. A user browsing for cores on LibreCores will be interested to know the quality of the project’s code so as to determine how useful the project will be to them. A part of such information can be inferred from the project’s source ...

OSDDI: lowRISC, Alex Bradbury

by Andrew Back on OSDDI – AB Open
lowRISC is a fantastic initiative to build a fully open source, Linux-capable, 64-bit RISC-V based system-on-chip. Not only this, but a SoC design with additional interesting features such as programmable I/O — think along the lines of XMOS devices — and tagged memory. At the present time the design can be targeted to FPGA, but there are plans for volume silicon and a low cost development board that utilises this. In this interview filmed in April of last year, lowRISC Director and ...

All Aboard, Part 3: Linker Relaxation in the RISC-V Toolchain

by Palmer Dabbelt on SiFive
Last week’s blog entry discussed relocations and how they apply to the RISC-V toolchain. This week we’ll be delving a bit deeper into the RISC-V linker to discuss linker relaxation, a concept so important it has greatly shaped the design of the RISC-V ISA. Linker relaxation is a mechanism for optimizing programs at link-time, as opposed to traditional program optimization which happens at compile-time. This blog will follow an example linker relaxation through the toolchain, demonstrate an ...

Updates to Sodor - Port to Fpga

by Kritik Bhimani on Kritik Bhimani
Tilelink specification can be accessed here Making sodor capable of speaking Tilelink had the following benefits access to various other bus protocols via tilelink adapters doc tilelink adapters src access to various peripherals of different protocols via sifive-blocks simple example usage of new open bus standard tilelink, though there are a lot more examples there in rocket-chip but hopefully the one in sodor is easier to understand a step towards making sodor as an on-boarding ...

Updates to Sodor - Debug Module, Priv1.10

by Kritik Bhimani on Kritik Bhimani
All cores now on Chisel3 Since the last blog post only ucode was the one which didn’t generate verilog using chisel3. ucode initially used MuxLookup to find the appropriate ucode address to jump to when a new instruction was fetched but the problem was that now dispatch table was made of BitPat to Int(address) mappings instead of earlier UInt to Int and so muxlookup somehow didn’t allow using BitPat to index to correct mapping when the array of mappings were composed of UInt to Int. This ...

Building a quarter sine-wave lookup table

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image The last time we discussed how to create a sinewave, we discussed the way to make a very simple sinewave. from a LUT-based table lookup. We limited that sinewave. to an 8-bit table for simplicity, although it could easily be extended to a much larger table. Today, let’s expand this concept to a sinewave. that uses a quarter wave table made from Block RAM. Such a table uses only a fourth of the block RAM resources required by a full table, although it does require some extra logic to ...

Debugging your soft-core CPU within an FPGA

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image We’ve already looked at the requirements for debugging a CPU in general, as well as how to debug a CPU within a Verilator based simulation. Let’s now return to this topic and take a look at how to modify your soft-core CPU so that you can debug it once it is placed within an FPGA. Fig 1: Soft-Core CPU H/W Debugging Needs When we discussed the general needs of a debugger, we used a figure similar to Fig 1. to describe a CPU’s debugging needs. The left column, debugging the CPU’s while ...

Our New Partnership with Rambus and the DesignShare Economy

by Jack Kang, vice president of product and business development, SiFive on SiFive
As we continue to expand our product offerings to better serve the rapidly growing RISC-V and SiFive community, we are always looking to work with companies (big and small) who share our vision. On Monday, we proudly announced that we will form a new partnership with Rambus, a leader in the digital security, semiconductor and IP industries, to help us take the next step in democratizing access to custom silicon. Through the partnership, we will be able to offer Rambus’ cryptography ...

The ZipCPU's pipeline logic

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image Now that we’ve discussed some general pipeline strategies, it’s time to take a look at how pipelining can work within a simple, in order, pipelined CPU. Let’s take a look, therefore, at the ZipCPU and see how it handles its pipeline logic. What you’ll see is that the ZipCPU uses a variant of the handshaking strategy we discussed earlier. If you are unfamiliar with the ZipCPU, the ZipCPU has five pipeline stages, as shown in Fig 1. Fig 1: The ZipCPU Pipeline Structure There’s the ...

OSDDI: Director's commentaries

by Olof Kindgren on Tales from Beyond the Register Map
Andrew Back of AB Open and FOSSi Foundation has been working on this great series of interviews called Open Source Digital Design Insights, in which he has been interviewing some of the great minds of the Free and Open Source Silicon movement (+ me). In the fourth episode the turn has come to me. As I watch the video myself, I realize how quickly time moves in the open source silicon world and how many things that have happened since then. I would therefore like to take the opportunity to ...

Rules for new FPGA designers

by ZipCPU on The ZipCPU by Gisselquist Technology
It’s a new school year! For all you new students out there, please accept my welcome to the wonderful world of digital design. I am neither a student nor a professor, and yet I have helped many students through their projects on the Digilent forum, as well as on freenode IRC. This post is an outgrowth of my own experience counseling beginners on Digilent’s forums. Indeed, sometimes I feel like I’m a broken record there repeating over and over the same rules for newbies. So, before you ...

All Aboard, Part 2: Relocations in ELF Toolchains

by Palmer Dabbelt on SiFive
Our first stop on our exploration of the RISC-V toolchain will be an overview of ELF relocations and how they are used by the RISC-V toolchain. We’ll shy away from discussing linker relaxations and their impact on performance for a follow-up blog post so this doesn’t get too long. The example has been carefully constructed to be unrelaxable as to avoid confusion. Additionally we’re only going to discuss the relocations used by statically linked executables, avoid discussing position ...

Two of the Simplest Digital filters

by ZipCPU on The ZipCPU by Gisselquist Technology
teaser image I’d like to spend some time discussing Digital Filtering on this blog. This is going to be a bit of a difficult topic, however, in that I don’t intend to discuss how to design a Digital Filter, nor do I intend to discuss how to evaluate the design of a digital filter, nor do I intend to discuss aliasing. These are all vital topics necessary for understanding what a digital filter is, as well as understanding whether or not a digital filter even works. They are also vital topics to ...

OSDDI: OpenRISC, Olof Kindgren

by Andrew Back on OSDDI – AB Open
The OpenRISC processor has been around for a good number of years and it has found use in a NASA satellite and Samsung digital televisions, to name just two applications. In this instalment of Open Source Digital Design Insights, long time OpenRISC contributor and open source developer, Olof Kindgren, provides an introduction to the project, it’s background, sponsors and typical uses. Olof also explains how OpenRISC led to the open source digital design and embedded systems conference, ...

RISC-V Foundation to Showcase Growth of New Architecture at Hot Chips 29

by Dave Hicks on RISC-V Foundation
teaser image Foundation members demo RISC-V-based implementations WHERE Hot Chips 29, Flint Center for the Performing Arts, 21250 Stevens Creek Blvd, Cupertino, Calif., 95014 WHEN Sunday, Aug. 20 to Tuesday, Aug. 22, 2017 WHAT RISC-V® Foundation will exhibit at Hot Chips 29, showcasing the momentum of its Instruction Set Architecture (ISA), the industry’s first open, free architecture. RISC-V founding member, SiFive, will host a session detailing the industry’s first open-source RISC-V ...

LimeSDR Made Simple Part 3: A Practical Example

by Karl Woodward on Myriad
teaser image This is the third in a series of posts that aims to make the LimeSDR platform a little more approachable. Again we will build upon previous examples and if you missed the last in the series it is available here. Last time we looked at the RX stage in detail with the aim of understanding a good proportion of the options within Lime Suite. While the last few posts have been theory, this will be a little less science heavy and we finally can get our hands dirty and power on the ...

All Aboard, Part 1: The -march, -mabi, and -mtune arguments to RISC-V Compilers

by Palmer Dabbelt on SiFive
Before we can board the RISC-V train, we’ll have to take a stop at the metaphorical ticket office: our machine-specific GCC command-line arguments. These arguments all begin with -m, and are all specific to the RISC-V architecture port. In general, we’ve tried to match existing conventions for these arguments, but like pretty much everything else there are enough quirks to warrant a blog post. This blog discusses the arguments most fundamental to the RISC-V ISA: the -march, -mabi, ...

FuseSoC 1.7

by Olof Kindgren on Tales from Beyond the Register Map
Lock up your wifes and daughters! FuseSoC 1.7 has been unleashed on the world. This unstoppable force will organize your HDL dependencies and provide abstractions to your EDA tools without giving you a chance to defend yourself.Actually, there's not that much new on the surface of this release. Most of the work has been spent on internal refactoring in order to bring in two new major features for the next cycle. The first of these is a separation of the frontend - which handles reading core ...

RS Components sponsors Open Source Digital Design Conference

by FOSSi Foundation on FOSSi Foundation - News & Posts
LONDON, UK, 11 August, 2017 - RS Components (RS), the trading brand of Electrocomponents plc (LSE:ECM), the global distributor for engineers, is sponsoring ORConf, an open source digital design and embedded systems conference that covers from the transistor level up to Linux user space and beyond — featuring presentations and discussion on free and open source IP projects, implementations on FPGA and in silicon, verification, EDA tools, licensing and embedded software, to name but a ...

OSDDI: SHAKTI Processor, IIT Madras

by Andrew Back on OSDDI – AB Open
This latest instalment of Open Source Digital Design Insights is once again from interviews filmed back at ORConf 2015 in Geneva, and this time on the RISC-V based SHAKTI processor from IIT Madras. A project that aims to build 6 processor variants that range from microcontroller up to HPC class silicon, with processor interconnect and experimental security features also being developed. Unfortunately, the quality of this video recording is not fantastic, on account of the filming location ...

All Aboard, Part 0: Introduction

by Palmer Dabbelt on SiFive
I’m Palmer Dabbelt, a software engineer at SiFive and a maintainer of various RISC-V ports. I’ve been working with the RISC-V ISA for a few years, and it’s finally starting to get ready for prime-time. We’re not yet upstream in Linux or glibc, but hopefully by the end of the year we’ll have the core set of system software in the relevant upstream repositories – at which point distributions can begin porting to RISC-V and users can begin using our software. I started working with ...

OTA: Reverse Engineering, Sky-High LoRaWAN, Budget Radio Astronomy, and More

by Gareth Halfacree on Myriad
teaser image If you subscribe to OTA via email you may have missed Karl Woodward’s second entry in the new LimeSDR Made Simple series, published earlier this week, which aims to introduce you to the concepts you’ll need to get the most from SDR in the real world. Following the first entry in the series last month, which covered core SDR concepts and the physical connections on the LimeSDR itself, Karl’s second post goes into solving impedance matching and takes a close look at the LMS7002M chip – the ...

LimeSDR Made Simple Part 2: matching, LMS7002M RX & I/Q

by Karl Woodward on Myriad
teaser image This is the second in a series of posts on the LimeSDR platform, that aim to demystify using SDR in the real world and programming a simple example with confidence, through bite sized chunks. Last time we explored what the LimeSDR is and what it can achieve. In this article we will look into the LMS7002M and the RF input/output, which is where a lot of the magic (otherwise known as RF) happens. We also discussed the multiple RF connections and the underlying reason these are required. ...

Prelude to orconf 2017 - Open Source Digital Design Insights

by FOSSi Foundation on FOSSi Foundation - News & Posts
Over the years orconf has grown to be the most prominent conference for open source silicon, and with presentations from some of the most interesting open source silicon projects lined up, this year does not seem to be an exception. Our audience can expect to learn about brand new projects as well as updates from long-running ones. But of equal importance to the people on stage are the ones in the audience. This is the best chance of the year to discuss with and gain insights from some of ...

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Last updated 25 September 2017 04:00 UTC