Planet LibreCores

Dover Microsystems Details Shift to Open-Source Renode Framework

by Gareth Halfacree on FOSSi – AB Open
Dover Microsystems’ Greg Sullivan has written of how Antmicro’s open-source Renode development framework has considerably decreased the length of his company’s design cycle – showcasing why the framework is becoming increasingly popular. Built with embedded platforms and the Internet of Things (IoT) in mind, Renode allows for the execution, debugging, and testing of embedded software unmodified on a standard off-the-shelf PC, and is proving popular for those designing the hardware itself. ...

Western Digital Boasts of “Gratifying” SweRV Response, Releases FPGA Reference Design

by Gareth Halfacree on FOSSi – AB Open
Western Digital has announced a strong response to the release of its RISC-V based open silicon SweRV Core, along with the availability of an official implementation for field-programmable gate array (FPGA) use. Announced back in December 2018 as part of a company-wide initiative to transition data processing products away from proprietary cores to alternatives based on the RISC-V instruction set architecture (ISA), released in January this year, and the subject of a deep-dive analysis by ...

OTA: AMSAT-F QO-100 Transmissions, SDR Added to RSGB Syllabus, New limeSNA, and More

by Gareth Halfacree on MyriadRF
The second AMSAT-F Recontre Radiomateur Spatiale was a special one, for an out-of-this-world reason: its lectures were transmitted to a global audience using a LimeSDR Mini and the Es’hail-2 (QO-100) satellite. Evariste Courjaud explained the transmission chain in an interview published this week on the Lime Micro community hub: “The chain was: a PC running Vmix (video mixer) to NDI [Network Device Interface] (over Ethernet) to a PC modulator. On the PC modulator: NDI to ffmpeg H.264 ...

RISC-V Foundation Finalises Schedule for RISC-V Workshop Zurich

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has released the agenda for its RISC-V Workshop Zurich, to be held on the 11th-13th of June as part of the larger Week of Open Source Hardware (WOSH). Following its call for speakers, which closed back in February, the RISC-V Foundation has firmed up the schedule for the three-day RISC-V Workshop Zurich 2019 – though only the first two of these days are open to the general public, with the latter being reserved for RISC-V Foundation members. The agenda includes a ...

CRU: Open Source Awards 2019, MIPS Open, RISC-V Priorities, and More

by Gareth Halfacree on FOSSi – AB Open
Open UK, a membership organisation dedicated to promoting and supporting the use of free and open source standards and software in the UK, has announced a call for nominations for the UK Open Source Awards 2019. “The awards have happened five times in the last 10 years, but not since 2015,” explains Open UK’s Amanda Brock. “With the massive move to adoption of open source across businesses and its rightful place as mainstream in our society by being recognised through events like the Red ...

El Correo Libre Issue 14

by Gareth Halfacree on LibreCores - Medium
teaser image Healthy Signs for the Free and Open Source Silicon Movement I really feel like the whole Free and Open Source Silicon movement has finally taken off. Many from our community have been around for ten years or more, but only over the last few years have we really seen a steadily increasing interest in open silicon design and engineering design automation tools. Many awesome projects are becoming very popular and attracting new folks, and we are seeing many companies, large enterprises, ...

chisel 3.1.7

by Jim Lawson on Chisel
We’ve recently (3/20/2019) published Chisel v3.1.7 and FIRRTL v1.1.7 and compatible updates to the rest of the BIG6 Chisel projects – chisel-testers v1.2.9, firrtl-interpreter v1.1.7, treadle v1.0.5, and dsptools v1.1.8. This release of the tool set consists of bug fixes. Please review the notes under the releases section of the relevant repository and the linked individual pull requests and issues for the details of the changes. As usual, your feedback is welcome.

SPDX Project Adds Open Hardware Licences to Licence List

by Gareth Halfacree on FOSSi – AB Open
The Software Package Data Exchange (SPDX) project, the initial standard for which AB Open’s Andrew Back acted as a contributor, has released the latest version of its SPDX Licence List – and it now includes open hardware licences. Made for ease of reference and to simplify identification of licences and their applied exceptions in documentation, source files, and elsewhere, the SPDX Licence List is now in Version 3.5 and includes both the licences themselves and a list of commonly found ...

Calista Redmond Outlines “Key Priorities” for the RISC-V Foundation

by Gareth Halfacree on FOSSi – AB Open
Calista Redmond, newly-appointed chief executive of the RISC-V Foundation, has highlighted the organisation’s key priorities for accelerating adoption and deployment of the open instruction set architecture (ISA) and related technologies. “With the significant uptick in RISC-V adoption over the past few years, the RISC-V Foundation Technical Committee has made it a priority to prepare the RISC-V base ISA and standard extensions for ratification,” Calista, who was appointed chief executive ...

Latch-Up Portland venue, speakers and sponsors

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image The FOSSi Foundation announced Latch-Up (latchup.io), earlier this year - its annual North American open source digital design conference in the mold of ORConf. Latch-Up opens a new chapter for the FOSSi Foundation, with it being the first event in the spirit of ORConf held in North America. Latch-Up is a community-focused conference for open source semiconductor, digital design and embedded systems professionals and enthusiasts. Expect presentations on a wide range of topics; open source ...

Freedom Studio Version 2019.03

by Drew Barbier on SiFive
teaser image Ever since we launched Freedom Studio in 2017, it has been a great way to quickly and easily get started writing code for SiFive platforms, whether those platforms are development boards such as the HiFive1 Rev B, Digilent Arty FPGA, or even our testbench, which ships along with SiFive IP deliverables. Freedom Studio is based on the industry-standard Eclipse IDE and comes with several plugins and pre-built tools supporting Windows, macOS, and Linux, to help with embedded development for ...

Wave Computing Announces First MIPS Open Release

by Gareth Halfacree on FOSSi – AB Open
Wave Computing has made the first public release under its MIPS Open initiative, announced back in December 2018, though its licence terms lag behind competitors like RISC-V. Following the sale of MIPS by Imagination Technologies, new owner Wave Computing came up with a plan to boost the popularity of the instruction set architecture (ISA): take on free and open source silicon darling RISC-V head-to-head with MIPS Open, an initiative that would see the company release its latest MIPS core ...

OTA: LimeSNA, QO-100 Projects, a Self-Tuning Antenna, and More

by Gareth Halfacree on MyriadRF
Forum user Peter ‘nepe’ Kis has published a scalar network analyser (SNA), developed using the LimeSDR Mini, which displays its user interface in the user’s web browser: limeSNA. Based on the pyLMS7002Soapy example, Peter’s software has been tested with the LimeSDR Mini and should be compatible – or easily made so – with other LimeSDR family members. It’s also under continuous improvement: “I have lots of ideas for how i can improve the tool,” he explains in an interview published to the ...

LLVM 8.0.0 Release Adds RISC-V Support to lld Linker

by Gareth Halfacree on FOSSi – AB Open
The LLVM project has announced the release of LLVM 8.0.0, which brings with it a wealth of new features including the first support for the open RISC-V architecture in the lld linker. Released this week, LLVM 8.0.0 includes a range of enhancements to the compiler and toolchain collection. “This release contains the work on trunk up to Subversion revision r351319, plus work on the release branch,” explains Hans Wennborg. “It’s the result of the LLVM community’s work over the past six months, ...

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part I

by Camille Kokozaki on SiFive
teaser image SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing, Calista Redmond was just appointed the new CEO of the RISC-V Foundation). He shared a slide showing the growing RISC-V ecosystem from tools vendors, to IP/semi chip ...

PULP Platform Announces Silicon Labs Partnership

by Gareth Halfacree on FOSSi – AB Open
The Parallel Ultra-Low Power (PULP) Platform has announced that Silicon Labs has adopted the platform to extend and customise embedded processor cores in their integrated circuit designs. Now approaching its sixth year, having been launched by Luca Benini at the University of Bologna back in May 2013, the PULP Platform’s numerous projects include the Hero open heterogeneous research platform, the RISC-V Ariane core and extended OpenPiton+Ariane design in partnership with the OpenPiton ...

Verilator - Verilator 4.012 Released

by Wilson Snyder on Veripool: News
Verilator 4.012 2019-3-23 Add +verilator+seed, bug1396. [Stan Sokorac] Support $fread. [Leendert van Doorn] Support void' cast on functions called as tasks, bug1383. [Al Grant] Add IGNOREDRETURN warning, bug1383. Report PORTSHORT errors on concat constants, bug 1400. [Will Korteland] Fix VERILATOR_GDB being ignored, msg2860. [Yu Sheng Lin] Fix $value$plus$args missing verilated_heavy.h. [Yi-Chung Chen] Fix MSVC compile error, bug1406. [Benjamin ...

CRU: Season of Docs, Hardware Compression IP, a SweRV Deep-Dive, and More

by Gareth Halfacree on FOSSi – AB Open
Google has announced a new programme, designed to run alongside the Google Summer of Code, through which it aims to improve the quality of documentation in open source projects: the Season of Docs. Google’s Summer of Code (GSoC) is a popular programme through which student developers are partnered with mentor organisations and financially supported in working on collaborating with a variety of open-source projects through programming. The Season of Docs is, as the name suggests, focused ...

Boot SMP Linux on OpenPiton+Ariane

by Jonathan Balkind on OpenPiton Blog
teaser image OpenPiton release 11 (19-03-19-r11) is now available. This release brings two major improvements alongside a number of smaller bug fixes and improvements that you can see on our GitHub repository. In conjunction with the PULP Platform’s Ariane release 4.1, OpenPiton+Ariane boots SMP Linux on FPGA. This makes OpenPiton+Ariane the first Linux-booting, open-source, RISC-V system that scales from single-core to manycore. You can download our 1-core (Nexys Video Artix-7), 2-core (Genesys2 ...

Andrew Katz’ Survey of Open Processor Core Licensing Published

by Gareth Halfacree on FOSSi – AB Open
Andrew Katz, partner at the law firm Moorcrofts LLP, has published the results of a survey into free and open source silicon (FOSSi) licensing concentrating on processor cores – which includes AB Open’s Andrew Back among its interviewees. Andrew Katz’ report was commissioned by Western Digital, which recently released its own RISC-V based SweRV Core under a permissive licence, in early 2018; the version published this month in the journal International Free and Open Source Software Law ...

RISC-V Workshop Taiwan Slides Now Available

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has published slides from the RISC-V Workshop Taiwan, which took place earlier this month as a means of showcasing the ecosystem and highlighting both ongoing and future projects. “RISC-V Workshop Taiwan showcased the open, expansive and international RISC-V ecosystem, highlighting current and prospective projects and implementations that influence the future evolution of the RISC-V instruction set architecture (ISA),” the Foundation’s summary of the event explains, ...

Freedom Everywhere — Back for Everyone!

by David Lee on SiFive
HiFive1 Rev B: The Second Generation HiFive1 Dev Board and the Freedom Everywhere SoC, FE310 When SiFive launched the FE310 and HiFive1 in 2016, the product received a very warm and enthusiastic reception. The project received much more attention and traction than we could have ever hoped for. We were nominated for two ACE awards and the HiFive1 team won “Design Team of the Year”. In the short period of time since we launched the HiFive1, we have seen new RTOSes, software stacks, ...

Microsoft Opens Zipline Hardware-Implementable Compression Algorithm

by Gareth Halfacree on FOSSi – AB Open
Microsoft’s cloud computing division, Azure, has announced the release of its hardware-implementable compression algorithm Project Zipline under a permissive licence, as part of the Open Compute project (OCP). “Microsoft’s Project Zipline compression algorithm yields dramatically better results, up to 2X high compression ratios versus the commonly used Zlib-L4 64KB model,” claims Microsoft’s Kushagra Vaid. “Enhancements like this can lead to direct customer benefits in the potential for ...

OTA: LimeNET Micro Upgrades, Es’hail-2 Transmissions, and More

by Gareth Halfacree on MyriadRF
Backers of the LimeNET Micro are set to receive a boost in computing power and storage thanks to a last-minute switch in Raspberry Pi Compute Module model, while shipping has now been pushed to the end of March. “As you all know, there were quite a few changes to the original specification and we decided to go for USB transceiver interfacing, fully active PoE, and add camera and display LVDS interfaces, as well as a HDMI connector,” explains Lime Micro’s Zydrunas Tamosevicius in a campaign ...

Tom Verbeure’s Deep-Dive Into WD’s SweRV RISC-V Core

by Gareth Halfacree on FOSSi – AB Open
Tom Verbeure has published comments on a deep-dive of the Western Digital SweRV open-source RISC-V core, following a workshop at the Bay Area RISC-V Meetup earlier this year. Announced late last year and released under a permissive licence in January, the SweRV Core is Western Digital’s open-source implementation of the RISC-V instruction set architecture (ISA). It was also the subject of a deep-dive workshop at the Bay Area RISC-V Meetup, and it’s details from this workshop on which Tom ...

The First Leg of our Global Symposiums is a Wrap, and it was an Enormous Success!

by Purvi Shenoy on SiFive
teaser image We welcomed over 600 attendees to the SiFive Tech Symposiums in Austin, Mountain View and Boston. The feedback we received is flattering. We heard comments like, “You guys are going bold, and we love it!” and “SiFive has built a solid team with good breadth of business and technology expertise,” and “Very different take – and someone is addressing the pain point for hardware folks, finally!” There was a great deal of energy in the crowd, and people were thoroughly engaged all day long. ...

Calista Redmond Named as RISC-V Foundation CEO

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has announced the appointment of IBM alumnus Calista Redmond as chief executive officer, taking over from interim chief Martin Fink. Calista Redmond’s work history includes 20 years of senior-level management and alliance experience at companies including Affinity Lab and Articulated Impact, including 12 years at IBM where she was most recently the vice president of the IBM Z Ecosystem division and, prior to that, the president of the OpenPOWER Foundation. “I’ve always ...

El Correo Libre Issue 13

by Gareth Halfacree on LibreCores - Medium
teaser image FOSSi Hits the Prime Time Last week I visited a small RISC-V themed workshop in Munich, Germany — or so I thought. When I showed up there, a crowd of over 50 people from industry and academia was eager to hear what RISC-V is all about, and how open source offerings could make their lives easier. This clearly show that, even though FOSSi has been with us for a long time, it is now ready for prime time. Companies are thinking hard about how they could replicate the success of open source ...

Linux Foundation to Launch FOSSi-Focused CHIPS Alliance

by Gareth Halfacree on FOSSi – AB Open
The Linux Foundation has launched a new group, dubbed the CHIPS Alliance, through which it hopes to support the burgeoning free and open source silicon (FOSSi) ecosystem. Officially announced today by the Linux Foundation, the CHIPS Alliance includes as founding members Esperanto, SiFive, and Western Digital – all of whom have announced or shipped products based around the open RISC-V instruction set architecture (ISA) – alongside cloud and consumer computing giant Google. “Open ...

Seeed Details RISC-V Raspberry Pi AI HAT, Development Board

by Gareth Halfacree on FOSSi – AB Open
Seeed Studio has announced a new Grove AI HAT for the Raspberry Pi, designed for edge computing projects, based around the Sipeed MAIX-I 64-bit RISC-V system-on-module (SOM) – and, interestingly, it will also function as a standalone development board. Unveiled on the official Seeed forum by Elaine Wu, the new design uses the full-size Hardware Attached on Top (HAT) form factor to connect to a Raspberry Pi single-board computer via its 40-pin GPIO header. Its primary feature: a Sipeed ...

CRU: Amazon, Imagination Bet on RISC-V, Google Targets Edge Acceleration, and More

by Gareth Halfacree on FOSSi – AB Open
Amazon has announced that it has added support for the RISC-V open instruction set architecture (ISA) to the MIT-licensed FreeRTOS real-time operating system kernel. “RISC-V is a free and open ISA that was designed to be simple, extensible, and easy to implement. The simplicity of the RISC-V model, coupled with its permissive BSD licence, makes it ideal for a wide variety of processors, including low-cost microcontrollers that can be manufactured without incurring licence costs,” Amazon’s ...

FuseSoC 1.9.1 Brings Improved, Sphinx-Generated Documentation

by Gareth Halfacree on FOSSi – AB Open
Olof Kindgren has announced the release of FuseSoC 1.9.1, and it brings with it improved documentation produced using the Sphinx Python Documentation Generator. Having a useful end product should be the primary goal of all open-source projects, but it shouldn’t be viewed as the only goal: no matter how useful a tool may be, if it’s not usable it may as well not exist. Documentation is key to accessibility, and all-too-often overlooked – which is why Olof’s work to improve the documentation ...

Linux Kernel 5.0 Launches with New RISC-V Features, Fixes

by Gareth Halfacree on FOSSi – AB Open
Linus Torvalds has announced the release of Linux 5.0, the latest version of the Linux kernel, and once again it pulls in a range of improvements and new features for the RISC-V instruction set architecture (ISA). Linux has boasted support for the open RISC-V ISA for a while, now, to the point where it’s possible to build a fully-functional desktop using off-the-shelf hardware. That doesn’t mean there isn’t still work to do, however, and the launch of the Linux 5.0 kernel brings with it a ...

FOSSi Foundation Selected as Google Summer of Code Mentor Organisation

by Gareth Halfacree on FOSSi – AB Open
The Free and Open Source Silicon (FOSSi) Foundation has announced it has been selected once again to be a mentor organisation in the Google Summer of Code (GSoC) programme, and is looking for students to participate. A not-for-profit organisation founded with the aim of promoting and assisting with the development and deployment of free and open source silicon solutions, the FOSSi Foundation’s participation in the Google Summer of Code programme will see it acting as a mentor organisation ...

OTA: Es’hail 2’s Amateur Transponder, Cellular Satcom, Magma, and More

by Gareth Halfacree on MyriadRF
The amateur transponder on board the Es’hail-2 satellite, launched back in November, has been activated and qualified as ready for amateur use – and use it amateurs most certainly are. Launched in November 2018 by Qatari communications company Es’hailSat, the Es’hail 2 satellite is located at 25.5 degrees East and carries a 2.4 GHz Phase 4 transponder, a 10.45 GHz Phase 4 transponder, 250 kHz linear transponder, and an 8 MHz transponder for experimental digital modulation schemes and ...

Amazon Adds RISC-V Support to FreeRTOS Kernel

by Gareth Halfacree on FOSSi – AB Open
Amazon has announced that it has added support for the RISC-V open instruction set architecture (ISA) to the MIT-licensed FreeRTOS real-time operating system kernel. “RISC-V is a free and open ISA that was designed to be simple, extensible, and easy to implement. The simplicity of the RISC-V model, coupled with its permissive BSD licence, makes it ideal for a wide variety of processors, including low-cost microcontrollers that can be manufactured without incurring licence costs,” Amazon’s ...

Imagination, Andes Partner on Wireless RISC-V Microcontroller Product

by Gareth Halfacree on FOSSi – AB Open
Imagination Technologies and Andes Technology have announced a partnership to combine the former’s Ensigma wireless intellectual property (IP) with the latter’s RISC-V N22 microcontroller IP in order to create an off-the-shelf product aimed at the Internet of Things (IoT) sector. The collaboration between the two companies marks the first time Imagination has shown interest in the RISC-V market; previously, the company’s general purpose processing products had centred around the proprietary ...

Become a GSoC student 2019!

by FOSSi Foundation on FOSSi Foundation - News & Posts
We are happy and honored to be part of the Google Summer of Code (GSoC) again this year. We are a mentoring organization and serve as an umbrella organization for many projects related to open source silicon design, open source EDA tools and the related ecosystem. Google Summer of Code is an excellent program for students to get a stipend by Google to work on open source projects. To start things off, we have prepared a list of project ideas. As a student you are free to base your project ...

GreenWaves’ €7m Series A Round Shows Hunger for RISC-V, FOSSi

by Gareth Halfacree on FOSSi – AB Open
GreenWaves Technologies, which launched the GAP8 RISC-V low-power processor and GAPuino development board in February last year, has announced that it has raised €7 million in Series A funding – a clear demonstration of the startling growth in the free and open source silicon (FOSSi) market. “This support from a distinguished group of corporate investors demonstrates the GAP processor family’s unique value proposition within this emerging market,” claims Loic Lietar, GreenWaves co-founder ...

Announcing Latch-Up in Portland, Oregon

by FOSSi Foundation on FOSSi Foundation - News & Posts
teaser image The FOSSi Foundation is proud to announce Latch-Up (latchup.io), a conference dedicated to free and open source silicon to be held over the weekend of May 4th and 5th in Portland, Oregon, USA. Latch-Up opens a new chapter for the FOSSi Foundation, with it being the first event in the spirit of ORConf held in North America. Latch-Up is a community-focused conference for open source semiconductor, digital design and embedded systems professionals and enthusiasts. Expect presentations on a ...

Reolink Argus Pro and Argus 2 Security Camera Installation and Review

by kevinhub88 on Black Mesa Labs
teaser image 2019.02.22 This blog is a quick setup guide and evaluation of the Reolink Argus family of solar powered motion activity security cameras.  I purchased both the Argus Pro and the Argus 2 which vary primarily only in the low light image sensor used. Installation manual was downloaded from here.  Goal of this blog is to provide a simple setup guide and a camera evaluation for use in an external security scenario for capturing both pedestrians on a sidewalk and car license plates entering a ...

CRU: Open ISA Events, New RISC-V & LoRaWAN Parts, IoT Regulation, and More

by Gareth Halfacree on FOSSi – AB Open
AB Open’s Andrew Back has published a piece on building a personal computer based on the RISC-V instruction set architecture (ISA), using a custom-designed housing containing a SiFive HiFive Unleashed development board and Microsemi Expansion Board. “While it’s clear that the most significant opportunities for RISC-V will be in democratising custom silicon for accelerating specific tasks and enabling new applications — and it’s already driving a renaissance in novel computer architectures, ...

DVCon 2019 to Host Panel Discussion on Open ISAs’ Impact on Verification and Compliance

by Gareth Halfacree on FOSSi – AB Open
The Design and Verification Conference (DVCon) 2019 is to host a panel on the verification and compliance implications of open instruction set architectures (ISAs) like RISC-V, organised by industry expert Imperas. Dubbed “Verification and Compliance in the Era of Open ISA – Is the Industry Ready to Address the Coming Tsunami of Innovation,” the panel is to be organised by Imperas’ Larry Lapides, moderated by Tirias Research’s Kevin Krewell, and feature Andes Technology’s Emerson Hsiao, ...

The RISC-V Revolution is Going Global This Month, you can join SiFive in Austin, Mountain View, or Boston

by Swamy Irrinki on SiFive
In 2018, we hosted several RISC-V technology symposia in India, China and Israel. These events were very successful in fueling the growing momentum surrounding the RISC-V ISA in these countries. It turns out that these events were just the tip of the iceberg. In 2019, SiFive is greatly expanding its reach by hosting over 50 SiFive Tech Symposia in cities throughout the world. The first leg of the global tour begins in the USA. In collaboration with our co-hosts and partner companies, we aim ...

RISC-V Workshop Zurich Call for Speakers Now Open

by Gareth Halfacree on FOSSi – AB Open
The RISC-V Foundation has issued a call for speakers ahead of the RISC-V Workshop Zurich, scheduled for mid-June 2019, with a submission deadline of the 28th of February. Hosted by the non-profit RISC-V Foundation in partnership with Informa’s Knowledge & Networking Division, KNect365, the RISC-V Workshop Zurich is to be held at ETH Zürich on the 11th to 13th of June 2019 as one of several events around the globe dedicated to the promotion of the free and open source instruction set ...

WCH Adds Upcoming RISC-V Bluetooth LE Microcontroller to CH57x Family

by Gareth Halfacree on FOSSi – AB Open
Embedded news site CNXSoft has highlighted an upcoming part from Jiangsu Qinheng Co., Ltd, also known as WinChipHead (WCH), which combines a RISC-V core running at 60MHz with Bluetooth Low Energy (BLE) connectivity. Recently added to WCH’s parts list, the 32-bit microcontroller has been dubbed the CH572 – putting it into the same CH57x family as the company’s Arm Cortex-M0 microcontroller offerings – and is claimed to run at 60MHz. Full details haven’t yet been supplied by the company, but ...

Seeed Studio Stocks Sub-$18 RISC-V Sipeed Tang Primer FPGA Board

by Gareth Halfacree on FOSSi – AB Open
Internet of Things (IoT)-focused components provider Seeed Studio has begun stocking the Sipeed Tang Primer FPGA development board, a sub-$18 part which features an Anlogic EG4S20 FPGA running a RISC-V soft core. Designed to offer a full RISC-V implementation in a very small form factor, the Tang is based around the Anlogic EG4S20 field-programmable gate array (FPGA) with 20,000 logic units, around 130KB of SRAM, and 64Mb of SDRAM on a 32-bit bus. The board also includes 8Mb user-accessible ...

OTA: MarconISSta Deinstalled, LimeSDR 35km Barefoot Transmission, RPi CNI, and More

by Gareth Halfacree on MyriadRF
teaser image The MarconISSta mission, which saw a LimeSDR and Raspberry Pi installed on the International Space Station (ISS), has successfully completed its first phase and has been safely deinstalled and stowed. “MarconISSta was deinstalled on Saturday, February 9th 2019, by NASA astronaut Anne McClain,” writes project lead Martin Buscher in what is the last live mission update from phase one. “The system is stowed in a safe location and waits for MarconISSta phase II, which we currently plan for not ...

Hailey Lynne McKeefry on the Procurement Benefits of Open Source Hardware

by Gareth Halfacree on FOSSi – AB Open
EBN editor-in-chief Hailey Lynne McKeefry has penned a piece pointing to the considerable benefits of open hardware, and in particular the RISC-V instruction set architecture (ISA), to the procurement process. “It’s clear that open source hardware will have a ripple effect, not just on design, but also on procurement practices,” Hailey writes, citing industry experts including RISC-V Foundation executive director Rick O’Connor and Wave Computing’s Art Swift. “With so many organisations ...

“Arm’s Days Could Be Numbered,” Claims RISC-V Vendor

by Gareth Halfacree on FOSSi – AB Open
EE Times correspondent Nitin Dahad has pointed to growing troubles for embedded processing giant Arm, and the source should be of no surprise: the growing tide of free and open source silicon (FOSSi) designs, including RISC-V. That the ability to literally clone a GitHub repository and have a fully-working processor design ready to use or modify with no royalties or restrictive licensing is causing something of a revolution in the semiconductor industry is no secret – RISC-V pioneer ...

El Correo Libre Issue 12

by Gareth Halfacree on LibreCores - Medium
teaser image FOSSi Foundation Applies to Join Google Summer of Code 2019 The Free and Open Source Silicon Foundation has announced its application for a mentorship position in the Google Summer of Code (GSoC) programme, as part of its efforts towards expanding and improving the ecosystem. “In the Google Summer of Code, Google grants students a scholarship to contribute to open source projects over the summer,” explains Foundation director Stefan Wallentowitz. “The FOSSi Foundation applies as an umbrella ...

Building a RISC-V PC

by Andrew Back on FOSSi – AB Open
teaser image How we assembled a RISC-V desktop computer. (video at the bottom of this post.) While it’s clear that the most significant opportunities for RISC-V will be in democratising custom silicon for accelerating specific tasks and enabling new applications — and it’s already driving a renaissance in novel computer architectures, for e.g. IoT and edge processing — one question that people cannot help but ask is, so when can I have a RISC-V PC? The answer to which is, right now. The SiFive HiFive ...

CRU: Wuthering Bytes 2019 Planning, SweRV RISC-V Released, and More

by Gareth Halfacree on FOSSi – AB Open
AB Open is pleased to announce a call for participation (CFP) in Wuthering Bytes, the annual community technology festival it produces, seeking those interested in hosting a talk, workshop, roundtable, or other event between Friday the 30th of August and Sunday the 8th of September. Wuthering Bytes — produced by AB Open as part of its contribution to the community — has grown considerably from the first event, held at Hebden Bridge Town Hall, in 2013: Wuthering Bytes 2017 saw attendees ...

RISC-V Growth Showcased by Bumper Embedded World 2019 Showing

by Gareth Halfacree on FOSSi – AB Open
The free and open-source silicon (FOSSi) ecosystem continues to grow, and nowhere will that growth be more obvious than at the Embedded World 2019 conference this year where 17 companies will be exhibiting RISC-V implementations and supporting technologies alone. Due to take place at the NürnbergMesse, Germany, from Tuesday the 26th of February to Thursday the 28th of February, Embedded World 2019 is to play host to a booth from the RISC-V Foundation which will include pods from members ...

OTA: PiTop SDR Upgrade, Osmocom, srsLTE Updates, and More

by Gareth Halfacree on Myriad
A video demonstrating the integration of a LimeSDR Mini with the modular, Raspberry Pi-based PiTop laptop has been released – and all it took was a few laser-cut parts. “The PiTop is a rather cool modular laptop that you build yourself and which is based around the Raspberry Pi platform. Eminently hackable, we thought it would be fun to see if we could integrate a LimeSDR Mini for software-defined radio development on the move,” explains Andrew Back in the latest video update to the LimeSDR ...

RISC-V Foundation Announces OpenSBI 0.1 Release

by Gareth Halfacree on FOSSi – AB Open
An initial implementation of an open supervisor binary interface (SBI) for RISC-V, imaginatively dubbed OpenSBI v0.1, has been released with support for the HiFive Unleashed, Kendryte K210-based development boards, and QEMU virtual machines. “OpenSBI is an open source implementation of the RISC-V Supervisor Binary Interface (SBI). SBI serves a critical purpose, enabling an operating system to interact with the supervisor execution environment (SEE),” explains the RISC-V Foundation of the ...

OTA: PiTop SDR Upgrade, Osmocom, srsLTE Updates, and More

by Gareth Halfacree on MyriadRF
A video demonstrating the integration of a LimeSDR Mini with the modular, Raspberry Pi-based PiTop laptop has been released – and all it took was a few laser-cut parts. “The PiTop is a rather cool modular laptop that you build yourself and which is based around the Raspberry Pi platform. Eminently hackable, we thought it would be fun to see if we could integrate a LimeSDR Mini for software-defined radio development on the move,” explains Andrew Back in the latest video update to the LimeSDR ...

Verilator - Verilator 4.010 Released

by Wilson Snyder on Veripool: News
Verilator 4.010 2019-01-27 Removed --trace-lxt2, use --trace-fst instead. For --xml, add additional information, bug1372. [Jonathan Kimmitt] Add circular typedef error, bug1388. [Al Grant] Add unsupported for loops error, msg2692. [Yu Sheng Lin] Fix FST tracing of wide arrays, bug1376. [Aleksander Osman] Fix error when pattern assignment has too few elements, bug1378. [Viktor Tomov] Fix error when no modules in $unit, bug1381. [Al Grant] Fix missing too ...

Western Digital Releases SweRV RISC-V Core Source Code

by Gareth Halfacree on FOSSi – AB Open
Storage giant Western Digital has officially released the source code for its SweRV RISC-V core, under the permissive Apache 2.0 Licence, allowing anyone to run, experiment with, or modify its implementation. Announced back in December, SweRV is a RISC-V core implementation developed in-house as part of Western Digital’s aim to transition its storage processing products away from proprietary cores and onto the free and open instruction set architecture (ISA). “Our SweRV Core and the new ...

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Last updated 24 April 2019 08:00 UTC