LibreCores Project List

optimsoc/optimsoc

OpTiMSoC is a framework to build a custom tiled Multi-Core SoC
by optimsoc (added on 2016-10-08)
Major language: Verilog-SystemVerilog Updated 2 months ago

imphil/pulpino

by imphil (added on 2016-10-08)
Major language: C/C++ Header Updated 5 months ago

rherveille/ahb3lite-interconnect

Fully parameterised AHB3-Multilayer Interconnect switch for AHB3-Lite based SoCs.
by rherveille (added on 2016-10-10)
Major language: Verilog-SystemVerilog Updated 2 years ago

imphil/glip

Simple FIFO-based, transport-agnostic device - host communication
by imphil (added on 2016-10-10)
Major language: Verilog-SystemVerilog Updated 5 months ago

eliaskousk/parallella-riscv

RISC-V port to Parallella Board
by eliaskousk (added on 2016-10-11)
Major language: Tcl/Tk Updated 2 years ago

olofk/FuseSoC

a package manager and a set of build tools for FPGA/ASIC development
by olofk (added on 2016-10-11)
Major language: Python Updated 5 months ago

sridhargunnam/mipsR3000

by sridhargunnam (added on 2016-10-11)
Major language: Verilog-SystemVerilog Updated 2 years ago

ZipCPU/zipcpu

The ZipCPU is a resource efficient 32-bit soft core implementation.
by ZipCPU (added on 2016-10-12)
Major language: Verilog-SystemVerilog Updated 1 year ago

ZipCPU/wbscope

A wishbone controlled scope for FPGAs
by ZipCPU (added on 2016-10-12)
Major language: Verilog-SystemVerilog Updated 1 year ago

ZipCPU/wbicapetwo

Wishbone to ICAPE interface bridge
by ZipCPU (added on 2016-10-12)
Major language: Verilog-SystemVerilog Updated 2 years ago

ZipCPU/wb2axip

A pipelined wishbone to AXI bridge
by ZipCPU (added on 2016-10-12)
Major language: Verilog-SystemVerilog Updated 2 years ago

ZipCPU/wbfmtx

A wishbone controlled FM transmitted hack
by ZipCPU (added on 2016-10-12)
Major language: TeX Updated 2 years ago

ZipCPU/wbpwmaudio

A wishbone controlled PWM (audio) controller
by ZipCPU (added on 2016-10-12)
Major language: TeX Updated 2 years ago

ZipCPU/dblclockfft

A C++ generator of Verilog FFT cores that produce and consume two samples per clock
by ZipCPU (added on 2016-10-12)
Major language: C++ Updated 2 years ago

ZipCPU/rtcclock

A Real Time Clock core for FPGA's
by ZipCPU (added on 2016-10-12)
Major language: Verilog-SystemVerilog Updated 2 years ago

ZipCPU/sdspi

SD-Card controller, using a SPI interface that is (optionally) shared
by ZipCPU (added on 2016-10-12)
Major language: make Updated 2 years ago

ZipCPU/s6soc

CMod-S6 SoC
by ZipCPU (added on 2016-10-12)
Major language: Verilog-SystemVerilog Updated 2 years ago

ZipCPU/wbuart32

A simple UART controller that can easily be wishbone controlled.
by ZipCPU (added on 2016-10-12)
Major language: Verilog-SystemVerilog Updated 1 year ago

ZipCPU/xulalx25soc

A System on a Chip Implementation for the XuLA2-LX25 board
by ZipCPU (added on 2016-10-12)
Major language: Verilog-SystemVerilog Updated 1 year ago

ZipCPU/openarty

An Open Source configuration of the Arty platform
by ZipCPU (added on 2016-10-12)
Major language: Verilog-SystemVerilog Updated 1 year ago

taichi-ishitani/rggen

Code generation tool for control/status registers in a SoC design
by taichi-ishitani (added on 2016-10-14)
Major language: Ruby Updated 19 days ago

cliffordwolf/picorv32

PicoRV32 - A Size-Optimized RISC-V CPU
by cliffordwolf (added on 2016-10-14)
Major language: Assembly Updated 1 year ago

cliffordwolf/SimpleVOut

SimpleVOut -- A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
by cliffordwolf (added on 2016-10-14)
Major language: Verilog-SystemVerilog Updated 3 years ago

olivier-girard/openmsp430

by olivier-girard (added on 2016-10-15)
Major language: Verilog-SystemVerilog Updated 2 years ago

olivier-girard/opengfx430

by olivier-girard (added on 2016-10-15)
Major language: Verilog-SystemVerilog Updated 2 years ago

olofk/wb-streamer

Streaming DMA with Wishbone interface
by olofk (added on 2016-10-16)
Major language: Verilog-SystemVerilog Updated 2 years ago

olofk/fifo

Generic FIFO implementation with optional FWFT
by olofk (added on 2016-10-16)
Major language: Verilog-SystemVerilog Updated 9 months ago

olofk/stream-utils

Data stream utility functions
by olofk (added on 2016-10-16)
Major language: Verilog-SystemVerilog Updated 3 years ago

olofk/wb-intercon

Wishbone interconnect utilities
by olofk (added on 2016-10-16)
Major language: Verilog-SystemVerilog Updated 6 months ago

olofk/wb-bfm

Wishbone Bus Functional Model
by olofk (added on 2016-10-16)
Major language: Verilog-SystemVerilog Updated 2 years ago

olofk/or1k-bootloaders

OpenRISC 1000-compatible bootloaders
by olofk (added on 2016-10-16)
Major language: Assembly Updated 2 years ago

olofk/ipyxact

Python library for working with IP-XACT files
by olofk (added on 2016-10-16)
Major language: Python Updated 9 months ago

olofk/libaxis

Library of VHDL components for AXI Stream infrastructure
by olofk (added on 2016-10-16)
Major language: VHDL Updated 7 months ago

olofk/libstorage

Library of VHDL components for data storage
by olofk (added on 2016-10-16)
Major language: VHDL Updated 3 years ago

fkuau/scct

Simple Capture/Compare Timer
by fkuau (added on 2016-10-19)
Major language: Verilog-SystemVerilog Updated 2 years ago

Paebbels/PicoBlaze-Library

The PicoBlaze-Library offers several PicoBlaze devices and routines to extend a common PicoBlaze environment to a little System on Chip.
by Paebbels (added on 2016-10-24)
Major language: VHDL Updated 3 years ago

Paebbels/JSON-for-VHDL

A JSON library implemented in VHDL
by Paebbels (added on 2016-10-24)
Major language: JSON Updated 2 years ago

Paebbels/PicoBlaze-Examples

This repository contains synthesizable examples which use the PoC-Library.
by Paebbels (added on 2016-10-24)
Major language: VHDL Updated 2 years ago

Paebbels/Pile-of-Cores

IP Core Library - Published and maintained by the VLSI-EDA, Faculty of Computer Science, Technische Universität Dresden, Germany.
by Paebbels (added on 2016-10-24)
Major language: VHDL Updated 2 years ago

krevanth/ZAP-ARM-Processor

ZAP is an ARMv4T processor with cache and MMU support.
by krevanth (added on 2016-11-04)

epekkar/kactus2

Kactus2 is a graphical EDA tool based on the IP-XACT standard.
by epekkar (added on 2016-12-20)
Major language: C++ Updated 5 months ago

openrisc/mor1kx

The new reference OpenRISC 1000 implementation
by openrisc (added on 2017-02-06)
Major language: Verilog-SystemVerilog Updated 5 months ago

arkenidar/resm-aka-bbjj

Computer/CPU design.Based on Turing Machine/BitBitJump machine.Extended,popularized,applied.Files,ideas,docs,programs,circuits,links.
by arkenidar (added on 2017-02-09)
Major language: HTML Updated 1 year ago

zerogravity/neo430

very small, msp430-compatible custom soft-core microcontroller-like processor system
by zerogravity (added on 2017-02-14)
Major language: VHDL Updated 1 year ago

TNSFloat/Ternary-FFT

by TNSFloat (added on 2017-03-27)
Major language: Markdown Updated 2 years ago

enjoy-digital/liteeth

Small footprint and configurable Ethernet core
by enjoy-digital (added on 2017-05-14)
Major language: Python Updated 1 year ago

enjoy-digital/litesata

Small footprint and configurable SATA core
by enjoy-digital (added on 2017-05-14)
Major language: Python Updated 1 year ago

enjoy-digital/litedram

Small footprint and configurable DRAM core
by enjoy-digital (added on 2017-05-14)
Major language: Python Updated 1 year ago

enjoy-digital/litepcie

Small footprint and configurable PCIe core
by enjoy-digital (added on 2017-05-14)
Major language: Verilog-SystemVerilog Updated 1 year ago

enjoy-digital/litejesd204b

Small footprint and configurable JESD204B core
by enjoy-digital (added on 2017-05-14)
Major language: Python Updated 1 year ago

enjoy-digital/litescope

Small footprint and configurable embedded FPGA logic analyzer
by enjoy-digital (added on 2017-05-14)
Major language: Python Updated 1 year ago

fossi-foundation/wishbone

The Wishbone SoC Interconnect Architecture
by fossi-foundation (added on 2017-05-22)
Major language: Markdown Updated 1 month ago

AndreaCorallo/kpu-soc

A minimal system on chip
by AndreaCorallo (added on 2017-06-02)
Major language: Assembly Updated 1 year ago

zguig52/euryspace

Space Communication System based on CCSDS recommandations
by zguig52 (added on 2017-06-16)
Major language: VHDL Updated 1 year ago

sid24/addsub

by sid24 (added on 2017-07-28)
Major language: Verilog-SystemVerilog Updated 1 year ago

timvideos/hdmi2usb

A version of the HDMI2USB firmware based around LiteX tools produced by @Enjoy-Digital (based on misoc+migen created by @M-Labs)
by timvideos (added on 2017-08-27)
Major language: C/C++ Header Updated 16 days ago

hatimak/edsac-fpga-museum

GSoC 2017: Museum on FPGA - EDSAC
by hatimak (added on 2017-09-09)
Major language: Verilog-SystemVerilog Updated 1 year ago

RoaLogic/rv12

The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market.
by RoaLogic (added on 2017-09-11)
Major language: Verilog-SystemVerilog Updated 1 year ago

jbush/nyuziprocessor

GPGPU processor architecture
by jbush (added on 2017-09-23)
Major language: C Updated 6 days ago

codelec/riscv-sodor

educational microarchitectures for risc-v isa
by codelec (added on 2017-09-23)
Major language: Scala Updated 4 months ago

jbush/waveview

Digital Waveform Viewer
by jbush (added on 2017-09-24)
Major language: Java Updated 29 days ago

www-asics-ws/usb-11-device-ip-core

USB 1.1 Device IP Core
by www-asics-ws (added on 2017-10-01)
Major language: Verilog-SystemVerilog Updated 1 year ago

www-asics-ws/usb-20-device-ip-core

USB 2.0 Device IP Core
by www-asics-ws (added on 2017-10-01)
Major language: Verilog-SystemVerilog Updated 1 year ago

www-asics-ws/aes-rijndael-ip-core

AES (Rijndael) IP Core (128 bit version)
by www-asics-ws (added on 2017-10-01)
Major language: Verilog-SystemVerilog Updated 1 year ago

www-asics-ws/wishbone-interconnect-ip-core

WISHBONE Interconnect
by www-asics-ws (added on 2017-10-01)
Major language: Verilog-SystemVerilog Updated 1 year ago

tudor-timi/systemverilog-reflection-api

Reflection API for SystemVerilog
by tudor-timi (added on 2017-10-15)
Major language: Verilog-SystemVerilog Updated 1 year ago

tudor-timi/rgen

IP-XACT based register generator
by tudor-timi (added on 2017-10-15)
Major language: Mako Updated 9 months ago

hatimak/sigma

General implementation of Unscented Kalman Filter on FPGA (part of author's Bachelors Thesis work)
by hatimak (added on 2017-10-24)
Major language: Verilog-SystemVerilog Updated 5 months ago

shrikuljoshi/axi4-configurable-master

AXI4 compliant modules designed with Verilog
by shrikuljoshi (added on 2017-11-13)
Major language: Markdown Updated 1 year ago

VHDL/corelib

by VHDL (added on 2017-11-16)
Major language: Markdown Updated 2 years ago

JoachimS/sha256

by JoachimS (added on 2018-01-03)
Major language: Verilog-SystemVerilog Updated 1 year ago

JoachimS/aes-128256

by JoachimS (added on 2018-01-03)
Major language: Verilog-SystemVerilog Updated 1 year ago

JoachimS/chacha

by JoachimS (added on 2018-01-03)
Major language: Verilog-SystemVerilog Updated 2 years ago

JoachimS/siphash

by JoachimS (added on 2018-01-03)
Major language: Verilog-SystemVerilog Updated 3 years ago

JoachimS/cmac-aes

by JoachimS (added on 2018-01-03)
Major language: Verilog-SystemVerilog Updated 2 years ago

JoachimS/sha512

by JoachimS (added on 2018-01-03)
Major language: Verilog-SystemVerilog Updated 2 years ago

JoachimS/sha1-hash

by JoachimS (added on 2018-01-03)
Major language: Verilog-SystemVerilog Updated 1 year ago

JoachimS/rc4-cipher

by JoachimS (added on 2018-01-03)
Major language: Verilog-SystemVerilog Updated 2 years ago

hutch31/sdlib

srdy-drdy library
by hutch31 (added on 2018-01-08)
Major language: Verilog-SystemVerilog Updated 1 year ago

hutch31/tv80

Shadow of OpenCores TV80 microprocessor
by hutch31 (added on 2018-01-08)
Major language: Verilog-SystemVerilog Updated 3 months ago

taichi-ishitani/noc-sv

Network on Chip
by taichi-ishitani (added on 2018-01-18)
Major language: Verilog-SystemVerilog Updated 2 months ago

taichi-ishitani/tue-uvm

Useful UVM extensions
by taichi-ishitani (added on 2018-01-18)
Major language: Verilog-SystemVerilog Updated 7 months ago

QNN7CS/reusehub

by QNN7CS (added on 2018-02-11)

mayurwaghela996/proj1

FOSSASIA Summit 2018 https://2018.fossasia.org
by mayurwaghela996 (added on 2018-02-13)
Major language: LESS Updated 1 year ago

tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
by tymonx (added on 2018-02-16)
Major language: Verilog-SystemVerilog Updated 5 months ago

sandipbhuyan/myblog

by sandipbhuyan (added on 2018-02-27)
Major language: PHP Updated 2 months ago

sandipbhuyan/loginpage

by sandipbhuyan (added on 2018-02-27)
Major language: PHP Updated 3 years ago

zarubaf/ariane

by zarubaf (added on 2018-02-28)
Major language: Sass Updated 5 months ago

daveshah1/mipi-csi-2-receiver

Open Source 4k CSI-2 Rx core for Xilinx FPGAs
by daveshah1 (added on 2018-03-03)
Major language: Verilog-SystemVerilog Updated 5 months ago

stevehoover/warp-v

WARP-V is an extremely flexible RISC-V CPU core.
by stevehoover (added on 2018-04-21)
Major language: Markdown Updated 6 months ago

alessandrocomodi/fpga-webserver

Connection between Web Application and Cloud FPGA accelerator devices
by alessandrocomodi (added on 2018-04-26)
Major language: Verilog-SystemVerilog Updated 16 days ago

christian-krieg/blake2

VHDL implementation of BLAKE2 cryptographic hash and message authentication code (MAC)
by christian-krieg (added on 2018-06-11)
Major language: VHDL Updated 10 months ago

drossi/pulp-open

A multi-core system based on clusters of 32-bit RISC-V cores with direct access to a small and fast scratchpad memory.
by drossi (added on 2018-09-22)
Major language: Verilog-SystemVerilog Updated 10 months ago

drossi/pulpissimo

by drossi (added on 2018-09-22)
Major language: Tcl/Tk Updated 8 months ago

drossi/ariane

by drossi (added on 2018-09-22)
Major language: Verilog-SystemVerilog Updated 6 months ago

drossi/bigpulp

by drossi (added on 2018-09-22)
Major language: Verilog-SystemVerilog Updated 9 months ago

drossi/ri5cy

by drossi (added on 2018-09-23)
Major language: Verilog-SystemVerilog Updated 9 months ago

drossi/zero-riscy

by drossi (added on 2018-09-23)
Major language: Verilog-SystemVerilog Updated 6 months ago

accelize/apyfal

Python Cloud Object Storage I/O
by accelize (added on 2018-10-26)
Major language: Python Updated 29 days ago

accelize/drmlib

by accelize (added on 2018-10-26)
Major language: C/C++ Header Updated 6 months ago

taichi-ishitani/tvip-axi

AMBA AXI VIP
by taichi-ishitani (added on 2018-10-26)
Major language: Verilog-SystemVerilog Updated 2 months ago

Nancy-Chauhan/johns-fifo

Susper Decentralised Search Engine https://susper.com
by Nancy-Chauhan (added on 2018-10-27)
Major language: TypeScript Updated 7 months ago

mballance/fwrisc

Featherweight RISC-V implementation
by mballance (added on 2018-11-27)
Major language: Assembly Updated 2 days ago

jbalkind/openpiton

The OpenPiton Platform
by jbalkind (added on 2018-11-29)
Updated 14 days ago

tomtor/hdl-deflate

FPGA implementation of deflate (de)compress RFC 1950/1951
by tomtor (added on 2019-01-03)
Major language: Verilog-SystemVerilog Updated 1 month ago

olofk/serv

SERV - The SErial RISC-V CPU
by olofk (added on 2019-01-03)
Major language: Verilog-SystemVerilog Updated 11 days ago

catharanthus/lxp32-cpu

A lightweight, FPGA-friendly 32-bit CPU core
by catharanthus (added on 2019-01-11)
Major language: VHDL Updated 5 months ago

mballance/dvkit

by mballance (added on 2019-01-19)
Major language: make Updated 4 months ago

mballance/edapack

Provides a packaged collection of open source EDA tools
by mballance (added on 2019-01-20)
Major language: Python Updated 2 months ago

jakubcabal/uart-for-fpga

Simple UART controller for FPGA written in VHDL
by jakubcabal (added on 2019-01-27)
Major language: VHDL Updated 4 months ago

jakubcabal/spi-fpga

SPI master and slave for FPGA written in VHDL
by jakubcabal (added on 2019-01-27)
Major language: VHDL Updated 5 months ago

EoneSystems/synchronous-fifo

by EoneSystems (added on 2019-02-10)

adrianf0/hdlregs

A Python-based HDL register file generator
by adrianf0 (added on 2019-03-11)
Major language: Python Updated 3 months ago

mguthaus/openram

An open-source static random access memory (SRAM) compiler.
by mguthaus (added on 2019-05-04)
Major language: Python Updated 1 month ago

jcastillo4/systemc-verilog-md5

SystemC and Verilog version of MD5 hash core
by jcastillo4 (added on 2019-06-16)
Major language: C++ Updated 2 days ago