LibreCores Project List
optimsoc/optimsoc
OpTiMSoC is a framework to build a custom tiled Multi-Core SoC
by optimsoc (added on 2016-10-08)
imphil/pulpino
by imphil (added on 2016-10-08)
rherveille/ahb3lite-interconnect
Fully parameterised AHB3-Multilayer Interconnect switch for AHB3-Lite based SoCs.
by rherveille (added on 2016-10-10)
imphil/glip
Simple FIFO-based, transport-agnostic device - host communication
by imphil (added on 2016-10-10)
eliaskousk/parallella-riscv
RISC-V port to Parallella Board
by eliaskousk (added on 2016-10-11)
olofk/FuseSoC
a package manager and a set of build tools for FPGA/ASIC development
by olofk (added on 2016-10-11)
sridhargunnam/mipsR3000
by sridhargunnam (added on 2016-10-11)
ZipCPU/zipcpu
The ZipCPU is a resource efficient 32-bit soft core implementation.
by ZipCPU (added on 2016-10-12)
ZipCPU/wbscope
A wishbone controlled scope for FPGAs
by ZipCPU (added on 2016-10-12)
ZipCPU/wbicapetwo
Wishbone to ICAPE interface bridge
by ZipCPU (added on 2016-10-12)
ZipCPU/wb2axip
A pipelined wishbone to AXI bridge
by ZipCPU (added on 2016-10-12)
ZipCPU/wbfmtx
A wishbone controlled FM transmitted hack
by ZipCPU (added on 2016-10-12)
ZipCPU/wbpwmaudio
A wishbone controlled PWM (audio) controller
by ZipCPU (added on 2016-10-12)
ZipCPU/dblclockfft
A C++ generator of Verilog FFT cores that produce and consume two samples per clock
by ZipCPU (added on 2016-10-12)
ZipCPU/rtcclock
A Real Time Clock core for FPGA's
by ZipCPU (added on 2016-10-12)
ZipCPU/sdspi
SD-Card controller, using a SPI interface that is (optionally) shared
by ZipCPU (added on 2016-10-12)
ZipCPU/s6soc
CMod-S6 SoC
by ZipCPU (added on 2016-10-12)
ZipCPU/wbuart32
A simple UART controller that can easily be wishbone controlled.
by ZipCPU (added on 2016-10-12)
ZipCPU/xulalx25soc
A System on a Chip Implementation for the XuLA2-LX25 board
by ZipCPU (added on 2016-10-12)
ZipCPU/openarty
An Open Source configuration of the Arty platform
by ZipCPU (added on 2016-10-12)
taichi-ishitani/rggen
Code generation tool for control/status registers in a SoC design
by taichi-ishitani (added on 2016-10-14)
cliffordwolf/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
by cliffordwolf (added on 2016-10-14)
cliffordwolf/SimpleVOut
SimpleVOut -- A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
by cliffordwolf (added on 2016-10-14)
olivier-girard/openmsp430
by olivier-girard (added on 2016-10-15)
olivier-girard/opengfx430
by olivier-girard (added on 2016-10-15)
olofk/wb-streamer
Streaming DMA with Wishbone interface
by olofk (added on 2016-10-16)
olofk/fifo
Generic FIFO implementation with optional FWFT
by olofk (added on 2016-10-16)
olofk/stream-utils
Data stream utility functions
by olofk (added on 2016-10-16)
olofk/wb-intercon
Wishbone interconnect utilities
by olofk (added on 2016-10-16)
olofk/wb-bfm
Wishbone Bus Functional Model
by olofk (added on 2016-10-16)
olofk/or1k-bootloaders
OpenRISC 1000-compatible bootloaders
by olofk (added on 2016-10-16)
olofk/ipyxact
Python library for working with IP-XACT files
by olofk (added on 2016-10-16)
olofk/libaxis
Library of VHDL components for AXI Stream infrastructure
by olofk (added on 2016-10-16)
olofk/libstorage
Library of VHDL components for data storage
by olofk (added on 2016-10-16)
fkuau/scct
Simple Capture/Compare Timer
by fkuau (added on 2016-10-19)
Paebbels/PicoBlaze-Library
The PicoBlaze-Library offers several PicoBlaze devices and routines to extend a common PicoBlaze environment to a little System on Chip.
by Paebbels (added on 2016-10-24)
Paebbels/JSON-for-VHDL
A JSON library implemented in VHDL
by Paebbels (added on 2016-10-24)
Paebbels/PicoBlaze-Examples
This repository contains synthesizable examples which use the PoC-Library.
by Paebbels (added on 2016-10-24)
Paebbels/Pile-of-Cores
IP Core Library - Published and maintained by the VLSI-EDA, Faculty of Computer Science, Technische Universität Dresden, Germany.
by Paebbels (added on 2016-10-24)
krevanth/ZAP-ARM-Processor
ZAP is an ARMv4T processor with cache and MMU support.
by krevanth (added on 2016-11-04)
epekkar/kactus2
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
by epekkar (added on 2016-12-20)
openrisc/mor1kx
The new reference OpenRISC 1000 implementation
by openrisc (added on 2017-02-06)
arkenidar/resm-aka-bbjj
Computer/CPU design.Based on Turing Machine/BitBitJump machine.Extended,popularized,applied.Files,ideas,docs,programs,circuits,links.
by arkenidar (added on 2017-02-09)
zerogravity/neo430
very small, msp430-compatible custom soft-core microcontroller-like processor system
by zerogravity (added on 2017-02-14)
TNSFloat/Ternary-FFT
by TNSFloat (added on 2017-03-27)
enjoy-digital/liteeth
Small footprint and configurable Ethernet core
by enjoy-digital (added on 2017-05-14)
enjoy-digital/litesata
Small footprint and configurable SATA core
by enjoy-digital (added on 2017-05-14)
enjoy-digital/litedram
Small footprint and configurable DRAM core
by enjoy-digital (added on 2017-05-14)
enjoy-digital/litepcie
Small footprint and configurable PCIe core
by enjoy-digital (added on 2017-05-14)
enjoy-digital/litejesd204b
Small footprint and configurable JESD204B core
by enjoy-digital (added on 2017-05-14)
enjoy-digital/litescope
Small footprint and configurable embedded FPGA logic analyzer
by enjoy-digital (added on 2017-05-14)
fossi-foundation/wishbone
The Wishbone SoC Interconnect Architecture
by fossi-foundation (added on 2017-05-22)
AndreaCorallo/kpu-soc
A minimal system on chip
by AndreaCorallo (added on 2017-06-02)
zguig52/euryspace
Space Communication System based on CCSDS recommandations
by zguig52 (added on 2017-06-16)
timvideos/hdmi2usb
A version of the HDMI2USB firmware based around LiteX tools produced by @Enjoy-Digital (based on misoc+migen created by @M-Labs)
by timvideos (added on 2017-08-27)
hatimak/edsac-fpga-museum
GSoC 2017: Museum on FPGA - EDSAC
by hatimak (added on 2017-09-09)
RoaLogic/rv12
The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market.
by RoaLogic (added on 2017-09-11)
jbush/nyuziprocessor
GPGPU processor architecture
by jbush (added on 2017-09-23)
codelec/riscv-sodor
educational microarchitectures for risc-v isa
by codelec (added on 2017-09-23)
jbush/waveview
Digital Waveform Viewer
by jbush (added on 2017-09-24)
www-asics-ws/usb-11-device-ip-core
USB 1.1 Device IP Core
by www-asics-ws (added on 2017-10-01)
www-asics-ws/usb-20-device-ip-core
USB 2.0 Device IP Core
by www-asics-ws (added on 2017-10-01)
www-asics-ws/aes-rijndael-ip-core
AES (Rijndael) IP Core (128 bit version)
by www-asics-ws (added on 2017-10-01)
www-asics-ws/wishbone-interconnect-ip-core
WISHBONE Interconnect
by www-asics-ws (added on 2017-10-01)
tudor-timi/systemverilog-reflection-api
Reflection API for SystemVerilog
by tudor-timi (added on 2017-10-15)
tudor-timi/rgen
IP-XACT based register generator
by tudor-timi (added on 2017-10-15)
hatimak/sigma
General implementation of Unscented Kalman Filter on FPGA (part of author's Bachelors Thesis work)
by hatimak (added on 2017-10-24)
shrikuljoshi/axi4-configurable-master
AXI4 compliant modules designed with Verilog
by shrikuljoshi (added on 2017-11-13)
VHDL/corelib
by VHDL (added on 2017-11-16)
JoachimS/sha256
by JoachimS (added on 2018-01-03)
JoachimS/aes-128256
by JoachimS (added on 2018-01-03)
JoachimS/chacha
by JoachimS (added on 2018-01-03)
JoachimS/siphash
by JoachimS (added on 2018-01-03)
JoachimS/cmac-aes
by JoachimS (added on 2018-01-03)
JoachimS/sha512
by JoachimS (added on 2018-01-03)
JoachimS/sha1-hash
by JoachimS (added on 2018-01-03)
JoachimS/rc4-cipher
by JoachimS (added on 2018-01-03)
hutch31/sdlib
srdy-drdy library
by hutch31 (added on 2018-01-08)
hutch31/tv80
Shadow of OpenCores TV80 microprocessor
by hutch31 (added on 2018-01-08)
taichi-ishitani/noc-sv
Network on Chip
by taichi-ishitani (added on 2018-01-18)
taichi-ishitani/tue-uvm
Useful UVM extensions
by taichi-ishitani (added on 2018-01-18)
mayurwaghela996/proj1
FOSSASIA Summit 2018 https://2018.fossasia.org
by mayurwaghela996 (added on 2018-02-13)
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
by tymonx (added on 2018-02-16)
sandipbhuyan/loginpage
by sandipbhuyan (added on 2018-02-27)
zarubaf/ariane
by zarubaf (added on 2018-02-28)
daveshah1/mipi-csi-2-receiver
Open Source 4k CSI-2 Rx core for Xilinx FPGAs
by daveshah1 (added on 2018-03-03)
stevehoover/warp-v
WARP-V is an extremely flexible RISC-V CPU core.
by stevehoover (added on 2018-04-21)
alessandrocomodi/fpga-webserver
Connection between Web Application and Cloud FPGA accelerator devices
by alessandrocomodi (added on 2018-04-26)
christian-krieg/blake2
VHDL implementation of BLAKE2 cryptographic hash and message authentication code (MAC)
by christian-krieg (added on 2018-06-11)
drossi/pulp-open
A multi-core system based on clusters of 32-bit RISC-V cores with direct access to a small and fast scratchpad memory.
by drossi (added on 2018-09-22)
drossi/pulpissimo
by drossi (added on 2018-09-22)
drossi/ariane
by drossi (added on 2018-09-22)
drossi/bigpulp
by drossi (added on 2018-09-22)
drossi/ri5cy
by drossi (added on 2018-09-23)
accelize/apyfal
Python Cloud Object Storage I/O
by accelize (added on 2018-10-26)
accelize/drmlib
by accelize (added on 2018-10-26)
taichi-ishitani/tvip-axi
AMBA AXI VIP
by taichi-ishitani (added on 2018-10-26)
Nancy-Chauhan/johns-fifo
Susper Decentralised Search Engine https://susper.com
by Nancy-Chauhan (added on 2018-10-27)
mballance/fwrisc
Featherweight RISC-V implementation
by mballance (added on 2018-11-27)
jbalkind/openpiton
The OpenPiton Platform
by jbalkind (added on 2018-11-29)
tomtor/hdl-deflate
FPGA implementation of deflate (de)compress RFC 1950/1951
by tomtor (added on 2019-01-03)
olofk/serv
SERV - The SErial RISC-V CPU
by olofk (added on 2019-01-03)
catharanthus/lxp32-cpu
A lightweight, FPGA-friendly 32-bit CPU core
by catharanthus (added on 2019-01-11)
mballance/dvkit
by mballance (added on 2019-01-19)
mballance/edapack
Provides a packaged collection of open source EDA tools
by mballance (added on 2019-01-20)
jakubcabal/uart-for-fpga
Simple UART controller for FPGA written in VHDL
by jakubcabal (added on 2019-01-27)
jakubcabal/spi-fpga
SPI master and slave for FPGA written in VHDL
by jakubcabal (added on 2019-01-27)
adrianf0/hdlregs
A Python-based HDL register file generator
by adrianf0 (added on 2019-03-11)
mguthaus/openram
An open-source static random access memory (SRAM) compiler.
by mguthaus (added on 2019-05-04)
jcastillo4/systemc-verilog-md5
SystemC and Verilog version of MD5 hash core
by jcastillo4 (added on 2019-06-16)
alexforencich/verilog-ethernet
Verilog Ethernet components for FPGA implementation
by alexforencich (added on 2019-07-11)
alexforencich/verilog-axis
Verilog AXI stream components for FPGA implementation
by alexforencich (added on 2019-07-11)
alexforencich/verilog-uart
Verilog UART
by alexforencich (added on 2019-07-11)
alexforencich/verilog-i2c
Verilog I2C interface for FPGA implementation
by alexforencich (added on 2019-07-11)
alexforencich/verilog-lfsr
Fully parametrizable combinatorial parallel LFSR/CRC module
by alexforencich (added on 2019-07-11)
alexforencich/verilog-axi
Verilog AXI components for FPGA implementation
by alexforencich (added on 2019-07-11)
alexforencich/verilog-wishbone
Verilog wishbone components
by alexforencich (added on 2019-07-11)
alexforencich/verilog-pcie
Verilog PCI express components
by alexforencich (added on 2019-07-16)
lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
by lowRISC (added on 2019-08-18)
ozdnerdnc/spi-module
Software drivers for systems without OS
by ozdnerdnc (added on 2019-08-19)
alexforencich/corundum
Open source FPGA NIC
by alexforencich (added on 2019-09-05)