ahb3lite_interconnect by rherveille

Fully parameterised AHB3-Multilayer Interconnect switch for AHB3-Lite based SoCs.
We have not analyzed this project yet

ahb3lite_interconnect

Fully Parameterised AHB3-Lite SoC Interconnect

This project contains a fully parameterised AHB3-Multi-layer Interconnect switch for AHB3-Lite based SoCs.

License

The RTL is released under a non-commercial license, the testbench is released under GNU-GPL3.

For commercial applications/purposes, please contact us to reach an agreement with us based on our commercial license terms.

Dependencies

This release requires the ahb3lite package found here https://github.com/RoaLogic/ahb3lite_pkg

Project Meta

  • Registered 2 years ago
  • Started 1 year ago
  • Last commit 1 year ago

Commits

{"labels":[2017,2018],"series":[["9",null]]}

Commits per year

Contributors

{"labels":[2017,2018],"series":[["1",null]]}

Unique contributors per year

Releases

Data not available

Languages

{"labels":["Others","Verilog-SystemVerilog"],"series":[2,21]}

Share of languages used

Data Sheet
https://github.com/RoaLogic/ahb3lite_interconnect.git
Last updated 1 year ago
Language: Verilog-SystemVerilog
2 watchers
9 commits by 1 contributor
rherveille

Activity in last 1 year

Updated 1 year ago