rggen by taichi-ishitani
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
RgGen has following features:
- Generate source files related to CSR from register map specifications
- Register map specifications can be written in human readable format
- Costomize RgGen for you environment
- E.g. add special bit field types
RgGen is written in the Ruby programing language and its required version is 2.5 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see this page.
RgGen depends on following sub components and other Ruby libraries.
To install RgGen and the dependencies, use the command below:
$ gem install rggen
RgGen and dependencies will be installed on your system root.
If you want to install them on other location, you need to specify install path and set the
GEM_PATH environment variable:
$ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen $ export GEM_PATH=YOUR_INSTALL_DIRECTORY
You would get the following error message duaring installation if you have the old RgGen (version < 0.9).
ERROR: Error installing rggen: "rggen" from rggen-core conflicts with installed executable from rggen
To resolve the above error, there are three solutions. See this page
See Wiki documents.
plugin feature to allow your cusomization.
See this Wiki document for futher detals.
Following EDA tools can accept the generated source files.
- Simulation tools
- Synopsys VCS
- Cadence Xcelium
- Xilinx Vivado Simulator
- Confirmed RTL only
- Not sure if UVM register models are accepted
- Icarus Verilog
- Verilog RTL only
- Synthesis tools
- Synopsys Design Compiler
- Intel Quartus
- Xilinx Vivado
You can get example configuration file and register map specification listed below:
- Configuration file
- Register map specifications
By using these example files, you can try to use RgGen. Hit command below:
$ rggen -c config.yml -o out block_0.yml block_1.yml
-c: Specify path to your configuration file
-o: Specify path to the directory where generated files will be written to
Then, generated files listed below will be written to
- SystemVerilog RTL
- UVM register model
- Markdown document
See Contributing Guide.
Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
Copyright & License
Code of Conduct
Everyone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the code of conduct.
The MIT License (MIT) Copyright (c) 2019-2021 Taichi Ishitani Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.