RgGen

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.

RgGen has following features:

• Generate source files related to CSR from register map specifications
  • SystemVerilog RTL
  • Verilog RTL
    • Need rggen-verilog plugin
  • UVM register model (UVM RAL)
  • Register map documents written in Markdown
• Register map specifications can be written in human readable format
  • Ruby with APIs to describe register map information
  • YAML
  • JSON
  • TOML
  • Spreadsheet (XLSX, XLS, OSD, CSV)
  • SiFive DUH
    • Need rggen-duh plugin
• Costomize RgGen for you environment
  • E.g. add special bit field types

Installation

Ruby

RgGen is written in the Ruby programing language and its required version is 2.5 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see this page.

Installatin Command

RgGen depends on following sub components and other Ruby libraries.

• rggen-core
• rggen-default-register-map
• rggen-systemverilog
• rggen-markdown
• rggen-spreadsheet-loader

To install RgGen and the dependencies, use the command below:

$ gem install rggen

RgGen and dependencies will be installed on your system root.

If you want to install them on other location, you need to specify install path and set the GEM_PATH environment variable:

$ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen
$ export GEM_PATH=YOUR_INSTALL_DIRECTORY

You would get the following error message duaring installation if you have the old RgGen (version < 0.9).

ERROR:  Error installing rggen:
        "rggen" from rggen-core conflicts with installed executable from rggen

To resolve the above error, there are three solutions. See this page

Usage

See Wiki documents.

Plugin

RgGen has plugin feature to allow your cusomization. See this Wiki document for futher detals.

Supported Tools

Following EDA tools can accept the generated source files.

• Simulation tools
  • Synopsys VCS
  • Cadence Xcelium
  • Xilinx Vivado Simulator
    • Confirmed RTL only
    • Not sure if UVM register models are accepted
  • Verilator
    • Need -Wno-fatal switch
• Synthesis tools
  • Synopsys Design Compiler
  • Intel Quartus
  • Xilinx Vivado

Example

You can get example configuration file and register map specification listed below:

• Configuration file
  • https://github.com/rggen/rggen-sample/blob/master/config.yml
• Register map specifications
  • https://github.com/rggen/rggen-sample/blob/master/block_0.yml
  • https://github.com/rggen/rggen-sample/blob/master/block_1.yml

By using these example files, you can try to use RgGen. Hit command below:

$ rggen -c config.yml -o out block_0.yml block_1.yml

• -c: Specify path to your configuration file
• -o: Specify path to the directory where generated files will be written to

Then, generated files listed below will be written to out directory.

• SystemVerilog RTL
  • https://github.com/rggen/rggen-sample/blob/master/block_0.sv
  • https://github.com/rggen/rggen-sample/blob/master/block_1.sv
• UVM register model
  • https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
  • https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
• Markdown document
  • https://github.com/rggen/rggen-sample/blob/master/block_0.md
  • https://github.com/rggen/rggen-sample/blob/master/block_1.md

Contributing

See Contributing Guide.

Contact

Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:

• GitHub Issue Tracker
• GitHub Discussions
• Chat Room
• Mailing List
• Mail

See Also

• https://github.com/rggen/rggen-core
• https://github.com/rggen/rggen-default-register-map
• https://github.com/rggen/rggen-systemverilog
• https://github.com/rggen/rggen-markdown
• https://github.com/rggen/rggen-spreadsheet-loader
• https://github.com/rggen/rggen-duh
• https://github.com/rggen/rggen-verilog

Copyright & License

Copyright © 2019-2021 Taichi Ishitani. RgGen is licensed under the MIT License, see LICENSE for futher detils.

Code of Conduct

Everyone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the code of conduct.