usb1_device
USB 1.1 Device IP Core
Description
USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external micro-controller necessary. Derived from my USB 2.0 Function IP core, except all the high speed support logic has been ripped out and the interface was changed from shared memory to FIFO based.
A basic test bench is now included as well. It should be viewed as a starting point to write a more comprehensive and complete test bench.
I expect the users of this core to have some fundamental USB knowledge and be familiar with the UTMI specification and with the general USB transceivers (e.g. from philips). If you are not familiar with these two you should check out www.usb.org and read up on this subject ...
Features
- USB 1.1 Compliant Function
- Hardware enumeration support
- No micro controller/CPU required
- FIFO based interface
- Written In Verilog
- Fully Synthesisable
- Tested in Hardware
Copyright (C) 2000-2017, ASICs World Services, LTD. All rights reserved. Redistribution and use in source, netlist, binary and silicon forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of ASICS World Services, the Authors and/or the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
https://github.com/www-asics-ws/usb1_device.git
Issue Tracker
Last activity 3 years ago
Primary language: Verilog-SystemVerilog
3 commits by 2 contributors
activity over the last year
LibreCores data updated 4 months ago