usb2_dev

USB 2.0 Device IP Core

Description

This is a USB 2.0 compliant core. USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core. A industry standard PHY interface for USB has been developed. This interface is called USB Transceiver Macrocell Interface or UTMI for short. The host interface of the USB core is WISHBONE SoC compliant. More information about the USB standard and a full specification can be found at www.usb.org More information about the WISHBONE SoC and a full specification can be found on www.opencores.org. The UTMI specification (and various other useful USB papers) can be downloaded from here: https://www.intel.com/content/www/us/en/io/universal-serial-bus/universal-serial-bus-specifications.html

Copyright (C) 2000-2017, ASICs World Services, LTD.

All rights reserved.

Redistribution and use in source, netlist, binary and silicon forms, with
or without modification, are permitted provided that the following conditions
are met:

   * Redistributions of source code must retain the above copyright notice,
     this list of conditions and the following disclaimer.
     
   * Redistributions in binary form must reproduce the above copyright notice,
     this list of conditions and the following disclaimer in the documentation
     and/or other materials provided with the distribution.
     
   * Neither the name of ASICS World Services, the Authors and/or the names of
     its contributors may be used to endorse or promote products derived from
     this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
OF THE POSSIBILITY OF SUCH DAMAGE.

Project Meta

Registered on LibreCores 4 years ago
Project started 4 years ago
Last commit 4 years ago

Commits

{"labels":[2017,2018,2019,2020,2021,2022],"series":[[3,0,0,0,0,0]]}

Commits per year

Contributors

{"labels":[2017,2018,2019,2020,2021,2022],"series":[[2,0,0,0,0,0]]}

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{"labels":["Others","Verilog-SystemVerilog","Markdown"],"series":[0,16,1]}

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Data Sheet

Project Web Site
https://github.com/www-asics-ws/usb2_dev.git
Issue Tracker
Last activity 4 years ago
Primary language: Verilog-SystemVerilog
3 commits by 2 contributors

activity over the last year