wb_conmax
WISHBONE Interconnect
This is a WISHBONE Interconnect Matrix IP core.It can interconnect up to 8 Masters and 16 Slaves.
Some of the main features are:
- Up to 8 Masters
- Up to 16 Slaves
- 1, 2 or 4 priority levels
- Fully configurable
Copyright (C) 2000-2017, ASICs World Services, LTD. All rights reserved. Redistribution and use in source, netlist, binary and silicon forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of ASICS World Services, the Authors and/or the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Data Sheet
Project Web Site
https://github.com/www-asics-ws/wb_conmax.git
Issue Tracker
Last activity 3 years ago
Primary language: Verilog-SystemVerilog
3 commits by 2 contributors
https://github.com/www-asics-ws/wb_conmax.git
Issue Tracker
Last activity 3 years ago
Primary language: Verilog-SystemVerilog
3 commits by 2 contributors
activity over the last year
LibreCores data updated 7 months ago