WISHBONE Interconnect IP Core by www-asics-ws

WISHBONE Interconnect

wb_conmax

WISHBONE Interconnect

This is a WISHBONE Interconnect Matrix IP core.It can interconnect up to 8 Masters and 16 Slaves.

Some of the main features are:

  • Up to 8 Masters
  • Up to 16 Slaves
  • 1, 2 or 4 priority levels
  • Fully configurable
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Redistribution and use in source, netlist, binary and silicon forms, with
or without modification, are permitted provided that the following conditions
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     this software without specific prior written permission.

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Project Meta

  • Registered 1 year ago
  • Started 1 year ago
  • Last commit 1 year ago

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{"labels":[2017,2018],"series":[["3",null]]}

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{"labels":[2017,2018],"series":[["2",null]]}

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{"labels":["Others","Verilog-SystemVerilog","make","Markdown"],"series":[0,14,1,1]}

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Data Sheet
Project Web Site
https://github.com/www-asics-ws/wb_conmax.git
Issue Tracker
Last updated 1 year ago
Language: Verilog-SystemVerilog
3 commits by 2 contributors
www-asics-ws Rudolf Usselmann

Activity in last 1 year

Updated 1 year ago