Common SV RTL Files by ynwa

Open source RTL codes. 
1. This repository contains common RTL design files, which can be used in hardware design. 
2. Language Used: SystemVerilog.

Project Meta

  • Registered on LibreCores 8 months ago
  • Project started 8 months ago
  • Last commit 7 months ago

Commits

{"labels":[2020,2021],"series":[[9,0]]}

Commits per year

Contributors

{"labels":[2020,2021],"series":[[1,0]]}

Unique contributors per year

Releases

Data not available

Languages

{"labels":["Others","Verilog-SystemVerilog"],"series":[0,8]}

Share of languages used

Data Sheet
Project Web Site
https://github.com/micky-bank/rtl_design.git
Issue Tracker
Last activity 7 months ago
Primary language: Verilog-SystemVerilog
1 watcher
9 commits by 1 contributor
Micky Bank
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,1,3,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

activity over the last year

LibreCores data updated 7 months ago