1. This repository contains common RTL design files, which can be used in hardware design. 2. Language Used: SystemVerilog.
Data Sheet
Project Web Site
https://github.com/micky-bank/rtl_design.git
Issue Tracker
Last activity 4 months ago
Primary language: Verilog-SystemVerilog
1 watcher
9 commits by 1 contributor
https://github.com/micky-bank/rtl_design.git
Issue Tracker
Last activity 4 months ago
Primary language: Verilog-SystemVerilog
1 watcher
9 commits by 1 contributor
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activity over the last year
LibreCores data updated 4 months ago