NEORV32 (RISC-V) by zerogravity
The NEORV32 RISC-V Processor
- FPGA Implementation Results
- Software Framework & Tooling
- Getting Started :rocket:
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at +24 MHz.
Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. Whenever an unexpected situation occurs the application code is informed via precise and resumable hardware exceptions.
:interrobang: Want to know more? Check out the project's rationale.
:package: Exemplary setups targeting various FPGA boards and toolchains to get you started.
:heavy_check_mark: Automatic check for RISC-V specification compliance.
:kite: Supported by upstream Zephyr OS and FreeRTOS.
:bulb: Feel free to open a new issue or start a new discussion if you have questions, comments, ideas or if something is not working as expected. Or have a chat on our gitter channel. See how to contribute.
Project Key Features
- [x] all-in-one package: CPU + SoC + Software Framework & Tooling
- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
- [x] extensive configuration options for adapting the processor to the requirements of the application
- [x] highly extensible hardware - on CPU, SoC and system level
- [x] aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-performance trade-off
- [x] optimized for high clock frequency to ease timing closure
- [x] from zero to "hello world!" - completely open source and documented
- [x] easy to use even for FPGA/RISC-V starters – intended to work out of the box
The NEORV32 is fully operational.
The processor passes the official RISC-V architecture tests, which are checked by the
neorv32-verif repository. It can successfully run any C program
(for example from the
sw/example folder) including CoreMark
and FreeRTOS and can be synthesized for any target technology - tested on Intel, Xilinx and Lattice FPGAs.
The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU. By using generics the design is highly configurable and allows a flexible customization to tailor the setup according to your needs. The following list shows all available SoC module. Note that all those modules are optional.
- 32-bit little-endian RISC-V single-core, pipelined/multi-cycle Von-Neumann architecture
- configurable ISA extensions
- compatible to subsets of the Unprivileged ISA Specification (Version 2.2) and the Privileged Architecture Specification (Version 1.12).
- implements all standard RISC-V exceptions/interrupts (including MTI, MEI & MSI)
- 16 fast interrupt request channels as NEORV32-specific extension
- processor-internal data and instruction memories (DMEM / IMEM) & cache (iCACHE)
- pre-installed bootloader (BOOTLDROM) with serial user interface
- allows booting application code via UART or from external SPI flash
- machine system timer, 64-bit (MTIME), RISC-V spec. compatible
- general purpose 32-bit timer (GPTMR)
- watchdog timer (WDT)
Input / Output
- standard serial interfaces (UART, SPI, TWI)
- general purpose GPIO and PWM
- smart LED interface (NEOLED) to directly control NeoPixel(TM) LEDs
- 32-bit external bus interface, Wishbone b4 compatible
- wrappers for AXI4-Lite and Avalon-MM host interfaces
- 32-bit stream link interface with up to 8 independent RX and TX links (SLINK) - AXI4-Stream compatible
- external interrupts controller with up to 32 channels (XIRQ)
- true random number generator (TRNG) based on the neoTRNG
- execute in place module (XIP) to directly execute code from SPI flash
- custom functions subsystem (CFS) for tightly-coupled custom accelerators and interfaces
- custom functions unit (CFU) for up to 1024 custom RISC-V instructions
- on-chip debugger (OCD) accessible via standard JTAG interface
- compliant to the "Minimal RISC-V Debug Specification Version 0.13.2"
- compatible with OpenOCD + gdb and Segger Embedded Studio
Zmmul RISC-V ISA extensions are frozen and officially ratified but there is no
upstream gcc support yet (will be available with GCC12). To circumvent this, the NEORV32 software framework provides
intrinsic libraries for the
3. FPGA Implementation Results
Implementation results for exemplary CPU-only configuration generated for an Intel Cyclone IV E
using Intel Quartus Prime Lite 21.1 (no timing constrains, balanced optimization, f_max from Slow 1200mV 0C Model).
|CPU Configuration (version 126.96.36.199)||LEs||FFs||Memory bits||DSPs||f_max|
:bulb: An incremental list of the CPU extensions and the Processor modules found in the [Data Sheet: FPGA Implementation Results]https://stnolting.github.io/neorv32/#_fpga_implementation_results).
neorv32-setups repository provides exemplary FPGA
setups targeting various FPGA boards and toolchains.
The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute). The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available CPU extensions.
The following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing 2000 iterations of the CoreMark CPU benchmark (using plain GCC10 rv32i built-in libraries only!).
|CPU Configuration (version 188.8.131.52)||CoreMark Score||CoreMarks/MHz||Average CPI|
:bulb: More information regarding the CPU performance can be found in the Data Sheet: CPU Performance. The CPU & SoC provide further "tuning" options to optimize the design for maximum performance, maximum clock speed, minimal area or minimal power consumption: UG: Application-Specific Processor Configuration
5. Software Framework and Tooling
- core libraries for high-level usage of the provided functions and peripherals
- application compilation based on GNU makefiles
- gcc-based toolchain (pre-compiled toolchains available)
- SVD file for advanced debugging and IDE integration
- bootloader with UART interface console
- runtime environment for handling traps
- several example programs to get started including CoreMark, FreeRTOS and Conway's Game of Life
- doxygen-based documentation, available on GitHub pages
- supports implementation using open source toolchains - both, software and hardware can be developed and debugged with open source tools (GHDL, Yosys, nextpnr, openOCD, gtkwave, ...)
- continuous integration is available for:
:books: Want to know more? Check out Data Sheet: Software Framework.
6. Getting Started
:electric_plug: Hardware Overview
:interrobang: Rationale - NEORV32: Why? How come? What for?
NEORV32 Processor - the SoC
NEORV32 CPU - the CPU
:floppy_disk: Software Overview
- Example Programs - test program execution on your setup
- Core Libraries - high-level functions for accessing the processor's peripherals
- Software Framework Documentation - doxygen-based documentation
- Application Makefiles - turning your application into an executable
- Bootloader - the build-in NEORV32 bootloader
:rocket: User Guide
- Toolchain Setup - install and setup the RISC-V GCC toolchain
- General Hardware Setup - setup a new NEORV32 EDA project
- General Software Setup - configure the software framework
- Application Compilation - compile an application using make
- Upload via Bootloader - upload and execute executables
- Application-Specific Processor Configuration - tailor the processor to your needs
- Adding Custom Hardware Modules - add your custom hardware
- Debugging via the On-Chip Debugger - step through code online and in-system
- Simulation - simulate the whole SoC
- Hello World! - run a quick "hello world" simulation
- Overview - license, disclaimer, limitation of liability for external links, proprietary notice, ...
- Citing - citing information
This is an open-source project that is free of charge. Use this project in any way you like (as long as it complies to the permissive license). Please cite it appropriately. :+1:
:heart: A big shout-out to the community and all the contributors, who helped improving this project!
BSD 3-Clause License Copyright (c) 2022, Stephan Nolting All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.