NEORV32 (RISC-V) by zerogravity
The NEORV32 RISC-V Processor
- Processor/SoC Features
- CPU Features
- Software Framework & Tooling
- Getting Started :rocket:
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom / customizable microcontroller.
:information_source: Want to know more? Check out the project's rationale.
setups folder provides exemplary setups targeting
various FPGA boards and toolchains to get you started.
:spiral_notepad: Check out the project boards for a list of current ideas, TODOs, features being planned and work-in-progress.
Project Key Features
- CPU plus Processor/SoC plus Software Framework & Tooling
- completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
- fully synchronous design, no latches, no gated clocks
- be as small as possible (while being as RISC-V-compliant as possible) – but with a reasonable size-performance trade-off (the processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz)
- from zero to
printf("hello world!");- completely open source and documented
- easy to use even for FPGA/RISC-V starters – intended to work out of the box
NEORV32 Processor Features
The NEORV32 Processor (top entity:
provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics
to allow a flexible customization according to your needs. Note that all modules listed below are optional.
In-depth detailed information regarding the processor/SoC can be found in the :books:
online documentation - "NEORV32 Processors (SoC)".
- processor-internal data and instruction memories (DMEM / IMEM) & cache (iCACHE)
- bootloader (BOOTLDROM) with serial user interface
- supports boot via UART or from external SPI flash
- standard serial interfaces (UART, SPI, TWI / I²C)
- general purpose GPIO and PWM
- smart LED interface (NEOLED) to directly drive NeoPixel(TM) LEDs
SoC Connectivity and Integration
- 32-bit external bus interface, Wishbone b4 compatible
- wrapper for AXI4-Lite master interface
- 32-bit stram link interface with up to 8 independent RX and TX links
- AXI4-Stream compatible
- external interrupt controller with up to 32 channels (XIRQ)
- alternative top entities/wrappers providing simplified and/or resolved top entity ports for easy system integration
- custom functions subsystem (CFS) for tightly-coupled custom co-processor extensions
- true random number generator (TRNG)
- on-chip debugger (OCD) via JTGA - implementing the Minimal RISC-V Debug Specification Version 0.13.2 and compatible with OpenOCD and gdb
:information_source: It is recommended to use the processor setup even if you want to use the CPU in stand-alone mode. Just disable all optional processor-internal modules via the according generics and you will get a "CPU wrapper" that provides a minimal CPU environment and an external memory interface (like AXI4). This minimal setup allows to further use the default bootloader and software framework. From this base you can start building your own processor system.
FPGA Implementation Results - Processor
The hardware resources used by a specifc processor setup is defined by the implemented CPU extensions (see below), the configuration of the peripheral modules and some "glue logic". Section "FPGA Implementation Results - Processor Modules" of the online datasheet shows the ressource utilization of each optional processor module to allow an estimation of the actual setup's hardware requirements.
setups folder provides exemplary FPGA
setups targeting various FPGA boards and toolchains. These setups also provide ressource utilization reports for different
NEORV32 CPU Features
:books: In-depth detailed information regarding the CPU can be found in the online documentation - "NEORV32 Central Processing Unit".
The CPU (top entity:
implements the RISC-V 32-bit
rv32 ISA with optional extensions (see below). It is compatible to a subset of the
Unprivileged ISA Specification (Version 2.2)
and a subset of the Privileged Architecture Specification (Version 1.12-draft).
Compatiility is checked by passing the official RISC-V architecture tests
The core implements a little-endian von-Neumann architecture using two pipeline stages. Each stage uses a multi-cycle processing
scheme. The CPU supports three privilege levels (
machine and optional
debug_mode), three standard RISC-V machine
MSI), a single non-maskable interrupt plus 16 fast interrupt requests as custom extensions.
It also supports all standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
instruction, breakpoint, environment call). As a special "execution safety" extension, all invalid, reserved or
malformed instructions will raise an exception.
Available ISA Extensions
Currently, the following optional RISC-V-compatible ISA extensions are implemented (linked to the according
documentation section). Note that the
X extension is always enabled.
B ISA extension has been temporarily removed from the processor.
See B ISA Extension project board.
FPGA Implementation Results - CPU
Implementation results for exemplary CPU configuration generated for an Intel Cyclone IV EP4CE22F17C6N FPGA using Intel Quartus Prime Lite 20.1 ("balanced implementation"). The timing information is derived from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.
Results generated for hardware version
|CPU Configuration||LEs||FFs||Memory bits||DSPs (9-bit)||f_max|
:information_source: An incrmental list of CPU exntension's hardware utilization can found in online documentation - "FPGA Implementation Results - CPU".
:information_source: The CPU provides options to further reduce the footprint (for example by constraining the CPU-internal counters). See the online data sheet for more information.
The NEORV32 CPU is based on a two-stages pipelined architecutre. Since both stage use a multi-cycle processing scheme, each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions). The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available CPU extensions.
The following table shows the performance results (relative CoreMark score and average cycles per instruction) for
exemplary CPU configuration running 2000 iterations of the CoreMark CPU benchmark.
The source files are available in
**CoreMark Setup** Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain) Compiler flags: default, see makefile; optimization -O3
Results generated for hardware version
|CPU Configuration||CoreMark Score||CoreMarks/MHz||Average CPI|
:information_source: More information regarding the CPU performance can be found in the online documentation - "CPU Performance".
Software Framework and Tooling
:books: In-depth detailed information regarding the software framework can be found in the online documentation - "Software Framework".
- core libraries for high-level usage of the provided functions and peripherals
- application compilation based on GNU makefiles
- gcc-based toolchain (pre-compiled toolchains available)
- bootloader with UART interface console
- runtime environment for handling traps
- several example programs to get started including CoreMark, FreeRTOS and Conway's Game of Life
doxygen-based documentation, available on GitHub pages
- supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future Verilog-to-Routing); both, software and hardware can be developed and debugged with open source tooling
- continuous Integration is available for:
- allowing users to see the expected execution/output of the tools
- ensuring specification compliance
- catching regressions
- providing ready-to-use and up-to-date bitstreams and documentation
:electric_plug: Hardware Overview
Rationale - NEORV32: why, how come, what for
NEORV32 Processor - the SoC
NEORV32 CPU - the RISC-V core
:floppy_disk: Software Overview
- Core Libraries - high-level functions for accessing the processor's peripherals
- Software Framework Documentation -
- Software Framework Documentation -
- Application Makefiles - turning your application into an executable
- Bootloader - the build-in NEORV32 bootloader
:rocket: User Guides (see full User Guide)
- Toolchain Setup - install and setup RISC-V gcc
- General Hardware Setup - setup a new NEORV32 EDA project
- General Software Setup - configure the software framework
- Application Compilation - compile an application using
- Upload via Bootloader - upload and execute executables
- Debugging via the On-Chip Debugger - step through code online and in-system
- Overview - license, disclaimer, proprietary notice, ...
- Citing - citing information (DOI)
- Impressum - imprint (:de:)
A big shoutout to all contributors, who helped improving this project! :heart:
RISC-V - Instruction Sets Want To Be Free!
Made with :coffee: in Hannover, Germany :eu:
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