NEORV32 (RISC-V) by zerogravity

A customizable, lightweight and open-source 32-bit RISC-V soft-core microcontroller written in platform-independent VHDL.

NEORV32

The NEORV32 RISC-V Processor

datasheet (pdf) datasheet (html) userguide (pdf) userguide (html) doxygen Gitter

  1. Overview
  2. Features
  3. FPGA Implementation Results
  4. Performance
  5. Software Framework & Tooling
  6. Getting Started :rocket:

1. Overview

neorv32 Overview

The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at +24 MHz.

Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. Whenever an unexpected situation occurs the application code is informed via precise and resumable hardware exceptions.

:interrobang: Want to know more? Check out the project's rationale.

:books: For detailed information take a look at the NEORV32 online documentation. The latest PDF versions can be found here.

:label: The project's change log is available in CHANGELOG.md. To see the changes between official releases visit the project's release page.

:package: Exemplary setups targeting various FPGA boards and toolchains to get you started.

:heavy_check_mark: Automatic check for RISC-V specification compliance.

:kite: Supported by upstream Zephyr OS and FreeRTOS.

:bulb: Feel free to open a new issue or start a new discussion if you have questions, comments, ideas or if something is not working as expected. Or have a chat on our gitter channel. See how to contribute.

:rocket: Check out the quick links below or directly jump to the User Guide to get started setting up your NEORV32 setup!

Project Key Features

  • [x] all-in-one package: CPU + SoC + Software Framework & Tooling
  • [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
  • [x] extensive configuration options for adapting the processor to the requirements of the application
  • [x] highly extensible hardware - on CPU, SoC and system level
  • [x] aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-performance trade-off
  • [x] optimized for high clock frequency to ease timing closure
  • [x] from zero to "hello world!" - completely open source and documented
  • [x] easy to use even for FPGA/RISC-V starters – intended to work out of the box

Status

release GitHub Pages
Documentation riscv-arch-test Processor

The NEORV32 is fully operational. The processor passes the official RISC-V architecture tests, which are checked by the neorv32-verif repository. It can successfully run any C program (for example from the sw/example folder) including CoreMark and FreeRTOS and can be synthesized for any target technology - tested on Intel, Xilinx and Lattice FPGAs.

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2. Features

The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU. By using generics the design is highly configurable and allows a flexible customization to tailor the setup according to your needs. The following list shows all available SoC module. Note that all those modules are optional.

CPU

  • 32-bit little-endian RISC-V single-core, pipelined/multi-cycle Von-Neumann architecture
  • configurable ISA extensions
  • compatible to subsets of the Unprivileged ISA Specification (Version 2.2) and the Privileged Architecture Specification (Version 1.12).
  • machine and user modes
  • implements all standard RISC-V exceptions/interrupts (including MTI, MEI & MSI)
  • 16 fast interrupt request channels as NEORV32-specific extension

Memory

  • processor-internal data and instruction memories (DMEM / IMEM) & cache (iCACHE)
  • pre-installed bootloader (BOOTLDROM) with serial user interface
    • allows booting application code via UART or from external SPI flash

Timers

  • machine system timer, 64-bit (MTIME), RISC-V spec. compatible
  • general purpose 32-bit timer (GPTMR)
  • watchdog timer (WDT)

Input / Output

  • standard serial interfaces (UART, SPI, TWI)
  • general purpose GPIO and PWM
  • smart LED interface (NEOLED) to directly control NeoPixel(TM) LEDs

SoC Connectivity

  • 32-bit external bus interface, Wishbone b4 compatible (WISHBONE)
    • wrappers for AXI4-Lite and Avalon-MM host interfaces
  • 32-bit stream link interface with up to 8 independent RX and TX links (SLINK) - AXI4-Stream compatible
  • external interrupts controller with up to 32 channels (XIRQ)

Advanced

  • true random number generator (TRNG) based on the neoTRNG
  • execute in place module (XIP) to directly execute code from SPI flash
  • custom functions subsystem (CFS) for tightly-coupled custom accelerators and interfaces
  • custom functions unit (CFU) for up to 1024 custom RISC-V instructions

Debugging

  • on-chip debugger (OCD) accessible via standard JTAG interface
  • compliant to the "Minimal RISC-V Debug Specification Version 0.13.2"
  • compatible with OpenOCD + gdb and Segger Embedded Studio

:warning: The B, Zfinx and Zmmul RISC-V ISA extensions are frozen and officially ratified but there is no upstream gcc support yet (will be available with GCC12). To circumvent this, the NEORV32 software framework provides intrinsic libraries for the B and Zfinx extensions.

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3. FPGA Implementation Results

Implementation results for exemplary CPU-only configuration generated for an Intel Cyclone IV E EP4CE22F17C6 FPGA using Intel Quartus Prime Lite 21.1 (no timing constrains, balanced optimization, f_max from Slow 1200mV 0C Model).

CPU Configuration (version 1.6.9.8) LEs FFs Memory bits DSPs f_max
rv32i_Zicsr 1328 678 1024 0 128 MHz
rv32i_Zicsr_Zicntr 1614 808 1024 0 128 MHz
rv32imc_Zicsr_Zicntr 2338 992 1024 0 128 MHz

:bulb: An incremental list of the CPU extensions and the Processor modules found in the [Data Sheet: FPGA Implementation Results]https://stnolting.github.io/neorv32/#_fpga_implementation_results).

:bulb: The neorv32-setups repository provides exemplary FPGA setups targeting various FPGA boards and toolchains.

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4. Performance

The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute). The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available CPU extensions.

The following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing 2000 iterations of the CoreMark CPU benchmark (using plain GCC10 rv32i built-in libraries only!).

CPU Configuration (version 1.5.7.10) CoreMark Score CoreMarks/MHz Average CPI
small (rv32i_Zicsr) 33.89 0.3389 4.04
medium (rv32imc_Zicsr) 62.50 0.6250 5.34
performance (rv32imc_Zicsr + perf. options) 95.23 0.9523 3.54

:bulb: More information regarding the CPU performance can be found in the Data Sheet: CPU Performance. The CPU & SoC provide further "tuning" options to optimize the design for maximum performance, maximum clock speed, minimal area or minimal power consumption: UG: Application-Specific Processor Configuration

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5. Software Framework and Tooling

  • core libraries for high-level usage of the provided functions and peripherals
  • application compilation based on GNU makefiles
  • gcc-based toolchain (pre-compiled toolchains available)
  • SVD file for advanced debugging and IDE integration
  • bootloader with UART interface console
  • runtime environment for handling traps
  • several example programs to get started including CoreMark, FreeRTOS and Conway's Game of Life
  • doxygen-based documentation, available on GitHub pages
  • supports implementation using open source toolchains - both, software and hardware can be developed and debugged with open source tools (GHDL, Yosys, nextpnr, openOCD, gtkwave, ...)
  • continuous integration is available for:

:books: Want to know more? Check out Data Sheet: Software Framework.

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6. Getting Started

This overview provides some quick links to the most important sections of the online Data Sheet and the online User Guide.

:electric_plug: Hardware Overview

:floppy_disk: Software Overview

:rocket: User Guide

:copyright: Legal

license DOI

  • Overview - license, disclaimer, limitation of liability for external links, proprietary notice, ...
  • Citing - citing information

This is an open-source project that is free of charge. Use this project in any way you like (as long as it complies to the permissive license). Please cite it appropriately. :+1:

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:heart: A big shout-out to the community and all the contributors, who helped improving this project!

BSD 3-Clause License

Copyright (c) 2022, Stephan Nolting
All rights reserved.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this
   list of conditions and the following disclaimer.

2. Redistributions in binary form must reproduce the above copyright notice,
   this list of conditions and the following disclaimer in the documentation
   and/or other materials provided with the distribution.

3. Neither the name of the copyright holder nor the names of its
   contributors may be used to endorse or promote products derived from
   this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Project Meta

  • Registered on LibreCores 1 year ago
  • Project started 1 year ago
  • Last commit 9 hours ago

Commits

{"labels":[2020,2021,2022],"series":[[818,2140,622]]}

Commits per year

Contributors

{"labels":[2020,2021,2022],"series":[[1,20,7]]}

Unique contributors per year

Releases

v1.7.1 is is the latest of 33 releases.

  • v1.7.1
    Apr 25, 2022 d1b15fc
  • v1.7.0
    Apr 8, 2022 15a11c9
  • v1.6.9
    Mar 9, 2022 f0138c9
  • v1.6.8
    Feb 17, 2022 27d24eb
  • v1.6.7
    Jan 28, 2022 a4a66a3
  • v1.6.6
    Jan 17, 2022 49c70c3
  • v1.6.5
    Dec 16, 2021 26bbea5
  • v1.6.4
    Nov 26, 2021 8ba3999
  • v1.6.3
    Nov 2, 2021 874ed98
  • v1.6.2
    Oct 17, 2021 f1fadaa
  • v1.6.1
    Sep 28, 2021 c938c6c
  • v1.6.0
    Sep 11, 2021 eb4ba9f
  • v1.5.9
    Aug 13, 2021 8bf4b70
  • v1.5.8
    Jul 22, 2021 984966c
  • v1.5.7
    Jun 23, 2021 569e8d7
  • v1.5.6.0
    Jun 1, 2021 2723525
  • v1.5.5.0
    May 10, 2021 a2e306e
  • v1.5.4.0
    Apr 17, 2021 e4036f6
  • v1.5.3.0
    Mar 24, 2021 9254366
  • v1.5.2.0
    Mar 1, 2021 9a2919d
  • v1.5.1.0
    Feb 7, 2021 0a21b7c
  • v1.5.0.0
    Jan 11, 2021 085fa53
  • v1.4.9.0
    Dec 20, 2020 9a96ee4
  • v1.4.8.0
    Dec 1, 2020 9240306
  • v1.4.7.0
    Nov 11, 2020 d27150c
  • v1.4.6.0
    Oct 24, 2020 c9d213b
  • v1.4.5.0
    Oct 13, 2020 cd48d5a
  • v1.4.4.0
    Oct 5, 2020 e203f1f
  • v1.4.3.0
    Sep 17, 2020 284c5a9
  • v1.4.0.0
    Aug 29, 2020 1f85fe4
  • v1.3.7.0
    Aug 14, 2020 54283c1
  • v1.3.6.0
    Aug 3, 2020 7a760cc
  • v1.2.0.5
    Jul 20, 2020 4a2f859

Languages

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Share of languages used

Data Sheet
Project Web Site
https://github.com/stnolting/neorv32.git
Issue Tracker
Last activity 9 hours ago
v1.7.1 released 26 days ago
Primary language: VHDL
13 open issues
5 open pull requests
110 forks
40 watchers
824 stars
3580 commits by 25 contributors
Stephan umarcor stnolting zipotron Lars Asplund
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,86,65,120,96,61,30,58,49,38,14,8,28,38,47,2,15,39,51,30,25,54,49,44,57,56,17,12,38,57,44,15,11,0,85,13,26,84,38,34,44,38,38,17,24,1,27,36,9,25,18,16,17,32

activity over the last year

LibreCores data updated 9 hours ago